Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1426

1

T2

1

T3

1

T4

1

clear_one[1]

auto[0]

auto[0]

auto[0]

436

1

T2

1

T4

1

T14

1

clear_one[1]

auto[0]

auto[0]

auto[1]

101

1

T33

3

T77

1

T66

1

clear_one[1]

auto[0]

auto[1]

auto[0]

131

1

T2

1

T5

1

T16

1

clear_one[1]

auto[0]

auto[1]

auto[1]

51

1

T18

2

T149

1

T253

1

clear_one[2]

auto[0]

auto[0]

auto[0]

421

1

T3

3

T13

2

T16

1

clear_one[2]

auto[0]

auto[0]

auto[1]

123

1

T13

1

T33

1

T77

1

clear_one[2]

auto[1]

auto[0]

auto[0]

114

1

T4

2

T75

1

T104

1

clear_one[2]

auto[1]

auto[0]

auto[1]

40

1

T66

1

T68

1

T111

2

clear_one[3]

auto[0]

auto[0]

auto[0]

421

1

T13

1

T14

1

T33

1

clear_one[3]

auto[0]

auto[1]

auto[0]

102

1

T3

1

T74

1

T69

1

clear_one[3]

auto[1]

auto[0]

auto[0]

129

1

T4

1

T18

1

T75

1

clear_one[3]

auto[1]

auto[1]

auto[0]

40

1

T149

1

T68

1

T372

2

clear_none

auto[0]

auto[0]

auto[0]

1295

1

T2

2

T3

1

T4

1

clear_none

auto[0]

auto[0]

auto[1]

121

1

T13

4

T77

2

T107

1

clear_none

auto[0]

auto[1]

auto[0]

123

1

T3

2

T5

1

T74

1

clear_none

auto[0]

auto[1]

auto[1]

41

1

T18

2

T215

1

T68

1

clear_none

auto[1]

auto[0]

auto[0]

136

1

T4

2

T44

1

T73

1

clear_none

auto[1]

auto[0]

auto[1]

23

1

T67

1

T207

1

T68

2

clear_none

auto[1]

auto[1]

auto[0]

38

1

T128

1

T258

1

T394

1

clear_none

auto[1]

auto[1]

auto[1]

15

1

T18

1

T128

1

T111

2

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1325	1			T2	1		T3	1		T4	1
clear_all	auto[1]	101	1			T126	4		T128	1		T110	1
clear_one[1]	auto[0]	686	1			T2	2		T4	1		T5	1
clear_one[1]	auto[1]	33	1			T84	4		T113	3		T245	1
clear_one[2]	auto[0]	664	1			T3	3		T4	2		T13	2
clear_one[2]	auto[1]	34	1			T13	1		T126	2		T380	1
clear_one[3]	auto[0]	635	1			T3	1		T4	1		T14	1
clear_one[3]	auto[1]	57	1			T13	1		T84	10		T108	1
clear_none	auto[0]	1713	1			T2	2		T3	3		T4	3
clear_none	auto[1]	79	1			T13	8		T128	5		T110	4