Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10749

1

T1

7

T2

14

T3

5

auto[Attestation]

7402

1

T1

2

T2

4

T3

3

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2660	1			T1	1		T2	2		T5	4
auto[Aes]	3243	1			T2	2		T4	8		T5	5
auto[Kmac]	3314	1			T1	2		T2	3		T3	8
auto[Otbn]	3279	1			T1	3		T2	3		T5	3

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7359	1			T1	8		T2	8		T3	8
auto[OpGenId]	5655	1			T1	3		T2	8		T5	9
auto[OpGenSwOut]	5584	1			T1	6		T2	8		T5	11
auto[OpGenHwOut]	6912	1			T2	2		T3	8		T4	8
auto[OpDisable]	148	1			T14	1		T18	3		T78	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10288

1

T1

8

T2

8

T3

8

auto[OpDoneFail]

15370

1

T1

9

T2

18

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6151	1			T1	2		T2	11		T3	1
auto[StInit]	3617	1			T1	2		T2	2		T3	2
auto[StCreatorRootKey]	3088	1			T1	2		T2	2		T3	2
auto[StOwnerIntKey]	2621	1			T1	2		T2	2		T3	2
auto[StOwnerKey]	2395	1			T1	2		T2	2		T3	2
auto[StDisabled]	7786	1			T1	7		T2	7		T3	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	322	1			T1	1		T2	1		T15	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	92	1			T16	1		T203	1		T137	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	83	1			T16	1		T18	2		T69	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	65	1			T204	1		T205	1		T206	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	69	1			T13	1		T18	1		T104	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	198	1			T2	1		T14	1		T44	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	261	1			T2	1		T15	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	117	1			T13	1		T15	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	81	1			T13	1		T69	1		T67	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	66	1			T76	1		T25	1		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	40	1			T69	1		T128	1		T68	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	208	1			T14	1		T18	2		T72	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	342	1			T2	2		T17	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	80	1			T14	1		T18	1		T99	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	91	1			T69	1		T207	1		T68	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	66	1			T66	1		T67	1		T126	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	63	1			T1	1		T204	1		T208	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	214	1			T13	1		T16	2		T44	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	305	1			T2	2		T13	1		T15	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	90	1			T1	1		T18	1		T99	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	90	1			T1	1		T72	1		T69	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	75	1			T84	1		T25	1		T68	4
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	63	1			T44	1		T209	1		T68	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	211	1			T1	1		T5	1		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	63	1			T18	1		T68	2		T189	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	98	1			T5	2		T66	1		T204	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	74	1			T84	1		T203	1		T210	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	72	1			T18	1		T108	1		T68	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	53	1			T5	1		T69	2		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	206	1			T5	1		T13	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	64	1			T18	1		T189	1		T147	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	103	1			T13	1		T200	1		T79	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	62	1			T18	1		T69	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	66	1			T5	1		T18	1		T67	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	63	1			T13	1		T72	1		T76	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	190	1			T5	1		T16	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	68	1			T18	1		T68	4		T189	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	89	1			T18	2		T84	1		T66	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	100	1			T15	1		T25	3		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	71	1			T25	1		T108	1		T109	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	44	1			T36	1		T37	1		T211	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	225	1			T1	1		T5	2		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	64	1			T18	1		T68	3		T147	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	86	1			T34	1		T66	1		T137	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	94	1			T2	1		T16	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	69	1			T5	1		T13	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	46	1			T44	1		T69	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	222	1			T5	1		T16	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	268	1			T15	1		T28	2		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	89	1			T208	1		T37	1		T68	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	82	1			T76	1		T36	1		T69	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	60	1			T18	1		T76	1		T66	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	52	1			T18	1		T66	1		T109	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	193	1			T13	2		T18	4		T84	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	513	1			T2	1		T13	1		T15	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	112	1			T4	1		T18	1		T84	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	109	1			T4	1		T14	1		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	79	1			T44	1		T18	1		T75	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	95	1			T18	2		T208	1		T67	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	294	1			T4	3		T18	1		T73	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	412	1			T17	2		T18	1		T212	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	117	1			T3	1		T13	1		T74	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	105	1			T3	1		T18	1		T74	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	77	1			T3	1		T16	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	97	1			T5	1		T18	1		T74	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	298	1			T2	1		T3	2		T18	5
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	466	1			T17	2		T28	1		T18	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	121	1			T33	1		T18	2		T66	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	93	1			T33	1		T69	1		T66	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	80	1			T77	1		T25	1		T211	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	84	1			T33	1		T76	2		T77	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	284	1			T33	2		T18	1		T77	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	48	1			T66	2		T68	1		T111	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	114	1			T14	1		T15	1		T18	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	62	1			T13	1		T68	1		T94	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	67	1			T36	1		T66	1		T208	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	55	1			T13	1		T76	1		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	175	1			T16	1		T18	1		T76	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	43	1			T18	1		T66	1		T154	4
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	110	1			T16	1		T18	1		T75	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	108	1			T75	1		T106	1		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	99	1			T4	1		T76	1		T84	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	73	1			T4	1		T18	1		T75	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	287	1			T4	1		T5	3		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	64	1			T18	1		T66	2		T111	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	105	1			T66	1		T214	1		T215	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	102	1			T125	1		T212	1		T214	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	105	1			T5	1		T105	1		T66	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	90	1			T3	1		T16	1		T204	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	289	1			T3	2		T18	2		T74	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	57	1			T66	1		T189	1		T111	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	107	1			T18	2		T77	1		T66	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	106	1			T15	1		T125	1		T18	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	91	1			T33	1		T18	1		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	103	1			T18	2		T66	1		T208	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	272	1			T13	1		T16	1		T33	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	208	1			T13	1		T16	1		T18	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	621	1			T1	1		T2	2		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	182	1			T13	1		T76	1		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	591	1			T2	1		T13	1		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	211	1			T1	1		T69	1		T66	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	645	1			T2	2		T13	1		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	208	1			T1	1		T44	1		T72	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	626	1			T1	2		T2	2		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	182	1			T5	1		T18	1		T84	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	384	1			T5	3		T13	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	179	1			T5	1		T13	1		T18	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	369	1			T5	1		T13	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	201	1			T15	1		T25	3		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	396	1			T1	1		T5	2		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	193	1			T2	1		T5	1		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	388	1			T5	1		T16	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	182	1			T18	2		T76	2		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	562	1			T13	2		T15	1		T28	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	266	1			T4	1		T14	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	936	1			T2	1		T4	4		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	267	1			T3	2		T5	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	839	1			T2	1		T3	3		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	245	1			T33	2		T76	2		T77	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	883	1			T17	2		T33	3		T28	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	169	1			T13	2		T76	1		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	352	1			T14	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	267	1			T4	2		T75	2		T76	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	453	1			T4	1		T5	3		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	285	1			T3	1		T5	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	470	1			T3	2		T18	3		T74	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	282	1			T15	1		T33	1		T125	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	454	1			T13	1		T16	1		T33	2