Unified Coverage Report :: Group Instance : attest_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31725

1

T1

23

T2

29

T3

20

auto[1]

315

1

T13

10

T84

7

T108

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31736	1			T1	23		T2	29		T3	20
auto[134217728:268435455]	7	1			T368	3		T419	1		T382	1
auto[268435456:402653183]	8	1			T13	1		T296	1		T280	1
auto[402653184:536870911]	9	1			T110	1		T113	1		T245	1
auto[536870912:671088639]	14	1			T128	1		T114	1		T380	1
auto[671088640:805306367]	11	1			T244	1		T114	1		T420	1
auto[805306368:939524095]	10	1			T108	2		T110	1		T380	1
auto[939524096:1073741823]	8	1			T13	1		T110	1		T328	1
auto[1073741824:1207959551]	14	1			T13	1		T128	1		T110	1
auto[1207959552:1342177279]	10	1			T84	1		T108	1		T110	1
auto[1342177280:1476395007]	9	1			T113	1		T286	1		T421	1
auto[1476395008:1610612735]	6	1			T128	1		T110	1		T293	1
auto[1610612736:1744830463]	8	1			T84	1		T114	1		T380	2
auto[1744830464:1879048191]	14	1			T244	1		T328	1		T380	1
auto[1879048192:2013265919]	8	1			T13	1		T380	1		T399	1
auto[2013265920:2147483647]	8	1			T110	1		T112	1		T368	1
auto[2147483648:2281701375]	10	1			T244	1		T114	1		T380	1
auto[2281701376:2415919103]	15	1			T244	1		T380	1		T247	1
auto[2415919104:2550136831]	7	1			T13	1		T244	2		T399	1
auto[2550136832:2684354559]	5	1			T128	1		T244	1		T296	1
auto[2684354560:2818572287]	9	1			T13	1		T380	1		T399	1
auto[2818572288:2952790015]	8	1			T244	1		T113	1		T328	1
auto[2952790016:3087007743]	11	1			T84	1		T244	1		T380	2
auto[3087007744:3221225471]	14	1			T13	1		T128	1		T328	1
auto[3221225472:3355443199]	18	1			T84	4		T112	1		T380	1
auto[3355443200:3489660927]	10	1			T244	1		T112	1		T114	1
auto[3489660928:3623878655]	4	1			T360	1		T341	1		T419	2
auto[3623878656:3758096383]	3	1			T328	1		T296	1		T242	1
auto[3758096384:3892314111]	11	1			T13	2		T244	1		T324	1
auto[3892314112:4026531839]	11	1			T110	1		T245	1		T114	1
auto[4026531840:4160749567]	14	1			T110	1		T113	2		T328	1
auto[4160749568:4294967295]	10	1			T324	2		T325	1		T308	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31725	1			T1	23		T2	29		T3	20
auto[0:134217727]	auto[1]	11	1			T13	1		T280	1		T337	1
auto[134217728:268435455]	auto[1]	7	1			T368	3		T419	1		T382	1
auto[268435456:402653183]	auto[1]	8	1			T13	1		T296	1		T280	1
auto[402653184:536870911]	auto[1]	9	1			T110	1		T113	1		T245	1
auto[536870912:671088639]	auto[1]	14	1			T128	1		T114	1		T380	1
auto[671088640:805306367]	auto[1]	11	1			T244	1		T114	1		T420	1
auto[805306368:939524095]	auto[1]	10	1			T108	2		T110	1		T380	1
auto[939524096:1073741823]	auto[1]	8	1			T13	1		T110	1		T328	1
auto[1073741824:1207959551]	auto[1]	14	1			T13	1		T128	1		T110	1
auto[1207959552:1342177279]	auto[1]	10	1			T84	1		T108	1		T110	1
auto[1342177280:1476395007]	auto[1]	9	1			T113	1		T286	1		T421	1
auto[1476395008:1610612735]	auto[1]	6	1			T128	1		T110	1		T293	1
auto[1610612736:1744830463]	auto[1]	8	1			T84	1		T114	1		T380	2
auto[1744830464:1879048191]	auto[1]	14	1			T244	1		T328	1		T380	1
auto[1879048192:2013265919]	auto[1]	8	1			T13	1		T380	1		T399	1
auto[2013265920:2147483647]	auto[1]	8	1			T110	1		T112	1		T368	1
auto[2147483648:2281701375]	auto[1]	10	1			T244	1		T114	1		T380	1
auto[2281701376:2415919103]	auto[1]	15	1			T244	1		T380	1		T247	1
auto[2415919104:2550136831]	auto[1]	7	1			T13	1		T244	2		T399	1
auto[2550136832:2684354559]	auto[1]	5	1			T128	1		T244	1		T296	1
auto[2684354560:2818572287]	auto[1]	9	1			T13	1		T380	1		T399	1
auto[2818572288:2952790015]	auto[1]	8	1			T244	1		T113	1		T328	1
auto[2952790016:3087007743]	auto[1]	11	1			T84	1		T244	1		T380	2
auto[3087007744:3221225471]	auto[1]	14	1			T13	1		T128	1		T328	1
auto[3221225472:3355443199]	auto[1]	18	1			T84	4		T112	1		T380	1
auto[3355443200:3489660927]	auto[1]	10	1			T244	1		T112	1		T114	1
auto[3489660928:3623878655]	auto[1]	4	1			T360	1		T341	1		T419	2
auto[3623878656:3758096383]	auto[1]	3	1			T328	1		T296	1		T242	1
auto[3758096384:3892314111]	auto[1]	11	1			T13	2		T244	1		T324	1
auto[3892314112:4026531839]	auto[1]	11	1			T110	1		T245	1		T114	1
auto[4026531840:4160749567]	auto[1]	14	1			T110	1		T113	2		T328	1
auto[4160749568:4294967295]	auto[1]	10	1			T324	2		T325	1		T308	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1534

1

T5

1

T13

2

T15

5

auto[1]

1734

1

T5

4

T13

5

T14

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	96	1			T14	1		T16	1		T18	2
auto[134217728:268435455]	93	1			T109	1		T71	1		T53	1
auto[268435456:402653183]	100	1			T52	1		T67	1		T207	1
auto[402653184:536870911]	110	1			T134	1		T254	1		T149	1
auto[536870912:671088639]	97	1			T18	1		T99	1		T48	2
auto[671088640:805306367]	100	1			T18	3		T99	1		T69	1
auto[805306368:939524095]	90	1			T5	1		T18	4		T66	1
auto[939524096:1073741823]	95	1			T66	2		T126	1		T70	1
auto[1073741824:1207959551]	103	1			T13	1		T15	1		T16	1
auto[1207959552:1342177279]	104	1			T5	2		T76	1		T48	1
auto[1342177280:1476395007]	108	1			T15	1		T16	1		T18	1
auto[1476395008:1610612735]	95	1			T17	1		T18	1		T99	1
auto[1610612736:1744830463]	98	1			T13	1		T35	1		T18	2
auto[1744830464:1879048191]	110	1			T35	1		T66	1		T128	1
auto[1879048192:2013265919]	95	1			T69	1		T215	1		T110	1
auto[2013265920:2147483647]	101	1			T13	1		T15	1		T28	1
auto[2147483648:2281701375]	90	1			T38	1		T69	1		T70	1
auto[2281701376:2415919103]	107	1			T15	1		T125	1		T66	1
auto[2415919104:2550136831]	107	1			T15	1		T17	1		T99	1
auto[2550136832:2684354559]	92	1			T18	1		T25	1		T38	1
auto[2684354560:2818572287]	98	1			T35	1		T18	2		T48	1
auto[2818572288:2952790015]	106	1			T17	1		T18	2		T76	2
auto[2952790016:3087007743]	104	1			T18	2		T84	1		T25	1
auto[3087007744:3221225471]	109	1			T15	2		T69	1		T53	1
auto[3221225472:3355443199]	108	1			T5	1		T13	2		T18	1
auto[3355443200:3489660927]	111	1			T18	1		T99	1		T134	1
auto[3489660928:3623878655]	100	1			T18	2		T84	1		T212	1
auto[3623878656:3758096383]	102	1			T69	1		T66	1		T126	1
auto[3758096384:3892314111]	104	1			T5	1		T13	2		T76	1
auto[3892314112:4026531839]	108	1			T78	1		T134	1		T66	1
auto[4026531840:4160749567]	114	1			T99	1		T48	2		T38	1
auto[4160749568:4294967295]	113	1			T18	1		T76	1		T48	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T69	1		T128	1		T110	1
auto[0:134217727]	auto[1]	53	1			T14	1		T16	1		T18	2
auto[134217728:268435455]	auto[0]	50	1			T53	1		T80	1		T29	1
auto[134217728:268435455]	auto[1]	43	1			T109	1		T71	1		T68	2
auto[268435456:402653183]	auto[0]	52	1			T52	1		T68	2		T111	1
auto[268435456:402653183]	auto[1]	48	1			T67	1		T207	1		T42	1
auto[402653184:536870911]	auto[0]	61	1			T68	1		T358	1		T29	2
auto[402653184:536870911]	auto[1]	49	1			T134	1		T254	1		T149	1
auto[536870912:671088639]	auto[0]	42	1			T99	1		T48	1		T254	1
auto[536870912:671088639]	auto[1]	55	1			T18	1		T48	1		T25	1
auto[671088640:805306367]	auto[0]	40	1			T18	1		T69	1		T66	1
auto[671088640:805306367]	auto[1]	60	1			T18	2		T99	1		T66	1
auto[805306368:939524095]	auto[0]	33	1			T66	1		T137	1		T68	1
auto[805306368:939524095]	auto[1]	57	1			T5	1		T18	4		T67	1
auto[939524096:1073741823]	auto[0]	52	1			T66	2		T126	1		T70	1
auto[939524096:1073741823]	auto[1]	43	1			T68	1		T110	1		T111	1
auto[1073741824:1207959551]	auto[0]	48	1			T17	1		T48	1		T137	1
auto[1073741824:1207959551]	auto[1]	55	1			T13	1		T15	1		T16	1
auto[1207959552:1342177279]	auto[0]	50	1			T76	1		T48	1		T68	1
auto[1207959552:1342177279]	auto[1]	54	1			T5	2		T109	1		T67	1
auto[1342177280:1476395007]	auto[0]	46	1			T15	1		T18	1		T136	1
auto[1342177280:1476395007]	auto[1]	62	1			T16	1		T134	1		T66	2
auto[1476395008:1610612735]	auto[0]	49	1			T17	1		T18	1		T48	1
auto[1476395008:1610612735]	auto[1]	46	1			T99	1		T108	1		T137	1
auto[1610612736:1744830463]	auto[0]	53	1			T35	1		T134	1		T126	1
auto[1610612736:1744830463]	auto[1]	45	1			T13	1		T18	2		T99	1
auto[1744830464:1879048191]	auto[0]	53	1			T35	1		T66	1		T68	2
auto[1744830464:1879048191]	auto[1]	57	1			T128	1		T68	3		T80	1
auto[1879048192:2013265919]	auto[0]	45	1			T69	1		T110	1		T244	1
auto[1879048192:2013265919]	auto[1]	50	1			T215	1		T26	1		T422	1
auto[2013265920:2147483647]	auto[0]	39	1			T13	1		T15	1		T28	1
auto[2013265920:2147483647]	auto[1]	62	1			T18	2		T69	1		T66	3
auto[2147483648:2281701375]	auto[0]	41	1			T70	1		T205	1		T68	1
auto[2147483648:2281701375]	auto[1]	49	1			T38	1		T69	1		T68	1
auto[2281701376:2415919103]	auto[0]	53	1			T15	1		T66	1		T68	1
auto[2281701376:2415919103]	auto[1]	54	1			T125	1		T210	1		T94	1
auto[2415919104:2550136831]	auto[0]	47	1			T17	1		T99	1		T6	1
auto[2415919104:2550136831]	auto[1]	60	1			T15	1		T109	1		T80	1
auto[2550136832:2684354559]	auto[0]	45	1			T38	1		T254	1		T253	1
auto[2550136832:2684354559]	auto[1]	47	1			T18	1		T25	1		T209	1
auto[2684354560:2818572287]	auto[0]	41	1			T66	1		T6	1		T68	1
auto[2684354560:2818572287]	auto[1]	57	1			T35	1		T18	2		T48	1
auto[2818572288:2952790015]	auto[0]	50	1			T17	1		T18	1		T76	1
auto[2818572288:2952790015]	auto[1]	56	1			T18	1		T76	1		T25	1
auto[2952790016:3087007743]	auto[0]	40	1			T25	1		T66	1		T71	1
auto[2952790016:3087007743]	auto[1]	64	1			T18	2		T84	1		T68	3
auto[3087007744:3221225471]	auto[0]	54	1			T15	2		T53	1		T68	1
auto[3087007744:3221225471]	auto[1]	55	1			T69	1		T207	1		T70	1
auto[3221225472:3355443199]	auto[0]	46	1			T52	1		T80	1		T253	1
auto[3221225472:3355443199]	auto[1]	62	1			T5	1		T13	2		T18	1
auto[3355443200:3489660927]	auto[0]	67	1			T18	1		T212	2		T69	2
auto[3355443200:3489660927]	auto[1]	44	1			T99	1		T134	1		T69	1
auto[3489660928:3623878655]	auto[0]	49	1			T18	1		T212	1		T71	1
auto[3489660928:3623878655]	auto[1]	51	1			T18	1		T84	1		T25	1
auto[3623878656:3758096383]	auto[0]	50	1			T69	1		T66	1		T206	1
auto[3623878656:3758096383]	auto[1]	52	1			T126	1		T149	1		T209	1
auto[3758096384:3892314111]	auto[0]	46	1			T5	1		T13	1		T76	1
auto[3758096384:3892314111]	auto[1]	58	1			T13	1		T84	1		T68	3
auto[3892314112:4026531839]	auto[0]	56	1			T134	1		T66	1		T71	1
auto[3892314112:4026531839]	auto[1]	52	1			T78	1		T128	1		T68	2
auto[4026531840:4160749567]	auto[0]	46	1			T99	1		T48	1		T69	1
auto[4026531840:4160749567]	auto[1]	68	1			T48	1		T38	1		T69	1
auto[4160749568:4294967295]	auto[0]	47	1			T76	1		T212	1		T68	2
auto[4160749568:4294967295]	auto[1]	66	1			T18	1		T48	1		T66	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1515

1

T5

1

T13

1

T15

4

auto[1]

1752

1

T5

4

T13

6

T14

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	115	1			T69	1		T66	1		T210	1
auto[134217728:268435455]	122	1			T15	1		T17	1		T18	3
auto[268435456:402653183]	113	1			T16	1		T69	1		T126	1
auto[402653184:536870911]	104	1			T99	1		T69	1		T6	1
auto[536870912:671088639]	96	1			T18	2		T134	1		T48	2
auto[671088640:805306367]	99	1			T14	1		T212	1		T69	1
auto[805306368:939524095]	92	1			T18	1		T38	1		T69	1
auto[939524096:1073741823]	105	1			T18	2		T69	1		T66	2
auto[1073741824:1207959551]	115	1			T76	1		T84	1		T99	1
auto[1207959552:1342177279]	95	1			T13	1		T76	1		T99	1
auto[1342177280:1476395007]	119	1			T5	1		T15	1		T18	1
auto[1476395008:1610612735]	95	1			T17	1		T28	1		T18	1
auto[1610612736:1744830463]	98	1			T15	1		T35	1		T76	1
auto[1744830464:1879048191]	108	1			T13	1		T18	2		T99	2
auto[1879048192:2013265919]	109	1			T13	1		T15	1		T35	1
auto[2013265920:2147483647]	91	1			T18	1		T76	1		T99	1
auto[2147483648:2281701375]	90	1			T76	1		T137	1		T302	1
auto[2281701376:2415919103]	102	1			T99	1		T69	1		T66	1
auto[2415919104:2550136831]	100	1			T13	1		T18	1		T69	2
auto[2550136832:2684354559]	104	1			T18	3		T84	1		T134	1
auto[2684354560:2818572287]	102	1			T15	1		T16	1		T35	1
auto[2818572288:2952790015]	119	1			T13	1		T16	1		T18	1
auto[2952790016:3087007743]	93	1			T13	1		T134	1		T66	2
auto[3087007744:3221225471]	98	1			T17	1		T18	2		T212	1
auto[3221225472:3355443199]	85	1			T15	1		T18	2		T134	1
auto[3355443200:3489660927]	93	1			T5	2		T18	2		T212	1
auto[3489660928:3623878655]	95	1			T15	1		T125	1		T18	3
auto[3623878656:3758096383]	99	1			T18	2		T78	1		T134	1
auto[3758096384:3892314111]	100	1			T48	1		T204	1		T67	1
auto[3892314112:4026531839]	112	1			T5	2		T13	1		T99	1
auto[4026531840:4160749567]	96	1			T17	1		T25	1		T69	1
auto[4160749568:4294967295]	103	1			T48	1		T25	1		T69	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T69	1		T66	1		T210	1
auto[0:134217727]	auto[1]	59	1			T302	1		T336	1		T246	1
auto[134217728:268435455]	auto[0]	57	1			T15	1		T17	1		T18	1
auto[134217728:268435455]	auto[1]	65	1			T18	2		T66	1		T136	1
auto[268435456:402653183]	auto[0]	59	1			T126	1		T209	1		T68	1
auto[268435456:402653183]	auto[1]	54	1			T16	1		T69	1		T127	1
auto[402653184:536870911]	auto[0]	51	1			T99	1		T69	1		T6	1
auto[402653184:536870911]	auto[1]	53	1			T68	2		T42	1		T50	1
auto[536870912:671088639]	auto[0]	40	1			T134	1		T48	2		T212	1
auto[536870912:671088639]	auto[1]	56	1			T18	2		T68	1		T50	1
auto[671088640:805306367]	auto[0]	44	1			T212	1		T136	1		T71	1
auto[671088640:805306367]	auto[1]	55	1			T14	1		T69	1		T206	1
auto[805306368:939524095]	auto[0]	44	1			T69	1		T126	1		T111	1
auto[805306368:939524095]	auto[1]	48	1			T18	1		T38	1		T248	1
auto[939524096:1073741823]	auto[0]	46	1			T18	1		T69	1		T52	1
auto[939524096:1073741823]	auto[1]	59	1			T18	1		T66	2		T108	1
auto[1073741824:1207959551]	auto[0]	56	1			T76	1		T99	1		T212	1
auto[1073741824:1207959551]	auto[1]	59	1			T84	1		T126	1		T68	3
auto[1207959552:1342177279]	auto[0]	51	1			T76	1		T99	1		T66	1
auto[1207959552:1342177279]	auto[1]	44	1			T13	1		T48	1		T25	1
auto[1342177280:1476395007]	auto[0]	55	1			T67	1		T253	1		T98	1
auto[1342177280:1476395007]	auto[1]	64	1			T5	1		T15	1		T18	1
auto[1476395008:1610612735]	auto[0]	50	1			T17	1		T28	1		T18	1
auto[1476395008:1610612735]	auto[1]	45	1			T66	1		T254	1		T207	1
auto[1610612736:1744830463]	auto[0]	35	1			T15	1		T76	1		T66	1
auto[1610612736:1744830463]	auto[1]	63	1			T35	1		T254	1		T207	1
auto[1744830464:1879048191]	auto[0]	54	1			T18	1		T71	1		T206	1
auto[1744830464:1879048191]	auto[1]	54	1			T13	1		T18	1		T99	2
auto[1879048192:2013265919]	auto[0]	47	1			T35	1		T66	2		T254	1
auto[1879048192:2013265919]	auto[1]	62	1			T13	1		T15	1		T18	1
auto[2013265920:2147483647]	auto[0]	42	1			T76	1		T69	1		T136	1
auto[2013265920:2147483647]	auto[1]	49	1			T18	1		T99	1		T48	1
auto[2147483648:2281701375]	auto[0]	42	1			T302	1		T147	1		T143	1
auto[2147483648:2281701375]	auto[1]	48	1			T76	1		T137	1		T394	1
auto[2281701376:2415919103]	auto[0]	51	1			T99	1		T136	1		T6	1
auto[2281701376:2415919103]	auto[1]	51	1			T69	1		T66	1		T248	1
auto[2415919104:2550136831]	auto[0]	47	1			T69	1		T137	1		T70	1
auto[2415919104:2550136831]	auto[1]	53	1			T13	1		T18	1		T69	1
auto[2550136832:2684354559]	auto[0]	37	1			T18	1		T134	1		T38	1
auto[2550136832:2684354559]	auto[1]	67	1			T18	2		T84	1		T53	1
auto[2684354560:2818572287]	auto[0]	45	1			T35	1		T69	1		T422	1
auto[2684354560:2818572287]	auto[1]	57	1			T15	1		T16	1		T84	1
auto[2818572288:2952790015]	auto[0]	57	1			T13	1		T16	1		T48	1
auto[2818572288:2952790015]	auto[1]	62	1			T18	1		T48	1		T215	1
auto[2952790016:3087007743]	auto[0]	44	1			T66	1		T210	1		T68	1
auto[2952790016:3087007743]	auto[1]	49	1			T13	1		T134	1		T66	1
auto[3087007744:3221225471]	auto[0]	43	1			T17	1		T18	1		T212	1
auto[3087007744:3221225471]	auto[1]	55	1			T18	1		T66	1		T108	1
auto[3221225472:3355443199]	auto[0]	35	1			T15	1		T18	1		T212	1
auto[3221225472:3355443199]	auto[1]	50	1			T18	1		T134	1		T149	1
auto[3355443200:3489660927]	auto[0]	47	1			T5	1		T212	1		T70	1
auto[3355443200:3489660927]	auto[1]	46	1			T5	1		T18	2		T149	1
auto[3489660928:3623878655]	auto[0]	42	1			T15	1		T18	1		T99	1
auto[3489660928:3623878655]	auto[1]	53	1			T125	1		T18	2		T25	1
auto[3623878656:3758096383]	auto[0]	36	1			T18	1		T66	1		T68	1
auto[3623878656:3758096383]	auto[1]	63	1			T18	1		T78	1		T134	1
auto[3758096384:3892314111]	auto[0]	51	1			T68	1		T42	1		T253	1
auto[3758096384:3892314111]	auto[1]	49	1			T48	1		T204	1		T67	1
auto[3892314112:4026531839]	auto[0]	53	1			T66	1		T137	1		T68	3
auto[3892314112:4026531839]	auto[1]	59	1			T5	2		T13	1		T99	1
auto[4026531840:4160749567]	auto[0]	47	1			T17	1		T189	1		T29	2
auto[4026531840:4160749567]	auto[1]	49	1			T25	1		T69	1		T149	1
auto[4160749568:4294967295]	auto[0]	51	1			T48	1		T25	1		T66	1
auto[4160749568:4294967295]	auto[1]	52	1			T69	1		T128	1		T68	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1535

1

T5

1

T13

1

T15

3

auto[1]

1734

1

T5

4

T13

6

T14

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	111	1			T99	1		T212	1		T66	1
auto[134217728:268435455]	115	1			T18	4		T212	1		T69	1
auto[268435456:402653183]	96	1			T15	1		T35	1		T125	1
auto[402653184:536870911]	114	1			T15	1		T76	1		T99	1
auto[536870912:671088639]	122	1			T5	1		T15	1		T18	3
auto[671088640:805306367]	114	1			T5	1		T13	1		T69	1
auto[805306368:939524095]	97	1			T15	1		T17	1		T84	1
auto[939524096:1073741823]	116	1			T16	1		T78	1		T84	1
auto[1073741824:1207959551]	93	1			T28	1		T18	1		T134	1
auto[1207959552:1342177279]	105	1			T48	1		T25	1		T254	1
auto[1342177280:1476395007]	106	1			T16	1		T99	2		T69	1
auto[1476395008:1610612735]	104	1			T13	1		T18	2		T99	1
auto[1610612736:1744830463]	95	1			T5	1		T18	1		T66	1
auto[1744830464:1879048191]	93	1			T66	1		T136	1		T70	1
auto[1879048192:2013265919]	90	1			T99	1		T69	2		T208	1
auto[2013265920:2147483647]	104	1			T18	1		T25	1		T254	1
auto[2147483648:2281701375]	81	1			T13	1		T212	1		T69	1
auto[2281701376:2415919103]	107	1			T18	1		T25	1		T108	1
auto[2415919104:2550136831]	113	1			T15	1		T16	1		T18	1
auto[2550136832:2684354559]	105	1			T18	3		T84	1		T69	1
auto[2684354560:2818572287]	97	1			T13	1		T15	1		T48	1
auto[2818572288:2952790015]	96	1			T17	1		T18	2		T99	1
auto[2952790016:3087007743]	99	1			T17	1		T28	1		T18	4
auto[3087007744:3221225471]	103	1			T13	2		T18	2		T38	1
auto[3221225472:3355443199]	93	1			T14	1		T76	1		T25	1
auto[3355443200:3489660927]	114	1			T13	1		T15	1		T76	1
auto[3489660928:3623878655]	96	1			T35	1		T76	1		T66	1
auto[3623878656:3758096383]	100	1			T5	1		T35	1		T76	1
auto[3758096384:3892314111]	97	1			T5	1		T18	2		T212	1
auto[3892314112:4026531839]	92	1			T48	1		T69	1		T66	2
auto[4026531840:4160749567]	97	1			T18	1		T99	1		T134	1
auto[4160749568:4294967295]	104	1			T17	1		T18	2		T204	1