Unified Coverage Report :: Group Instance : salt_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2884

1

T5

5

T13

7

T14

1

auto[1]

258

1

T13

13

T84

12

T108

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T17	1		T35	1		T84	1
auto[134217728:268435455]	94	1			T18	1		T25	1		T66	1
auto[268435456:402653183]	89	1			T13	1		T35	1		T18	2
auto[402653184:536870911]	93	1			T125	1		T48	1		T25	1
auto[536870912:671088639]	71	1			T13	1		T18	1		T76	1
auto[671088640:805306367]	102	1			T13	1		T18	2		T134	1
auto[805306368:939524095]	102	1			T18	2		T134	1		T69	1
auto[939524096:1073741823]	88	1			T5	1		T18	2		T48	1
auto[1073741824:1207959551]	81	1			T5	1		T13	1		T76	1
auto[1207959552:1342177279]	106	1			T15	1		T16	1		T69	1
auto[1342177280:1476395007]	103	1			T84	1		T66	1		T248	1
auto[1476395008:1610612735]	102	1			T13	1		T134	1		T48	2
auto[1610612736:1744830463]	98	1			T13	1		T16	2		T204	1
auto[1744830464:1879048191]	109	1			T13	2		T18	2		T84	1
auto[1879048192:2013265919]	114	1			T13	1		T18	1		T212	1
auto[2013265920:2147483647]	108	1			T5	1		T84	2		T134	1
auto[2147483648:2281701375]	114	1			T18	1		T84	2		T48	1
auto[2281701376:2415919103]	86	1			T13	2		T18	2		T84	1
auto[2415919104:2550136831]	95	1			T13	1		T18	1		T84	1
auto[2550136832:2684354559]	91	1			T84	1		T134	1		T66	2
auto[2684354560:2818572287]	101	1			T13	1		T17	1		T18	1
auto[2818572288:2952790015]	112	1			T13	3		T17	1		T84	1
auto[2952790016:3087007743]	109	1			T5	1		T35	1		T18	1
auto[3087007744:3221225471]	102	1			T13	1		T28	1		T18	1
auto[3221225472:3355443199]	77	1			T5	1		T76	1		T84	1
auto[3355443200:3489660927]	99	1			T18	1		T48	1		T212	1
auto[3489660928:3623878655]	95	1			T13	1		T14	1		T108	2
auto[3623878656:3758096383]	100	1			T18	1		T76	1		T78	1
auto[3758096384:3892314111]	92	1			T13	1		T18	1		T84	1
auto[3892314112:4026531839]	100	1			T15	1		T17	1		T109	1
auto[4026531840:4160749567]	105	1			T13	1		T18	3		T109	1
auto[4160749568:4294967295]	104	1			T212	1		T69	1		T108	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	98	1			T17	1		T35	1		T99	1
auto[0:134217727]	auto[1]	2	1			T84	1		T439	1		-	-
auto[134217728:268435455]	auto[0]	89	1			T18	1		T25	1		T66	1
auto[134217728:268435455]	auto[1]	5	1			T110	1		T380	1		T337	1
auto[268435456:402653183]	auto[0]	81	1			T35	1		T18	2		T48	1
auto[268435456:402653183]	auto[1]	8	1			T13	1		T84	1		T128	1
auto[402653184:536870911]	auto[0]	82	1			T125	1		T48	1		T25	1
auto[402653184:536870911]	auto[1]	11	1			T110	1		T244	3		T113	1
auto[536870912:671088639]	auto[0]	67	1			T18	1		T76	1		T38	1
auto[536870912:671088639]	auto[1]	4	1			T13	1		T360	1		T440	1
auto[671088640:805306367]	auto[0]	93	1			T18	2		T134	1		T66	2
auto[671088640:805306367]	auto[1]	9	1			T13	1		T110	1		T245	1
auto[805306368:939524095]	auto[0]	91	1			T18	2		T134	1		T69	1
auto[805306368:939524095]	auto[1]	11	1			T110	1		T113	1		T337	1
auto[939524096:1073741823]	auto[0]	81	1			T5	1		T18	2		T48	1
auto[939524096:1073741823]	auto[1]	7	1			T110	1		T113	2		T380	1
auto[1073741824:1207959551]	auto[0]	75	1			T5	1		T13	1		T76	1
auto[1073741824:1207959551]	auto[1]	6	1			T244	1		T113	1		T380	1
auto[1207959552:1342177279]	auto[0]	99	1			T15	1		T16	1		T69	1
auto[1207959552:1342177279]	auto[1]	7	1			T126	1		T110	1		T296	1
auto[1342177280:1476395007]	auto[0]	91	1			T84	1		T66	1		T248	1
auto[1342177280:1476395007]	auto[1]	12	1			T114	1		T380	1		T280	1
auto[1476395008:1610612735]	auto[0]	93	1			T13	1		T134	1		T48	2
auto[1476395008:1610612735]	auto[1]	9	1			T128	2		T114	1		T286	1
auto[1610612736:1744830463]	auto[0]	91	1			T16	2		T204	1		T207	1
auto[1610612736:1744830463]	auto[1]	7	1			T13	1		T242	1		T324	1
auto[1744830464:1879048191]	auto[0]	99	1			T18	2		T99	1		T136	1
auto[1744830464:1879048191]	auto[1]	10	1			T13	2		T84	1		T296	1
auto[1879048192:2013265919]	auto[0]	107	1			T13	1		T18	1		T212	1
auto[1879048192:2013265919]	auto[1]	7	1			T380	1		T241	1		T432	1
auto[2013265920:2147483647]	auto[0]	103	1			T5	1		T84	1		T134	1
auto[2013265920:2147483647]	auto[1]	5	1			T84	1		T325	1		T368	1
auto[2147483648:2281701375]	auto[0]	103	1			T18	1		T48	1		T66	2
auto[2147483648:2281701375]	auto[1]	11	1			T84	2		T380	1		T247	1
auto[2281701376:2415919103]	auto[0]	74	1			T18	2		T69	2		T66	1
auto[2281701376:2415919103]	auto[1]	12	1			T13	2		T84	1		T380	1
auto[2415919104:2550136831]	auto[0]	86	1			T13	1		T18	1		T38	1
auto[2415919104:2550136831]	auto[1]	9	1			T84	1		T245	1		T296	1
auto[2550136832:2684354559]	auto[0]	87	1			T134	1		T66	2		T204	2
auto[2550136832:2684354559]	auto[1]	4	1			T84	1		T114	2		T286	1
auto[2684354560:2818572287]	auto[0]	93	1			T17	1		T18	1		T38	1
auto[2684354560:2818572287]	auto[1]	8	1			T13	1		T126	1		T110	1
auto[2818572288:2952790015]	auto[0]	100	1			T17	1		T48	1		T212	1
auto[2818572288:2952790015]	auto[1]	12	1			T13	3		T84	1		T126	1
auto[2952790016:3087007743]	auto[0]	103	1			T5	1		T35	1		T18	1
auto[2952790016:3087007743]	auto[1]	6	1			T84	1		T244	2		T441	1
auto[3087007744:3221225471]	auto[0]	95	1			T13	1		T28	1		T18	1
auto[3087007744:3221225471]	auto[1]	7	1			T380	1		T247	1		T368	1
auto[3221225472:3355443199]	auto[0]	71	1			T5	1		T76	1		T84	1
auto[3221225472:3355443199]	auto[1]	6	1			T110	1		T337	1		T308	1
auto[3355443200:3489660927]	auto[0]	89	1			T18	1		T48	1		T212	1
auto[3355443200:3489660927]	auto[1]	10	1			T126	1		T110	1		T380	1
auto[3489660928:3623878655]	auto[0]	87	1			T13	1		T14	1		T108	1
auto[3489660928:3623878655]	auto[1]	8	1			T108	1		T245	1		T242	1
auto[3623878656:3758096383]	auto[0]	93	1			T18	1		T76	1		T78	1
auto[3623878656:3758096383]	auto[1]	7	1			T128	1		T110	1		T324	1
auto[3758096384:3892314111]	auto[0]	83	1			T13	1		T18	1		T99	1
auto[3758096384:3892314111]	auto[1]	9	1			T84	1		T245	1		T400	1
auto[3892314112:4026531839]	auto[0]	90	1			T15	1		T17	1		T109	1
auto[3892314112:4026531839]	auto[1]	10	1			T245	1		T114	1		T420	1
auto[4026531840:4160749567]	auto[0]	94	1			T18	3		T109	1		T67	1
auto[4026531840:4160749567]	auto[1]	11	1			T13	1		T113	1		T325	1
auto[4160749568:4294967295]	auto[0]	96	1			T212	1		T69	1		T6	1
auto[4160749568:4294967295]	auto[1]	8	1			T108	1		T110	1		T244	2