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71 always_ff @(posedge clk_i or negedge rst_ni) begin
72 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
73 1/1 err_q <= '0;
Tests: T1 T2 T3
74 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
75 1/1 err_q <= 1'b1;
Tests: T34 T10 T36
76 end
MISSING_ELSE
77 end
78
79 // integrity error output is permanent and should be used for alert generation
80 // register errors are transactional
81 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T2 T3
82
83 // outgoing integrity generation
84 tlul_pkg::tl_d2h_t tl_o_pre;
85 tlul_rsp_intg_gen #(
86 .EnableRspIntgGen(1),
87 .EnableDataIntgGen(1)
88 ) u_rsp_intg_gen (
89 .tl_i(tl_o_pre),
90 .tl_o(tl_o)
91 );
92
93 1/1 assign tl_reg_h2d = tl_i;
Tests: T1 T2 T3
94 1/1 assign tl_o_pre = tl_reg_d2h;
Tests: T1 T2 T3
95
96 tlul_adapter_reg #(
97 .RegAw(AW),
98 .RegDw(DW),
99 .EnableDataIntgGen(0)
100 ) u_reg_if (
101 .clk_i (clk_i),
102 .rst_ni (rst_ni),
103
104 .tl_i (tl_reg_h2d),
105 .tl_o (tl_reg_d2h),
106
107 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
108 .intg_error_o(),
109
110 .we_o (reg_we),
111 .re_o (reg_re),
112 .addr_o (reg_addr),
113 .wdata_o (reg_wdata),
114 .be_o (reg_be),
115 .busy_i (reg_busy),
116 .rdata_i (reg_rdata),
117 .error_i (reg_error)
118 );
119
120 // cdc oversampling signals
121
122 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T1 T2 T3
123 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T34 T18 T36
124
125 // Define SW related signals
126 // Format: <reg>_<field>_{wd|we|qs}
127 // or <reg>_{wd|we|qs} if field == 1 or 0
128 logic intr_state_we;
129 logic intr_state_qs;
130 logic intr_state_wd;
131 logic intr_enable_we;
132 logic intr_enable_qs;
133 logic intr_enable_wd;
134 logic intr_test_we;
135 logic intr_test_wd;
136 logic alert_test_we;
137 logic alert_test_recov_operation_err_wd;
138 logic alert_test_fatal_fault_err_wd;
139 logic cfg_regwen_re;
140 logic cfg_regwen_qs;
141 logic start_we;
142 logic start_qs;
143 logic start_wd;
144 logic control_shadowed_re;
145 logic control_shadowed_we;
146 logic [2:0] control_shadowed_operation_qs;
147 logic [2:0] control_shadowed_operation_wd;
148 logic control_shadowed_operation_storage_err;
149 logic control_shadowed_operation_update_err;
150 logic control_shadowed_cdi_sel_qs;
151 logic control_shadowed_cdi_sel_wd;
152 logic control_shadowed_cdi_sel_storage_err;
153 logic control_shadowed_cdi_sel_update_err;
154 logic [1:0] control_shadowed_dest_sel_qs;
155 logic [1:0] control_shadowed_dest_sel_wd;
156 logic control_shadowed_dest_sel_storage_err;
157 logic control_shadowed_dest_sel_update_err;
158 logic sideload_clear_we;
159 logic [2:0] sideload_clear_qs;
160 logic [2:0] sideload_clear_wd;
161 logic reseed_interval_regwen_we;
162 logic reseed_interval_regwen_qs;
163 logic reseed_interval_regwen_wd;
164 logic reseed_interval_shadowed_re;
165 logic reseed_interval_shadowed_we;
166 logic [15:0] reseed_interval_shadowed_qs;
167 logic [15:0] reseed_interval_shadowed_wd;
168 logic reseed_interval_shadowed_storage_err;
169 logic reseed_interval_shadowed_update_err;
170 logic sw_binding_regwen_re;
171 logic sw_binding_regwen_we;
172 logic sw_binding_regwen_qs;
173 logic sw_binding_regwen_wd;
174 logic sealing_sw_binding_0_we;
175 logic [31:0] sealing_sw_binding_0_qs;
176 logic [31:0] sealing_sw_binding_0_wd;
177 logic sealing_sw_binding_1_we;
178 logic [31:0] sealing_sw_binding_1_qs;
179 logic [31:0] sealing_sw_binding_1_wd;
180 logic sealing_sw_binding_2_we;
181 logic [31:0] sealing_sw_binding_2_qs;
182 logic [31:0] sealing_sw_binding_2_wd;
183 logic sealing_sw_binding_3_we;
184 logic [31:0] sealing_sw_binding_3_qs;
185 logic [31:0] sealing_sw_binding_3_wd;
186 logic sealing_sw_binding_4_we;
187 logic [31:0] sealing_sw_binding_4_qs;
188 logic [31:0] sealing_sw_binding_4_wd;
189 logic sealing_sw_binding_5_we;
190 logic [31:0] sealing_sw_binding_5_qs;
191 logic [31:0] sealing_sw_binding_5_wd;
192 logic sealing_sw_binding_6_we;
193 logic [31:0] sealing_sw_binding_6_qs;
194 logic [31:0] sealing_sw_binding_6_wd;
195 logic sealing_sw_binding_7_we;
196 logic [31:0] sealing_sw_binding_7_qs;
197 logic [31:0] sealing_sw_binding_7_wd;
198 logic attest_sw_binding_0_we;
199 logic [31:0] attest_sw_binding_0_qs;
200 logic [31:0] attest_sw_binding_0_wd;
201 logic attest_sw_binding_1_we;
202 logic [31:0] attest_sw_binding_1_qs;
203 logic [31:0] attest_sw_binding_1_wd;
204 logic attest_sw_binding_2_we;
205 logic [31:0] attest_sw_binding_2_qs;
206 logic [31:0] attest_sw_binding_2_wd;
207 logic attest_sw_binding_3_we;
208 logic [31:0] attest_sw_binding_3_qs;
209 logic [31:0] attest_sw_binding_3_wd;
210 logic attest_sw_binding_4_we;
211 logic [31:0] attest_sw_binding_4_qs;
212 logic [31:0] attest_sw_binding_4_wd;
213 logic attest_sw_binding_5_we;
214 logic [31:0] attest_sw_binding_5_qs;
215 logic [31:0] attest_sw_binding_5_wd;
216 logic attest_sw_binding_6_we;
217 logic [31:0] attest_sw_binding_6_qs;
218 logic [31:0] attest_sw_binding_6_wd;
219 logic attest_sw_binding_7_we;
220 logic [31:0] attest_sw_binding_7_qs;
221 logic [31:0] attest_sw_binding_7_wd;
222 logic salt_0_we;
223 logic [31:0] salt_0_qs;
224 logic [31:0] salt_0_wd;
225 logic salt_1_we;
226 logic [31:0] salt_1_qs;
227 logic [31:0] salt_1_wd;
228 logic salt_2_we;
229 logic [31:0] salt_2_qs;
230 logic [31:0] salt_2_wd;
231 logic salt_3_we;
232 logic [31:0] salt_3_qs;
233 logic [31:0] salt_3_wd;
234 logic salt_4_we;
235 logic [31:0] salt_4_qs;
236 logic [31:0] salt_4_wd;
237 logic salt_5_we;
238 logic [31:0] salt_5_qs;
239 logic [31:0] salt_5_wd;
240 logic salt_6_we;
241 logic [31:0] salt_6_qs;
242 logic [31:0] salt_6_wd;
243 logic salt_7_we;
244 logic [31:0] salt_7_qs;
245 logic [31:0] salt_7_wd;
246 logic key_version_we;
247 logic [31:0] key_version_qs;
248 logic [31:0] key_version_wd;
249 logic max_creator_key_ver_regwen_we;
250 logic max_creator_key_ver_regwen_qs;
251 logic max_creator_key_ver_regwen_wd;
252 logic max_creator_key_ver_shadowed_re;
253 logic max_creator_key_ver_shadowed_we;
254 logic [31:0] max_creator_key_ver_shadowed_qs;
255 logic [31:0] max_creator_key_ver_shadowed_wd;
256 logic max_creator_key_ver_shadowed_storage_err;
257 logic max_creator_key_ver_shadowed_update_err;
258 logic max_owner_int_key_ver_regwen_we;
259 logic max_owner_int_key_ver_regwen_qs;
260 logic max_owner_int_key_ver_regwen_wd;
261 logic max_owner_int_key_ver_shadowed_re;
262 logic max_owner_int_key_ver_shadowed_we;
263 logic [31:0] max_owner_int_key_ver_shadowed_qs;
264 logic [31:0] max_owner_int_key_ver_shadowed_wd;
265 logic max_owner_int_key_ver_shadowed_storage_err;
266 logic max_owner_int_key_ver_shadowed_update_err;
267 logic max_owner_key_ver_regwen_we;
268 logic max_owner_key_ver_regwen_qs;
269 logic max_owner_key_ver_regwen_wd;
270 logic max_owner_key_ver_shadowed_re;
271 logic max_owner_key_ver_shadowed_we;
272 logic [31:0] max_owner_key_ver_shadowed_qs;
273 logic [31:0] max_owner_key_ver_shadowed_wd;
274 logic max_owner_key_ver_shadowed_storage_err;
275 logic max_owner_key_ver_shadowed_update_err;
276 logic sw_share0_output_0_re;
277 logic [31:0] sw_share0_output_0_qs;
278 logic [31:0] sw_share0_output_0_wd;
279 logic sw_share0_output_1_re;
280 logic [31:0] sw_share0_output_1_qs;
281 logic [31:0] sw_share0_output_1_wd;
282 logic sw_share0_output_2_re;
283 logic [31:0] sw_share0_output_2_qs;
284 logic [31:0] sw_share0_output_2_wd;
285 logic sw_share0_output_3_re;
286 logic [31:0] sw_share0_output_3_qs;
287 logic [31:0] sw_share0_output_3_wd;
288 logic sw_share0_output_4_re;
289 logic [31:0] sw_share0_output_4_qs;
290 logic [31:0] sw_share0_output_4_wd;
291 logic sw_share0_output_5_re;
292 logic [31:0] sw_share0_output_5_qs;
293 logic [31:0] sw_share0_output_5_wd;
294 logic sw_share0_output_6_re;
295 logic [31:0] sw_share0_output_6_qs;
296 logic [31:0] sw_share0_output_6_wd;
297 logic sw_share0_output_7_re;
298 logic [31:0] sw_share0_output_7_qs;
299 logic [31:0] sw_share0_output_7_wd;
300 logic sw_share1_output_0_re;
301 logic [31:0] sw_share1_output_0_qs;
302 logic [31:0] sw_share1_output_0_wd;
303 logic sw_share1_output_1_re;
304 logic [31:0] sw_share1_output_1_qs;
305 logic [31:0] sw_share1_output_1_wd;
306 logic sw_share1_output_2_re;
307 logic [31:0] sw_share1_output_2_qs;
308 logic [31:0] sw_share1_output_2_wd;
309 logic sw_share1_output_3_re;
310 logic [31:0] sw_share1_output_3_qs;
311 logic [31:0] sw_share1_output_3_wd;
312 logic sw_share1_output_4_re;
313 logic [31:0] sw_share1_output_4_qs;
314 logic [31:0] sw_share1_output_4_wd;
315 logic sw_share1_output_5_re;
316 logic [31:0] sw_share1_output_5_qs;
317 logic [31:0] sw_share1_output_5_wd;
318 logic sw_share1_output_6_re;
319 logic [31:0] sw_share1_output_6_qs;
320 logic [31:0] sw_share1_output_6_wd;
321 logic sw_share1_output_7_re;
322 logic [31:0] sw_share1_output_7_qs;
323 logic [31:0] sw_share1_output_7_wd;
324 logic [2:0] working_state_qs;
325 logic op_status_we;
326 logic [1:0] op_status_qs;
327 logic [1:0] op_status_wd;
328 logic err_code_we;
329 logic err_code_invalid_op_qs;
330 logic err_code_invalid_op_wd;
331 logic err_code_invalid_kmac_input_qs;
332 logic err_code_invalid_kmac_input_wd;
333 logic err_code_invalid_shadow_update_qs;
334 logic err_code_invalid_shadow_update_wd;
335 logic fault_status_cmd_qs;
336 logic fault_status_kmac_fsm_qs;
337 logic fault_status_kmac_done_qs;
338 logic fault_status_kmac_op_qs;
339 logic fault_status_kmac_out_qs;
340 logic fault_status_regfile_intg_qs;
341 logic fault_status_shadow_qs;
342 logic fault_status_ctrl_fsm_intg_qs;
343 logic fault_status_ctrl_fsm_chk_qs;
344 logic fault_status_ctrl_fsm_cnt_qs;
345 logic fault_status_reseed_cnt_qs;
346 logic fault_status_side_ctrl_fsm_qs;
347 logic fault_status_side_ctrl_sel_qs;
348 logic fault_status_key_ecc_qs;
349 logic debug_we;
350 logic debug_invalid_creator_seed_qs;
351 logic debug_invalid_creator_seed_wd;
352 logic debug_invalid_owner_seed_qs;
353 logic debug_invalid_owner_seed_wd;
354 logic debug_invalid_dev_id_qs;
355 logic debug_invalid_dev_id_wd;
356 logic debug_invalid_health_state_qs;
357 logic debug_invalid_health_state_wd;
358 logic debug_invalid_key_version_qs;
359 logic debug_invalid_key_version_wd;
360 logic debug_invalid_key_qs;
361 logic debug_invalid_key_wd;
362 logic debug_invalid_digest_qs;
363 logic debug_invalid_digest_wd;
364
365 // Register instances
366 // R[intr_state]: V(False)
367 prim_subreg #(
368 .DW (1),
369 .SwAccess(prim_subreg_pkg::SwAccessW1C),
370 .RESVAL (1'h0),
371 .Mubi (1'b0)
372 ) u_intr_state (
373 .clk_i (clk_i),
374 .rst_ni (rst_ni),
375
376 // from register interface
377 .we (intr_state_we),
378 .wd (intr_state_wd),
379
380 // from internal hardware
381 .de (hw2reg.intr_state.de),
382 .d (hw2reg.intr_state.d),
383
384 // to internal hardware
385 .qe (),
386 .q (reg2hw.intr_state.q),
387 .ds (),
388
389 // to register interface (read)
390 .qs (intr_state_qs)
391 );
392
393
394 // R[intr_enable]: V(False)
395 prim_subreg #(
396 .DW (1),
397 .SwAccess(prim_subreg_pkg::SwAccessRW),
398 .RESVAL (1'h0),
399 .Mubi (1'b0)
400 ) u_intr_enable (
401 .clk_i (clk_i),
402 .rst_ni (rst_ni),
403
404 // from register interface
405 .we (intr_enable_we),
406 .wd (intr_enable_wd),
407
408 // from internal hardware
409 .de (1'b0),
410 .d ('0),
411
412 // to internal hardware
413 .qe (),
414 .q (reg2hw.intr_enable.q),
415 .ds (),
416
417 // to register interface (read)
418 .qs (intr_enable_qs)
419 );
420
421
422 // R[intr_test]: V(True)
423 logic intr_test_qe;
424 logic [0:0] intr_test_flds_we;
425 1/1 assign intr_test_qe = &intr_test_flds_we;
Tests: T18 T66 T68
426 prim_subreg_ext #(
427 .DW (1)
428 ) u_intr_test (
429 .re (1'b0),
430 .we (intr_test_we),
431 .wd (intr_test_wd),
432 .d ('0),
433 .qre (),
434 .qe (intr_test_flds_we[0]),
435 .q (reg2hw.intr_test.q),
436 .ds (),
437 .qs ()
438 );
439 1/1 assign reg2hw.intr_test.qe = intr_test_qe;
Tests: T18 T66 T68
440
441
442 // R[alert_test]: V(True)
443 logic alert_test_qe;
444 logic [1:0] alert_test_flds_we;
445 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T63 T18 T64
446 // F[recov_operation_err]: 0:0
447 prim_subreg_ext #(
448 .DW (1)
449 ) u_alert_test_recov_operation_err (
450 .re (1'b0),
451 .we (alert_test_we),
452 .wd (alert_test_recov_operation_err_wd),
453 .d ('0),
454 .qre (),
455 .qe (alert_test_flds_we[0]),
456 .q (reg2hw.alert_test.recov_operation_err.q),
457 .ds (),
458 .qs ()
459 );
460 1/1 assign reg2hw.alert_test.recov_operation_err.qe = alert_test_qe;
Tests: T63 T18 T64
461
462 // F[fatal_fault_err]: 1:1
463 prim_subreg_ext #(
464 .DW (1)
465 ) u_alert_test_fatal_fault_err (
466 .re (1'b0),
467 .we (alert_test_we),
468 .wd (alert_test_fatal_fault_err_wd),
469 .d ('0),
470 .qre (),
471 .qe (alert_test_flds_we[1]),
472 .q (reg2hw.alert_test.fatal_fault_err.q),
473 .ds (),
474 .qs ()
475 );
476 1/1 assign reg2hw.alert_test.fatal_fault_err.qe = alert_test_qe;
Tests: T63 T18 T64
477
478
479 // R[cfg_regwen]: V(True)
480 prim_subreg_ext #(
481 .DW (1)
482 ) u_cfg_regwen (
483 .re (cfg_regwen_re),
484 .we (1'b0),
485 .wd ('0),
486 .d (hw2reg.cfg_regwen.d),
487 .qre (),
488 .qe (),
489 .q (),
490 .ds (),
491 .qs (cfg_regwen_qs)
492 );
493
494
495 // R[start]: V(False)
496 // Create REGWEN-gated WE signal
497 logic start_gated_we;
498 1/1 assign start_gated_we = start_we & cfg_regwen_qs;
Tests: T1 T2 T3
499 prim_subreg #(
500 .DW (1),
501 .SwAccess(prim_subreg_pkg::SwAccessRW),
502 .RESVAL (1'h0),
503 .Mubi (1'b0)
504 ) u_start (
505 .clk_i (clk_i),
506 .rst_ni (rst_ni),
507
508 // from register interface
509 .we (start_gated_we),
510 .wd (start_wd),
511
512 // from internal hardware
513 .de (hw2reg.start.de),
514 .d (hw2reg.start.d),
515
516 // to internal hardware
517 .qe (),
518 .q (reg2hw.start.q),
519 .ds (),
520
521 // to register interface (read)
522 .qs (start_qs)
523 );
524
525
526 // R[control_shadowed]: V(False)
527 // Create REGWEN-gated WE signal
528 logic control_shadowed_gated_we;
529 1/1 assign control_shadowed_gated_we = control_shadowed_we & cfg_regwen_qs;
Tests: T1 T2 T3
530 // F[operation]: 6:4
531 prim_subreg_shadow #(
532 .DW (3),
533 .SwAccess(prim_subreg_pkg::SwAccessRW),
534 .RESVAL (3'h1),
535 .Mubi (1'b0)
536 ) u_control_shadowed_operation (
537 .clk_i (clk_i),
538 .rst_ni (rst_ni),
539 .rst_shadowed_ni (rst_shadowed_ni),
540
541 // from register interface
542 .re (control_shadowed_re),
543 .we (control_shadowed_gated_we),
544 .wd (control_shadowed_operation_wd),
545
546 // from internal hardware
547 .de (1'b0),
548 .d ('0),
549
550 // to internal hardware
551 .qe (),
552 .q (reg2hw.control_shadowed.operation.q),
553 .ds (),
554
555 // to register interface (read)
556 .qs (control_shadowed_operation_qs),
557
558 // Shadow register phase. Relevant for hwext only.
559 .phase (),
560
561 // Shadow register error conditions
562 .err_update (control_shadowed_operation_update_err),
563 .err_storage (control_shadowed_operation_storage_err)
564 );
565
566 // F[cdi_sel]: 7:7
567 prim_subreg_shadow #(
568 .DW (1),
569 .SwAccess(prim_subreg_pkg::SwAccessRW),
570 .RESVAL (1'h0),
571 .Mubi (1'b0)
572 ) u_control_shadowed_cdi_sel (
573 .clk_i (clk_i),
574 .rst_ni (rst_ni),
575 .rst_shadowed_ni (rst_shadowed_ni),
576
577 // from register interface
578 .re (control_shadowed_re),
579 .we (control_shadowed_gated_we),
580 .wd (control_shadowed_cdi_sel_wd),
581
582 // from internal hardware
583 .de (1'b0),
584 .d ('0),
585
586 // to internal hardware
587 .qe (),
588 .q (reg2hw.control_shadowed.cdi_sel.q),
589 .ds (),
590
591 // to register interface (read)
592 .qs (control_shadowed_cdi_sel_qs),
593
594 // Shadow register phase. Relevant for hwext only.
595 .phase (),
596
597 // Shadow register error conditions
598 .err_update (control_shadowed_cdi_sel_update_err),
599 .err_storage (control_shadowed_cdi_sel_storage_err)
600 );
601
602 // F[dest_sel]: 13:12
603 prim_subreg_shadow #(
604 .DW (2),
605 .SwAccess(prim_subreg_pkg::SwAccessRW),
606 .RESVAL (2'h0),
607 .Mubi (1'b0)
608 ) u_control_shadowed_dest_sel (
609 .clk_i (clk_i),
610 .rst_ni (rst_ni),
611 .rst_shadowed_ni (rst_shadowed_ni),
612
613 // from register interface
614 .re (control_shadowed_re),
615 .we (control_shadowed_gated_we),
616 .wd (control_shadowed_dest_sel_wd),
617
618 // from internal hardware
619 .de (1'b0),
620 .d ('0),
621
622 // to internal hardware
623 .qe (),
624 .q (reg2hw.control_shadowed.dest_sel.q),
625 .ds (),
626
627 // to register interface (read)
628 .qs (control_shadowed_dest_sel_qs),
629
630 // Shadow register phase. Relevant for hwext only.
631 .phase (),
632
633 // Shadow register error conditions
634 .err_update (control_shadowed_dest_sel_update_err),
635 .err_storage (control_shadowed_dest_sel_storage_err)
636 );
637
638
639 // R[sideload_clear]: V(False)
640 // Create REGWEN-gated WE signal
641 logic sideload_clear_gated_we;
642 1/1 assign sideload_clear_gated_we = sideload_clear_we & cfg_regwen_qs;
Tests: T1 T2 T3
643 prim_subreg #(
644 .DW (3),
645 .SwAccess(prim_subreg_pkg::SwAccessRW),
646 .RESVAL (3'h0),
647 .Mubi (1'b0)
648 ) u_sideload_clear (
649 .clk_i (clk_i),
650 .rst_ni (rst_ni),
651
652 // from register interface
653 .we (sideload_clear_gated_we),
654 .wd (sideload_clear_wd),
655
656 // from internal hardware
657 .de (1'b0),
658 .d ('0),
659
660 // to internal hardware
661 .qe (),
662 .q (reg2hw.sideload_clear.q),
663 .ds (),
664
665 // to register interface (read)
666 .qs (sideload_clear_qs)
667 );
668
669
670 // R[reseed_interval_regwen]: V(False)
671 prim_subreg #(
672 .DW (1),
673 .SwAccess(prim_subreg_pkg::SwAccessW0C),
674 .RESVAL (1'h1),
675 .Mubi (1'b0)
676 ) u_reseed_interval_regwen (
677 .clk_i (clk_i),
678 .rst_ni (rst_ni),
679
680 // from register interface
681 .we (reseed_interval_regwen_we),
682 .wd (reseed_interval_regwen_wd),
683
684 // from internal hardware
685 .de (1'b0),
686 .d ('0),
687
688 // to internal hardware
689 .qe (),
690 .q (),
691 .ds (),
692
693 // to register interface (read)
694 .qs (reseed_interval_regwen_qs)
695 );
696
697
698 // R[reseed_interval_shadowed]: V(False)
699 // Create REGWEN-gated WE signal
700 logic reseed_interval_shadowed_gated_we;
701 1/1 assign reseed_interval_shadowed_gated_we =
Tests: T1 T2 T3
702 reseed_interval_shadowed_we & reseed_interval_regwen_qs;
703 prim_subreg_shadow #(
704 .DW (16),
705 .SwAccess(prim_subreg_pkg::SwAccessRW),
706 .RESVAL (16'h100),
707 .Mubi (1'b0)
708 ) u_reseed_interval_shadowed (
709 .clk_i (clk_i),
710 .rst_ni (rst_ni),
711 .rst_shadowed_ni (rst_shadowed_ni),
712
713 // from register interface
714 .re (reseed_interval_shadowed_re),
715 .we (reseed_interval_shadowed_gated_we),
716 .wd (reseed_interval_shadowed_wd),
717
718 // from internal hardware
719 .de (1'b0),
720 .d ('0),
721
722 // to internal hardware
723 .qe (),
724 .q (reg2hw.reseed_interval_shadowed.q),
725 .ds (),
726
727 // to register interface (read)
728 .qs (reseed_interval_shadowed_qs),
729
730 // Shadow register phase. Relevant for hwext only.
731 .phase (),
732
733 // Shadow register error conditions
734 .err_update (reseed_interval_shadowed_update_err),
735 .err_storage (reseed_interval_shadowed_storage_err)
736 );
737
738
739 // R[sw_binding_regwen]: V(True)
740 logic sw_binding_regwen_qe;
741 logic [0:0] sw_binding_regwen_flds_we;
742 1/1 assign sw_binding_regwen_qe = &sw_binding_regwen_flds_we;
Tests: T5 T13 T14
743 prim_subreg_ext #(
744 .DW (1)
745 ) u_sw_binding_regwen (
746 .re (sw_binding_regwen_re),
747 .we (sw_binding_regwen_we),
748 .wd (sw_binding_regwen_wd),
749 .d (hw2reg.sw_binding_regwen.d),
750 .qre (),
751 .qe (sw_binding_regwen_flds_we[0]),
752 .q (reg2hw.sw_binding_regwen.q),
753 .ds (),
754 .qs (sw_binding_regwen_qs)
755 );
756 1/1 assign reg2hw.sw_binding_regwen.qe = sw_binding_regwen_qe;
Tests: T5 T13 T14
757
758
759 // Subregister 0 of Multireg sealing_sw_binding
760 // R[sealing_sw_binding_0]: V(False)
761 // Create REGWEN-gated WE signal
762 logic sealing_sw_binding_0_gated_we;
763 1/1 assign sealing_sw_binding_0_gated_we = sealing_sw_binding_0_we & sw_binding_regwen_qs;
Tests: T1 T2 T3
764 prim_subreg #(
765 .DW (32),
766 .SwAccess(prim_subreg_pkg::SwAccessRW),
767 .RESVAL (32'h0),
768 .Mubi (1'b0)
769 ) u_sealing_sw_binding_0 (
770 .clk_i (clk_i),
771 .rst_ni (rst_ni),
772
773 // from register interface
774 .we (sealing_sw_binding_0_gated_we),
775 .wd (sealing_sw_binding_0_wd),
776
777 // from internal hardware
778 .de (1'b0),
779 .d ('0),
780
781 // to internal hardware
782 .qe (),
783 .q (reg2hw.sealing_sw_binding[0].q),
784 .ds (),
785
786 // to register interface (read)
787 .qs (sealing_sw_binding_0_qs)
788 );
789
790
791 // Subregister 1 of Multireg sealing_sw_binding
792 // R[sealing_sw_binding_1]: V(False)
793 // Create REGWEN-gated WE signal
794 logic sealing_sw_binding_1_gated_we;
795 1/1 assign sealing_sw_binding_1_gated_we = sealing_sw_binding_1_we & sw_binding_regwen_qs;
Tests: T1 T2 T3
796 prim_subreg #(
797 .DW (32),
798 .SwAccess(prim_subreg_pkg::SwAccessRW),
799 .RESVAL (32'h0),
800 .Mubi (1'b0)
801 ) u_sealing_sw_binding_1 (
802 .clk_i (clk_i),
803 .rst_ni (rst_ni),
804
805 // from register interface
806 .we (sealing_sw_binding_1_gated_we),
807 .wd (sealing_sw_binding_1_wd),
808
809 // from internal hardware
810 .de (1'b0),
811 .d ('0),
812
813 // to internal hardware
814 .qe (),
815 .q (reg2hw.sealing_sw_binding[1].q),
816 .ds (),
817
818 // to register interface (read)
819 .qs (sealing_sw_binding_1_qs)
820 );
821
822
823 // Subregister 2 of Multireg sealing_sw_binding
824 // R[sealing_sw_binding_2]: V(False)
825 // Create REGWEN-gated WE signal
826 logic sealing_sw_binding_2_gated_we;
827 1/1 assign sealing_sw_binding_2_gated_we = sealing_sw_binding_2_we & sw_binding_regwen_qs;
Tests: T1 T2 T3
828 prim_subreg #(
829 .DW (32),
830 .SwAccess(prim_subreg_pkg::SwAccessRW),
831 .RESVAL (32'h0),
832 .Mubi (1'b0)
833 ) u_sealing_sw_binding_2 (
834 .clk_i (clk_i),
835 .rst_ni (rst_ni),
836
837 // from register interface
838 .we (sealing_sw_binding_2_gated_we),
839 .wd (sealing_sw_binding_2_wd),
840
841 // from internal hardware
842 .de (1'b0),
843 .d ('0),
844
845 // to internal hardware
846 .qe (),
847 .q (reg2hw.sealing_sw_binding[2].q),
848 .ds (),
849
850 // to register interface (read)
851 .qs (sealing_sw_binding_2_qs)
852 );
853
854
855 // Subregister 3 of Multireg sealing_sw_binding
856 // R[sealing_sw_binding_3]: V(False)
857 // Create REGWEN-gated WE signal
858 logic sealing_sw_binding_3_gated_we;
859 1/1 assign sealing_sw_binding_3_gated_we = sealing_sw_binding_3_we & sw_binding_regwen_qs;
Tests: T1 T2 T3
860 prim_subreg #(
861 .DW (32),
862 .SwAccess(prim_subreg_pkg::SwAccessRW),
863 .RESVAL (32'h0),
864 .Mubi (1'b0)
865 ) u_sealing_sw_binding_3 (
866 .clk_i (clk_i),
867 .rst_ni (rst_ni),
868
869 // from register interface
870 .we (sealing_sw_binding_3_gated_we),
871 .wd (sealing_sw_binding_3_wd),
872
873 // from internal hardware
874 .de (1'b0),
875 .d ('0),
876
877 // to internal hardware
878 .qe (),
879 .q (reg2hw.sealing_sw_binding[3].q),
880 .ds (),
881
882 // to register interface (read)
883 .qs (sealing_sw_binding_3_qs)
884 );
885
886
887 // Subregister 4 of Multireg sealing_sw_binding
888 // R[sealing_sw_binding_4]: V(False)
889 // Create REGWEN-gated WE signal
890 logic sealing_sw_binding_4_gated_we;
891 1/1 assign sealing_sw_binding_4_gated_we = sealing_sw_binding_4_we & sw_binding_regwen_qs;
Tests: T1 T2 T3
892 prim_subreg #(
893 .DW (32),
894 .SwAccess(prim_subreg_pkg::SwAccessRW),
895 .RESVAL (32'h0),
896 .Mubi (1'b0)
897 ) u_sealing_sw_binding_4 (
898 .clk_i (clk_i),
899 .rst_ni (rst_ni),
900
901 // from register interface
902 .we (sealing_sw_binding_4_gated_we),
903 .wd (sealing_sw_binding_4_wd),
904
905 // from internal hardware
906 .de (1'b0),
907 .d ('0),
908
909 // to internal hardware
910 .qe (),
911 .q (reg2hw.sealing_sw_binding[4].q),
912 .ds (),
913
914 // to register interface (read)
915 .qs (sealing_sw_binding_4_qs)
916 );
917
918
919 // Subregister 5 of Multireg sealing_sw_binding
920 // R[sealing_sw_binding_5]: V(False)
921 // Create REGWEN-gated WE signal
922 logic sealing_sw_binding_5_gated_we;
923 1/1 assign sealing_sw_binding_5_gated_we = sealing_sw_binding_5_we & sw_binding_regwen_qs;
Tests: T1 T2 T3
924 prim_subreg #(
925 .DW (32),
926 .SwAccess(prim_subreg_pkg::SwAccessRW),
927 .RESVAL (32'h0),
928 .Mubi (1'b0)
929 ) u_sealing_sw_binding_5 (
930 .clk_i (clk_i),
931 .rst_ni (rst_ni),
932
933 // from register interface
934 .we (sealing_sw_binding_5_gated_we),
935 .wd (sealing_sw_binding_5_wd),
936
937 // from internal hardware
938 .de (1'b0),
939 .d ('0),
940
941 // to internal hardware
942 .qe (),
943 .q (reg2hw.sealing_sw_binding[5].q),
944 .ds (),
945
946 // to register interface (read)
947 .qs (sealing_sw_binding_5_qs)
948 );
949
950
951 // Subregister 6 of Multireg sealing_sw_binding
952 // R[sealing_sw_binding_6]: V(False)
953 // Create REGWEN-gated WE signal
954 logic sealing_sw_binding_6_gated_we;
955 1/1 assign sealing_sw_binding_6_gated_we = sealing_sw_binding_6_we & sw_binding_regwen_qs;
Tests: T1 T2 T3
956 prim_subreg #(
957 .DW (32),
958 .SwAccess(prim_subreg_pkg::SwAccessRW),
959 .RESVAL (32'h0),
960 .Mubi (1'b0)
961 ) u_sealing_sw_binding_6 (
962 .clk_i (clk_i),
963 .rst_ni (rst_ni),
964
965 // from register interface
966 .we (sealing_sw_binding_6_gated_we),
967 .wd (sealing_sw_binding_6_wd),
968
969 // from internal hardware
970 .de (1'b0),
971 .d ('0),
972
973 // to internal hardware
974 .qe (),
975 .q (reg2hw.sealing_sw_binding[6].q),
976 .ds (),
977
978 // to register interface (read)
979 .qs (sealing_sw_binding_6_qs)
980 );
981
982
983 // Subregister 7 of Multireg sealing_sw_binding
984 // R[sealing_sw_binding_7]: V(False)
985 // Create REGWEN-gated WE signal
986 logic sealing_sw_binding_7_gated_we;
987 1/1 assign sealing_sw_binding_7_gated_we = sealing_sw_binding_7_we & sw_binding_regwen_qs;
Tests: T1 T2 T3
988 prim_subreg #(
989 .DW (32),
990 .SwAccess(prim_subreg_pkg::SwAccessRW),
991 .RESVAL (32'h0),
992 .Mubi (1'b0)
993 ) u_sealing_sw_binding_7 (
994 .clk_i (clk_i),
995 .rst_ni (rst_ni),
996
997 // from register interface
998 .we (sealing_sw_binding_7_gated_we),
999 .wd (sealing_sw_binding_7_wd),
1000
1001 // from internal hardware
1002 .de (1'b0),
1003 .d ('0),
1004
1005 // to internal hardware
1006 .qe (),
1007 .q (reg2hw.sealing_sw_binding[7].q),
1008 .ds (),
1009
1010 // to register interface (read)
1011 .qs (sealing_sw_binding_7_qs)
1012 );
1013
1014
1015 // Subregister 0 of Multireg attest_sw_binding
1016 // R[attest_sw_binding_0]: V(False)
1017 // Create REGWEN-gated WE signal
1018 logic attest_sw_binding_0_gated_we;
1019 1/1 assign attest_sw_binding_0_gated_we = attest_sw_binding_0_we & sw_binding_regwen_qs;
Tests: T1 T2 T3
1020 prim_subreg #(
1021 .DW (32),
1022 .SwAccess(prim_subreg_pkg::SwAccessRW),
1023 .RESVAL (32'h0),
1024 .Mubi (1'b0)
1025 ) u_attest_sw_binding_0 (
1026 .clk_i (clk_i),
1027 .rst_ni (rst_ni),
1028
1029 // from register interface
1030 .we (attest_sw_binding_0_gated_we),
1031 .wd (attest_sw_binding_0_wd),
1032
1033 // from internal hardware
1034 .de (1'b0),
1035 .d ('0),
1036
1037 // to internal hardware
1038 .qe (),
1039 .q (reg2hw.attest_sw_binding[0].q),
1040 .ds (),
1041
1042 // to register interface (read)
1043 .qs (attest_sw_binding_0_qs)
1044 );
1045
1046
1047 // Subregister 1 of Multireg attest_sw_binding
1048 // R[attest_sw_binding_1]: V(False)
1049 // Create REGWEN-gated WE signal
1050 logic attest_sw_binding_1_gated_we;
1051 1/1 assign attest_sw_binding_1_gated_we = attest_sw_binding_1_we & sw_binding_regwen_qs;
Tests: T1 T2 T3
1052 prim_subreg #(
1053 .DW (32),
1054 .SwAccess(prim_subreg_pkg::SwAccessRW),
1055 .RESVAL (32'h0),
1056 .Mubi (1'b0)
1057 ) u_attest_sw_binding_1 (
1058 .clk_i (clk_i),
1059 .rst_ni (rst_ni),
1060
1061 // from register interface
1062 .we (attest_sw_binding_1_gated_we),
1063 .wd (attest_sw_binding_1_wd),
1064
1065 // from internal hardware
1066 .de (1'b0),
1067 .d ('0),
1068
1069 // to internal hardware
1070 .qe (),
1071 .q (reg2hw.attest_sw_binding[1].q),
1072 .ds (),
1073
1074 // to register interface (read)
1075 .qs (attest_sw_binding_1_qs)
1076 );
1077
1078
1079 // Subregister 2 of Multireg attest_sw_binding
1080 // R[attest_sw_binding_2]: V(False)
1081 // Create REGWEN-gated WE signal
1082 logic attest_sw_binding_2_gated_we;
1083 1/1 assign attest_sw_binding_2_gated_we = attest_sw_binding_2_we & sw_binding_regwen_qs;
Tests: T1 T2 T3
1084 prim_subreg #(
1085 .DW (32),
1086 .SwAccess(prim_subreg_pkg::SwAccessRW),
1087 .RESVAL (32'h0),
1088 .Mubi (1'b0)
1089 ) u_attest_sw_binding_2 (
1090 .clk_i (clk_i),
1091 .rst_ni (rst_ni),
1092
1093 // from register interface
1094 .we (attest_sw_binding_2_gated_we),
1095 .wd (attest_sw_binding_2_wd),
1096
1097 // from internal hardware
1098 .de (1'b0),
1099 .d ('0),
1100
1101 // to internal hardware
1102 .qe (),
1103 .q (reg2hw.attest_sw_binding[2].q),
1104 .ds (),
1105
1106 // to register interface (read)
1107 .qs (attest_sw_binding_2_qs)
1108 );
1109
1110
1111 // Subregister 3 of Multireg attest_sw_binding
1112 // R[attest_sw_binding_3]: V(False)
1113 // Create REGWEN-gated WE signal
1114 logic attest_sw_binding_3_gated_we;
1115 1/1 assign attest_sw_binding_3_gated_we = attest_sw_binding_3_we & sw_binding_regwen_qs;
Tests: T1 T2 T3
1116 prim_subreg #(
1117 .DW (32),
1118 .SwAccess(prim_subreg_pkg::SwAccessRW),
1119 .RESVAL (32'h0),
1120 .Mubi (1'b0)
1121 ) u_attest_sw_binding_3 (
1122 .clk_i (clk_i),
1123 .rst_ni (rst_ni),
1124
1125 // from register interface
1126 .we (attest_sw_binding_3_gated_we),
1127 .wd (attest_sw_binding_3_wd),
1128
1129 // from internal hardware
1130 .de (1'b0),
1131 .d ('0),
1132
1133 // to internal hardware
1134 .qe (),
1135 .q (reg2hw.attest_sw_binding[3].q),
1136 .ds (),
1137
1138 // to register interface (read)
1139 .qs (attest_sw_binding_3_qs)
1140 );
1141
1142
1143 // Subregister 4 of Multireg attest_sw_binding
1144 // R[attest_sw_binding_4]: V(False)
1145 // Create REGWEN-gated WE signal
1146 logic attest_sw_binding_4_gated_we;
1147 1/1 assign attest_sw_binding_4_gated_we = attest_sw_binding_4_we & sw_binding_regwen_qs;
Tests: T1 T2 T3
1148 prim_subreg #(
1149 .DW (32),
1150 .SwAccess(prim_subreg_pkg::SwAccessRW),
1151 .RESVAL (32'h0),
1152 .Mubi (1'b0)
1153 ) u_attest_sw_binding_4 (
1154 .clk_i (clk_i),
1155 .rst_ni (rst_ni),
1156
1157 // from register interface
1158 .we (attest_sw_binding_4_gated_we),
1159 .wd (attest_sw_binding_4_wd),
1160
1161 // from internal hardware
1162 .de (1'b0),
1163 .d ('0),
1164
1165 // to internal hardware
1166 .qe (),
1167 .q (reg2hw.attest_sw_binding[4].q),
1168 .ds (),
1169
1170 // to register interface (read)
1171 .qs (attest_sw_binding_4_qs)
1172 );
1173
1174
1175 // Subregister 5 of Multireg attest_sw_binding
1176 // R[attest_sw_binding_5]: V(False)
1177 // Create REGWEN-gated WE signal
1178 logic attest_sw_binding_5_gated_we;
1179 1/1 assign attest_sw_binding_5_gated_we = attest_sw_binding_5_we & sw_binding_regwen_qs;
Tests: T1 T2 T3
1180 prim_subreg #(
1181 .DW (32),
1182 .SwAccess(prim_subreg_pkg::SwAccessRW),
1183 .RESVAL (32'h0),
1184 .Mubi (1'b0)
1185 ) u_attest_sw_binding_5 (
1186 .clk_i (clk_i),
1187 .rst_ni (rst_ni),
1188
1189 // from register interface
1190 .we (attest_sw_binding_5_gated_we),
1191 .wd (attest_sw_binding_5_wd),
1192
1193 // from internal hardware
1194 .de (1'b0),
1195 .d ('0),
1196
1197 // to internal hardware
1198 .qe (),
1199 .q (reg2hw.attest_sw_binding[5].q),
1200 .ds (),
1201
1202 // to register interface (read)
1203 .qs (attest_sw_binding_5_qs)
1204 );
1205
1206
1207 // Subregister 6 of Multireg attest_sw_binding
1208 // R[attest_sw_binding_6]: V(False)
1209 // Create REGWEN-gated WE signal
1210 logic attest_sw_binding_6_gated_we;
1211 1/1 assign attest_sw_binding_6_gated_we = attest_sw_binding_6_we & sw_binding_regwen_qs;
Tests: T1 T2 T3
1212 prim_subreg #(
1213 .DW (32),
1214 .SwAccess(prim_subreg_pkg::SwAccessRW),
1215 .RESVAL (32'h0),
1216 .Mubi (1'b0)
1217 ) u_attest_sw_binding_6 (
1218 .clk_i (clk_i),
1219 .rst_ni (rst_ni),
1220
1221 // from register interface
1222 .we (attest_sw_binding_6_gated_we),
1223 .wd (attest_sw_binding_6_wd),
1224
1225 // from internal hardware
1226 .de (1'b0),
1227 .d ('0),
1228
1229 // to internal hardware
1230 .qe (),
1231 .q (reg2hw.attest_sw_binding[6].q),
1232 .ds (),
1233
1234 // to register interface (read)
1235 .qs (attest_sw_binding_6_qs)
1236 );
1237
1238
1239 // Subregister 7 of Multireg attest_sw_binding
1240 // R[attest_sw_binding_7]: V(False)
1241 // Create REGWEN-gated WE signal
1242 logic attest_sw_binding_7_gated_we;
1243 1/1 assign attest_sw_binding_7_gated_we = attest_sw_binding_7_we & sw_binding_regwen_qs;
Tests: T1 T2 T3
1244 prim_subreg #(
1245 .DW (32),
1246 .SwAccess(prim_subreg_pkg::SwAccessRW),
1247 .RESVAL (32'h0),
1248 .Mubi (1'b0)
1249 ) u_attest_sw_binding_7 (
1250 .clk_i (clk_i),
1251 .rst_ni (rst_ni),
1252
1253 // from register interface
1254 .we (attest_sw_binding_7_gated_we),
1255 .wd (attest_sw_binding_7_wd),
1256
1257 // from internal hardware
1258 .de (1'b0),
1259 .d ('0),
1260
1261 // to internal hardware
1262 .qe (),
1263 .q (reg2hw.attest_sw_binding[7].q),
1264 .ds (),
1265
1266 // to register interface (read)
1267 .qs (attest_sw_binding_7_qs)
1268 );
1269
1270
1271 // Subregister 0 of Multireg salt
1272 // R[salt_0]: V(False)
1273 // Create REGWEN-gated WE signal
1274 logic salt_0_gated_we;
1275 1/1 assign salt_0_gated_we = salt_0_we & cfg_regwen_qs;
Tests: T1 T2 T3
1276 prim_subreg #(
1277 .DW (32),
1278 .SwAccess(prim_subreg_pkg::SwAccessRW),
1279 .RESVAL (32'h0),
1280 .Mubi (1'b0)
1281 ) u_salt_0 (
1282 .clk_i (clk_i),
1283 .rst_ni (rst_ni),
1284
1285 // from register interface
1286 .we (salt_0_gated_we),
1287 .wd (salt_0_wd),
1288
1289 // from internal hardware
1290 .de (1'b0),
1291 .d ('0),
1292
1293 // to internal hardware
1294 .qe (),
1295 .q (reg2hw.salt[0].q),
1296 .ds (),
1297
1298 // to register interface (read)
1299 .qs (salt_0_qs)
1300 );
1301
1302
1303 // Subregister 1 of Multireg salt
1304 // R[salt_1]: V(False)
1305 // Create REGWEN-gated WE signal
1306 logic salt_1_gated_we;
1307 1/1 assign salt_1_gated_we = salt_1_we & cfg_regwen_qs;
Tests: T1 T2 T3
1308 prim_subreg #(
1309 .DW (32),
1310 .SwAccess(prim_subreg_pkg::SwAccessRW),
1311 .RESVAL (32'h0),
1312 .Mubi (1'b0)
1313 ) u_salt_1 (
1314 .clk_i (clk_i),
1315 .rst_ni (rst_ni),
1316
1317 // from register interface
1318 .we (salt_1_gated_we),
1319 .wd (salt_1_wd),
1320
1321 // from internal hardware
1322 .de (1'b0),
1323 .d ('0),
1324
1325 // to internal hardware
1326 .qe (),
1327 .q (reg2hw.salt[1].q),
1328 .ds (),
1329
1330 // to register interface (read)
1331 .qs (salt_1_qs)
1332 );
1333
1334
1335 // Subregister 2 of Multireg salt
1336 // R[salt_2]: V(False)
1337 // Create REGWEN-gated WE signal
1338 logic salt_2_gated_we;
1339 1/1 assign salt_2_gated_we = salt_2_we & cfg_regwen_qs;
Tests: T1 T2 T3
1340 prim_subreg #(
1341 .DW (32),
1342 .SwAccess(prim_subreg_pkg::SwAccessRW),
1343 .RESVAL (32'h0),
1344 .Mubi (1'b0)
1345 ) u_salt_2 (
1346 .clk_i (clk_i),
1347 .rst_ni (rst_ni),
1348
1349 // from register interface
1350 .we (salt_2_gated_we),
1351 .wd (salt_2_wd),
1352
1353 // from internal hardware
1354 .de (1'b0),
1355 .d ('0),
1356
1357 // to internal hardware
1358 .qe (),
1359 .q (reg2hw.salt[2].q),
1360 .ds (),
1361
1362 // to register interface (read)
1363 .qs (salt_2_qs)
1364 );
1365
1366
1367 // Subregister 3 of Multireg salt
1368 // R[salt_3]: V(False)
1369 // Create REGWEN-gated WE signal
1370 logic salt_3_gated_we;
1371 1/1 assign salt_3_gated_we = salt_3_we & cfg_regwen_qs;
Tests: T1 T2 T3
1372 prim_subreg #(
1373 .DW (32),
1374 .SwAccess(prim_subreg_pkg::SwAccessRW),
1375 .RESVAL (32'h0),
1376 .Mubi (1'b0)
1377 ) u_salt_3 (
1378 .clk_i (clk_i),
1379 .rst_ni (rst_ni),
1380
1381 // from register interface
1382 .we (salt_3_gated_we),
1383 .wd (salt_3_wd),
1384
1385 // from internal hardware
1386 .de (1'b0),
1387 .d ('0),
1388
1389 // to internal hardware
1390 .qe (),
1391 .q (reg2hw.salt[3].q),
1392 .ds (),
1393
1394 // to register interface (read)
1395 .qs (salt_3_qs)
1396 );
1397
1398
1399 // Subregister 4 of Multireg salt
1400 // R[salt_4]: V(False)
1401 // Create REGWEN-gated WE signal
1402 logic salt_4_gated_we;
1403 1/1 assign salt_4_gated_we = salt_4_we & cfg_regwen_qs;
Tests: T1 T2 T3
1404 prim_subreg #(
1405 .DW (32),
1406 .SwAccess(prim_subreg_pkg::SwAccessRW),
1407 .RESVAL (32'h0),
1408 .Mubi (1'b0)
1409 ) u_salt_4 (
1410 .clk_i (clk_i),
1411 .rst_ni (rst_ni),
1412
1413 // from register interface
1414 .we (salt_4_gated_we),
1415 .wd (salt_4_wd),
1416
1417 // from internal hardware
1418 .de (1'b0),
1419 .d ('0),
1420
1421 // to internal hardware
1422 .qe (),
1423 .q (reg2hw.salt[4].q),
1424 .ds (),
1425
1426 // to register interface (read)
1427 .qs (salt_4_qs)
1428 );
1429
1430
1431 // Subregister 5 of Multireg salt
1432 // R[salt_5]: V(False)
1433 // Create REGWEN-gated WE signal
1434 logic salt_5_gated_we;
1435 1/1 assign salt_5_gated_we = salt_5_we & cfg_regwen_qs;
Tests: T1 T2 T3
1436 prim_subreg #(
1437 .DW (32),
1438 .SwAccess(prim_subreg_pkg::SwAccessRW),
1439 .RESVAL (32'h0),
1440 .Mubi (1'b0)
1441 ) u_salt_5 (
1442 .clk_i (clk_i),
1443 .rst_ni (rst_ni),
1444
1445 // from register interface
1446 .we (salt_5_gated_we),
1447 .wd (salt_5_wd),
1448
1449 // from internal hardware
1450 .de (1'b0),
1451 .d ('0),
1452
1453 // to internal hardware
1454 .qe (),
1455 .q (reg2hw.salt[5].q),
1456 .ds (),
1457
1458 // to register interface (read)
1459 .qs (salt_5_qs)
1460 );
1461
1462
1463 // Subregister 6 of Multireg salt
1464 // R[salt_6]: V(False)
1465 // Create REGWEN-gated WE signal
1466 logic salt_6_gated_we;
1467 1/1 assign salt_6_gated_we = salt_6_we & cfg_regwen_qs;
Tests: T1 T2 T3
1468 prim_subreg #(
1469 .DW (32),
1470 .SwAccess(prim_subreg_pkg::SwAccessRW),
1471 .RESVAL (32'h0),
1472 .Mubi (1'b0)
1473 ) u_salt_6 (
1474 .clk_i (clk_i),
1475 .rst_ni (rst_ni),
1476
1477 // from register interface
1478 .we (salt_6_gated_we),
1479 .wd (salt_6_wd),
1480
1481 // from internal hardware
1482 .de (1'b0),
1483 .d ('0),
1484
1485 // to internal hardware
1486 .qe (),
1487 .q (reg2hw.salt[6].q),
1488 .ds (),
1489
1490 // to register interface (read)
1491 .qs (salt_6_qs)
1492 );
1493
1494
1495 // Subregister 7 of Multireg salt
1496 // R[salt_7]: V(False)
1497 // Create REGWEN-gated WE signal
1498 logic salt_7_gated_we;
1499 1/1 assign salt_7_gated_we = salt_7_we & cfg_regwen_qs;
Tests: T1 T2 T3
1500 prim_subreg #(
1501 .DW (32),
1502 .SwAccess(prim_subreg_pkg::SwAccessRW),
1503 .RESVAL (32'h0),
1504 .Mubi (1'b0)
1505 ) u_salt_7 (
1506 .clk_i (clk_i),
1507 .rst_ni (rst_ni),
1508
1509 // from register interface
1510 .we (salt_7_gated_we),
1511 .wd (salt_7_wd),
1512
1513 // from internal hardware
1514 .de (1'b0),
1515 .d ('0),
1516
1517 // to internal hardware
1518 .qe (),
1519 .q (reg2hw.salt[7].q),
1520 .ds (),
1521
1522 // to register interface (read)
1523 .qs (salt_7_qs)
1524 );
1525
1526
1527 // Subregister 0 of Multireg key_version
1528 // R[key_version]: V(False)
1529 // Create REGWEN-gated WE signal
1530 logic key_version_gated_we;
1531 1/1 assign key_version_gated_we = key_version_we & cfg_regwen_qs;
Tests: T1 T2 T3
1532 prim_subreg #(
1533 .DW (32),
1534 .SwAccess(prim_subreg_pkg::SwAccessRW),
1535 .RESVAL (32'h0),
1536 .Mubi (1'b0)
1537 ) u_key_version (
1538 .clk_i (clk_i),
1539 .rst_ni (rst_ni),
1540
1541 // from register interface
1542 .we (key_version_gated_we),
1543 .wd (key_version_wd),
1544
1545 // from internal hardware
1546 .de (1'b0),
1547 .d ('0),
1548
1549 // to internal hardware
1550 .qe (),
1551 .q (reg2hw.key_version[0].q),
1552 .ds (),
1553
1554 // to register interface (read)
1555 .qs (key_version_qs)
1556 );
1557
1558
1559 // R[max_creator_key_ver_regwen]: V(False)
1560 prim_subreg #(
1561 .DW (1),
1562 .SwAccess(prim_subreg_pkg::SwAccessW0C),
1563 .RESVAL (1'h1),
1564 .Mubi (1'b0)
1565 ) u_max_creator_key_ver_regwen (
1566 .clk_i (clk_i),
1567 .rst_ni (rst_ni),
1568
1569 // from register interface
1570 .we (max_creator_key_ver_regwen_we),
1571 .wd (max_creator_key_ver_regwen_wd),
1572
1573 // from internal hardware
1574 .de (1'b0),
1575 .d ('0),
1576
1577 // to internal hardware
1578 .qe (),
1579 .q (),
1580 .ds (),
1581
1582 // to register interface (read)
1583 .qs (max_creator_key_ver_regwen_qs)
1584 );
1585
1586
1587 // R[max_creator_key_ver_shadowed]: V(False)
1588 // Create REGWEN-gated WE signal
1589 logic max_creator_key_ver_shadowed_gated_we;
1590 1/1 assign max_creator_key_ver_shadowed_gated_we =
Tests: T1 T2 T3
1591 max_creator_key_ver_shadowed_we & max_creator_key_ver_regwen_qs;
1592 prim_subreg_shadow #(
1593 .DW (32),
1594 .SwAccess(prim_subreg_pkg::SwAccessRW),
1595 .RESVAL (32'h0),
1596 .Mubi (1'b0)
1597 ) u_max_creator_key_ver_shadowed (
1598 .clk_i (clk_i),
1599 .rst_ni (rst_ni),
1600 .rst_shadowed_ni (rst_shadowed_ni),
1601
1602 // from register interface
1603 .re (max_creator_key_ver_shadowed_re),
1604 .we (max_creator_key_ver_shadowed_gated_we),
1605 .wd (max_creator_key_ver_shadowed_wd),
1606
1607 // from internal hardware
1608 .de (1'b0),
1609 .d ('0),
1610
1611 // to internal hardware
1612 .qe (),
1613 .q (reg2hw.max_creator_key_ver_shadowed.q),
1614 .ds (),
1615
1616 // to register interface (read)
1617 .qs (max_creator_key_ver_shadowed_qs),
1618
1619 // Shadow register phase. Relevant for hwext only.
1620 .phase (),
1621
1622 // Shadow register error conditions
1623 .err_update (max_creator_key_ver_shadowed_update_err),
1624 .err_storage (max_creator_key_ver_shadowed_storage_err)
1625 );
1626
1627
1628 // R[max_owner_int_key_ver_regwen]: V(False)
1629 prim_subreg #(
1630 .DW (1),
1631 .SwAccess(prim_subreg_pkg::SwAccessW0C),
1632 .RESVAL (1'h1),
1633 .Mubi (1'b0)
1634 ) u_max_owner_int_key_ver_regwen (
1635 .clk_i (clk_i),
1636 .rst_ni (rst_ni),
1637
1638 // from register interface
1639 .we (max_owner_int_key_ver_regwen_we),
1640 .wd (max_owner_int_key_ver_regwen_wd),
1641
1642 // from internal hardware
1643 .de (1'b0),
1644 .d ('0),
1645
1646 // to internal hardware
1647 .qe (),
1648 .q (),
1649 .ds (),
1650
1651 // to register interface (read)
1652 .qs (max_owner_int_key_ver_regwen_qs)
1653 );
1654
1655
1656 // R[max_owner_int_key_ver_shadowed]: V(False)
1657 // Create REGWEN-gated WE signal
1658 logic max_owner_int_key_ver_shadowed_gated_we;
1659 1/1 assign max_owner_int_key_ver_shadowed_gated_we =
Tests: T1 T2 T3
1660 max_owner_int_key_ver_shadowed_we & max_owner_int_key_ver_regwen_qs;
1661 prim_subreg_shadow #(
1662 .DW (32),
1663 .SwAccess(prim_subreg_pkg::SwAccessRW),
1664 .RESVAL (32'h1),
1665 .Mubi (1'b0)
1666 ) u_max_owner_int_key_ver_shadowed (
1667 .clk_i (clk_i),
1668 .rst_ni (rst_ni),
1669 .rst_shadowed_ni (rst_shadowed_ni),
1670
1671 // from register interface
1672 .re (max_owner_int_key_ver_shadowed_re),
1673 .we (max_owner_int_key_ver_shadowed_gated_we),
1674 .wd (max_owner_int_key_ver_shadowed_wd),
1675
1676 // from internal hardware
1677 .de (1'b0),
1678 .d ('0),
1679
1680 // to internal hardware
1681 .qe (),
1682 .q (reg2hw.max_owner_int_key_ver_shadowed.q),
1683 .ds (),
1684
1685 // to register interface (read)
1686 .qs (max_owner_int_key_ver_shadowed_qs),
1687
1688 // Shadow register phase. Relevant for hwext only.
1689 .phase (),
1690
1691 // Shadow register error conditions
1692 .err_update (max_owner_int_key_ver_shadowed_update_err),
1693 .err_storage (max_owner_int_key_ver_shadowed_storage_err)
1694 );
1695
1696
1697 // R[max_owner_key_ver_regwen]: V(False)
1698 prim_subreg #(
1699 .DW (1),
1700 .SwAccess(prim_subreg_pkg::SwAccessW0C),
1701 .RESVAL (1'h1),
1702 .Mubi (1'b0)
1703 ) u_max_owner_key_ver_regwen (
1704 .clk_i (clk_i),
1705 .rst_ni (rst_ni),
1706
1707 // from register interface
1708 .we (max_owner_key_ver_regwen_we),
1709 .wd (max_owner_key_ver_regwen_wd),
1710
1711 // from internal hardware
1712 .de (1'b0),
1713 .d ('0),
1714
1715 // to internal hardware
1716 .qe (),
1717 .q (),
1718 .ds (),
1719
1720 // to register interface (read)
1721 .qs (max_owner_key_ver_regwen_qs)
1722 );
1723
1724
1725 // R[max_owner_key_ver_shadowed]: V(False)
1726 // Create REGWEN-gated WE signal
1727 logic max_owner_key_ver_shadowed_gated_we;
1728 1/1 assign max_owner_key_ver_shadowed_gated_we =
Tests: T1 T2 T3
1729 max_owner_key_ver_shadowed_we & max_owner_key_ver_regwen_qs;
1730 prim_subreg_shadow #(
1731 .DW (32),
1732 .SwAccess(prim_subreg_pkg::SwAccessRW),
1733 .RESVAL (32'h0),
1734 .Mubi (1'b0)
1735 ) u_max_owner_key_ver_shadowed (
1736 .clk_i (clk_i),
1737 .rst_ni (rst_ni),
1738 .rst_shadowed_ni (rst_shadowed_ni),
1739
1740 // from register interface
1741 .re (max_owner_key_ver_shadowed_re),
1742 .we (max_owner_key_ver_shadowed_gated_we),
1743 .wd (max_owner_key_ver_shadowed_wd),
1744
1745 // from internal hardware
1746 .de (1'b0),
1747 .d ('0),
1748
1749 // to internal hardware
1750 .qe (),
1751 .q (reg2hw.max_owner_key_ver_shadowed.q),
1752 .ds (),
1753
1754 // to register interface (read)
1755 .qs (max_owner_key_ver_shadowed_qs),
1756
1757 // Shadow register phase. Relevant for hwext only.
1758 .phase (),
1759
1760 // Shadow register error conditions
1761 .err_update (max_owner_key_ver_shadowed_update_err),
1762 .err_storage (max_owner_key_ver_shadowed_storage_err)
1763 );
1764
1765
1766 // Subregister 0 of Multireg sw_share0_output
1767 // R[sw_share0_output_0]: V(False)
1768 prim_subreg #(
1769 .DW (32),
1770 .SwAccess(prim_subreg_pkg::SwAccessRC),
1771 .RESVAL (32'h0),
1772 .Mubi (1'b0)
1773 ) u_sw_share0_output_0 (
1774 .clk_i (clk_i),
1775 .rst_ni (rst_ni),
1776
1777 // from register interface
1778 .we (sw_share0_output_0_re),
1779 .wd (sw_share0_output_0_wd),
1780
1781 // from internal hardware
1782 .de (hw2reg.sw_share0_output[0].de),
1783 .d (hw2reg.sw_share0_output[0].d),
1784
1785 // to internal hardware
1786 .qe (),
1787 .q (),
1788 .ds (),
1789
1790 // to register interface (read)
1791 .qs (sw_share0_output_0_qs)
1792 );
1793
1794
1795 // Subregister 1 of Multireg sw_share0_output
1796 // R[sw_share0_output_1]: V(False)
1797 prim_subreg #(
1798 .DW (32),
1799 .SwAccess(prim_subreg_pkg::SwAccessRC),
1800 .RESVAL (32'h0),
1801 .Mubi (1'b0)
1802 ) u_sw_share0_output_1 (
1803 .clk_i (clk_i),
1804 .rst_ni (rst_ni),
1805
1806 // from register interface
1807 .we (sw_share0_output_1_re),
1808 .wd (sw_share0_output_1_wd),
1809
1810 // from internal hardware
1811 .de (hw2reg.sw_share0_output[1].de),
1812 .d (hw2reg.sw_share0_output[1].d),
1813
1814 // to internal hardware
1815 .qe (),
1816 .q (),
1817 .ds (),
1818
1819 // to register interface (read)
1820 .qs (sw_share0_output_1_qs)
1821 );
1822
1823
1824 // Subregister 2 of Multireg sw_share0_output
1825 // R[sw_share0_output_2]: V(False)
1826 prim_subreg #(
1827 .DW (32),
1828 .SwAccess(prim_subreg_pkg::SwAccessRC),
1829 .RESVAL (32'h0),
1830 .Mubi (1'b0)
1831 ) u_sw_share0_output_2 (
1832 .clk_i (clk_i),
1833 .rst_ni (rst_ni),
1834
1835 // from register interface
1836 .we (sw_share0_output_2_re),
1837 .wd (sw_share0_output_2_wd),
1838
1839 // from internal hardware
1840 .de (hw2reg.sw_share0_output[2].de),
1841 .d (hw2reg.sw_share0_output[2].d),
1842
1843 // to internal hardware
1844 .qe (),
1845 .q (),
1846 .ds (),
1847
1848 // to register interface (read)
1849 .qs (sw_share0_output_2_qs)
1850 );
1851
1852
1853 // Subregister 3 of Multireg sw_share0_output
1854 // R[sw_share0_output_3]: V(False)
1855 prim_subreg #(
1856 .DW (32),
1857 .SwAccess(prim_subreg_pkg::SwAccessRC),
1858 .RESVAL (32'h0),
1859 .Mubi (1'b0)
1860 ) u_sw_share0_output_3 (
1861 .clk_i (clk_i),
1862 .rst_ni (rst_ni),
1863
1864 // from register interface
1865 .we (sw_share0_output_3_re),
1866 .wd (sw_share0_output_3_wd),
1867
1868 // from internal hardware
1869 .de (hw2reg.sw_share0_output[3].de),
1870 .d (hw2reg.sw_share0_output[3].d),
1871
1872 // to internal hardware
1873 .qe (),
1874 .q (),
1875 .ds (),
1876
1877 // to register interface (read)
1878 .qs (sw_share0_output_3_qs)
1879 );
1880
1881
1882 // Subregister 4 of Multireg sw_share0_output
1883 // R[sw_share0_output_4]: V(False)
1884 prim_subreg #(
1885 .DW (32),
1886 .SwAccess(prim_subreg_pkg::SwAccessRC),
1887 .RESVAL (32'h0),
1888 .Mubi (1'b0)
1889 ) u_sw_share0_output_4 (
1890 .clk_i (clk_i),
1891 .rst_ni (rst_ni),
1892
1893 // from register interface
1894 .we (sw_share0_output_4_re),
1895 .wd (sw_share0_output_4_wd),
1896
1897 // from internal hardware
1898 .de (hw2reg.sw_share0_output[4].de),
1899 .d (hw2reg.sw_share0_output[4].d),
1900
1901 // to internal hardware
1902 .qe (),
1903 .q (),
1904 .ds (),
1905
1906 // to register interface (read)
1907 .qs (sw_share0_output_4_qs)
1908 );
1909
1910
1911 // Subregister 5 of Multireg sw_share0_output
1912 // R[sw_share0_output_5]: V(False)
1913 prim_subreg #(
1914 .DW (32),
1915 .SwAccess(prim_subreg_pkg::SwAccessRC),
1916 .RESVAL (32'h0),
1917 .Mubi (1'b0)
1918 ) u_sw_share0_output_5 (
1919 .clk_i (clk_i),
1920 .rst_ni (rst_ni),
1921
1922 // from register interface
1923 .we (sw_share0_output_5_re),
1924 .wd (sw_share0_output_5_wd),
1925
1926 // from internal hardware
1927 .de (hw2reg.sw_share0_output[5].de),
1928 .d (hw2reg.sw_share0_output[5].d),
1929
1930 // to internal hardware
1931 .qe (),
1932 .q (),
1933 .ds (),
1934
1935 // to register interface (read)
1936 .qs (sw_share0_output_5_qs)
1937 );
1938
1939
1940 // Subregister 6 of Multireg sw_share0_output
1941 // R[sw_share0_output_6]: V(False)
1942 prim_subreg #(
1943 .DW (32),
1944 .SwAccess(prim_subreg_pkg::SwAccessRC),
1945 .RESVAL (32'h0),
1946 .Mubi (1'b0)
1947 ) u_sw_share0_output_6 (
1948 .clk_i (clk_i),
1949 .rst_ni (rst_ni),
1950
1951 // from register interface
1952 .we (sw_share0_output_6_re),
1953 .wd (sw_share0_output_6_wd),
1954
1955 // from internal hardware
1956 .de (hw2reg.sw_share0_output[6].de),
1957 .d (hw2reg.sw_share0_output[6].d),
1958
1959 // to internal hardware
1960 .qe (),
1961 .q (),
1962 .ds (),
1963
1964 // to register interface (read)
1965 .qs (sw_share0_output_6_qs)
1966 );
1967
1968
1969 // Subregister 7 of Multireg sw_share0_output
1970 // R[sw_share0_output_7]: V(False)
1971 prim_subreg #(
1972 .DW (32),
1973 .SwAccess(prim_subreg_pkg::SwAccessRC),
1974 .RESVAL (32'h0),
1975 .Mubi (1'b0)
1976 ) u_sw_share0_output_7 (
1977 .clk_i (clk_i),
1978 .rst_ni (rst_ni),
1979
1980 // from register interface
1981 .we (sw_share0_output_7_re),
1982 .wd (sw_share0_output_7_wd),
1983
1984 // from internal hardware
1985 .de (hw2reg.sw_share0_output[7].de),
1986 .d (hw2reg.sw_share0_output[7].d),
1987
1988 // to internal hardware
1989 .qe (),
1990 .q (),
1991 .ds (),
1992
1993 // to register interface (read)
1994 .qs (sw_share0_output_7_qs)
1995 );
1996
1997
1998 // Subregister 0 of Multireg sw_share1_output
1999 // R[sw_share1_output_0]: V(False)
2000 prim_subreg #(
2001 .DW (32),
2002 .SwAccess(prim_subreg_pkg::SwAccessRC),
2003 .RESVAL (32'h0),
2004 .Mubi (1'b0)
2005 ) u_sw_share1_output_0 (
2006 .clk_i (clk_i),
2007 .rst_ni (rst_ni),
2008
2009 // from register interface
2010 .we (sw_share1_output_0_re),
2011 .wd (sw_share1_output_0_wd),
2012
2013 // from internal hardware
2014 .de (hw2reg.sw_share1_output[0].de),
2015 .d (hw2reg.sw_share1_output[0].d),
2016
2017 // to internal hardware
2018 .qe (),
2019 .q (),
2020 .ds (),
2021
2022 // to register interface (read)
2023 .qs (sw_share1_output_0_qs)
2024 );
2025
2026
2027 // Subregister 1 of Multireg sw_share1_output
2028 // R[sw_share1_output_1]: V(False)
2029 prim_subreg #(
2030 .DW (32),
2031 .SwAccess(prim_subreg_pkg::SwAccessRC),
2032 .RESVAL (32'h0),
2033 .Mubi (1'b0)
2034 ) u_sw_share1_output_1 (
2035 .clk_i (clk_i),
2036 .rst_ni (rst_ni),
2037
2038 // from register interface
2039 .we (sw_share1_output_1_re),
2040 .wd (sw_share1_output_1_wd),
2041
2042 // from internal hardware
2043 .de (hw2reg.sw_share1_output[1].de),
2044 .d (hw2reg.sw_share1_output[1].d),
2045
2046 // to internal hardware
2047 .qe (),
2048 .q (),
2049 .ds (),
2050
2051 // to register interface (read)
2052 .qs (sw_share1_output_1_qs)
2053 );
2054
2055
2056 // Subregister 2 of Multireg sw_share1_output
2057 // R[sw_share1_output_2]: V(False)
2058 prim_subreg #(
2059 .DW (32),
2060 .SwAccess(prim_subreg_pkg::SwAccessRC),
2061 .RESVAL (32'h0),
2062 .Mubi (1'b0)
2063 ) u_sw_share1_output_2 (
2064 .clk_i (clk_i),
2065 .rst_ni (rst_ni),
2066
2067 // from register interface
2068 .we (sw_share1_output_2_re),
2069 .wd (sw_share1_output_2_wd),
2070
2071 // from internal hardware
2072 .de (hw2reg.sw_share1_output[2].de),
2073 .d (hw2reg.sw_share1_output[2].d),
2074
2075 // to internal hardware
2076 .qe (),
2077 .q (),
2078 .ds (),
2079
2080 // to register interface (read)
2081 .qs (sw_share1_output_2_qs)
2082 );
2083
2084
2085 // Subregister 3 of Multireg sw_share1_output
2086 // R[sw_share1_output_3]: V(False)
2087 prim_subreg #(
2088 .DW (32),
2089 .SwAccess(prim_subreg_pkg::SwAccessRC),
2090 .RESVAL (32'h0),
2091 .Mubi (1'b0)
2092 ) u_sw_share1_output_3 (
2093 .clk_i (clk_i),
2094 .rst_ni (rst_ni),
2095
2096 // from register interface
2097 .we (sw_share1_output_3_re),
2098 .wd (sw_share1_output_3_wd),
2099
2100 // from internal hardware
2101 .de (hw2reg.sw_share1_output[3].de),
2102 .d (hw2reg.sw_share1_output[3].d),
2103
2104 // to internal hardware
2105 .qe (),
2106 .q (),
2107 .ds (),
2108
2109 // to register interface (read)
2110 .qs (sw_share1_output_3_qs)
2111 );
2112
2113
2114 // Subregister 4 of Multireg sw_share1_output
2115 // R[sw_share1_output_4]: V(False)
2116 prim_subreg #(
2117 .DW (32),
2118 .SwAccess(prim_subreg_pkg::SwAccessRC),
2119 .RESVAL (32'h0),
2120 .Mubi (1'b0)
2121 ) u_sw_share1_output_4 (
2122 .clk_i (clk_i),
2123 .rst_ni (rst_ni),
2124
2125 // from register interface
2126 .we (sw_share1_output_4_re),
2127 .wd (sw_share1_output_4_wd),
2128
2129 // from internal hardware
2130 .de (hw2reg.sw_share1_output[4].de),
2131 .d (hw2reg.sw_share1_output[4].d),
2132
2133 // to internal hardware
2134 .qe (),
2135 .q (),
2136 .ds (),
2137
2138 // to register interface (read)
2139 .qs (sw_share1_output_4_qs)
2140 );
2141
2142
2143 // Subregister 5 of Multireg sw_share1_output
2144 // R[sw_share1_output_5]: V(False)
2145 prim_subreg #(
2146 .DW (32),
2147 .SwAccess(prim_subreg_pkg::SwAccessRC),
2148 .RESVAL (32'h0),
2149 .Mubi (1'b0)
2150 ) u_sw_share1_output_5 (
2151 .clk_i (clk_i),
2152 .rst_ni (rst_ni),
2153
2154 // from register interface
2155 .we (sw_share1_output_5_re),
2156 .wd (sw_share1_output_5_wd),
2157
2158 // from internal hardware
2159 .de (hw2reg.sw_share1_output[5].de),
2160 .d (hw2reg.sw_share1_output[5].d),
2161
2162 // to internal hardware
2163 .qe (),
2164 .q (),
2165 .ds (),
2166
2167 // to register interface (read)
2168 .qs (sw_share1_output_5_qs)
2169 );
2170
2171
2172 // Subregister 6 of Multireg sw_share1_output
2173 // R[sw_share1_output_6]: V(False)
2174 prim_subreg #(
2175 .DW (32),
2176 .SwAccess(prim_subreg_pkg::SwAccessRC),
2177 .RESVAL (32'h0),
2178 .Mubi (1'b0)
2179 ) u_sw_share1_output_6 (
2180 .clk_i (clk_i),
2181 .rst_ni (rst_ni),
2182
2183 // from register interface
2184 .we (sw_share1_output_6_re),
2185 .wd (sw_share1_output_6_wd),
2186
2187 // from internal hardware
2188 .de (hw2reg.sw_share1_output[6].de),
2189 .d (hw2reg.sw_share1_output[6].d),
2190
2191 // to internal hardware
2192 .qe (),
2193 .q (),
2194 .ds (),
2195
2196 // to register interface (read)
2197 .qs (sw_share1_output_6_qs)
2198 );
2199
2200
2201 // Subregister 7 of Multireg sw_share1_output
2202 // R[sw_share1_output_7]: V(False)
2203 prim_subreg #(
2204 .DW (32),
2205 .SwAccess(prim_subreg_pkg::SwAccessRC),
2206 .RESVAL (32'h0),
2207 .Mubi (1'b0)
2208 ) u_sw_share1_output_7 (
2209 .clk_i (clk_i),
2210 .rst_ni (rst_ni),
2211
2212 // from register interface
2213 .we (sw_share1_output_7_re),
2214 .wd (sw_share1_output_7_wd),
2215
2216 // from internal hardware
2217 .de (hw2reg.sw_share1_output[7].de),
2218 .d (hw2reg.sw_share1_output[7].d),
2219
2220 // to internal hardware
2221 .qe (),
2222 .q (),
2223 .ds (),
2224
2225 // to register interface (read)
2226 .qs (sw_share1_output_7_qs)
2227 );
2228
2229
2230 // R[working_state]: V(False)
2231 prim_subreg #(
2232 .DW (3),
2233 .SwAccess(prim_subreg_pkg::SwAccessRO),
2234 .RESVAL (3'h0),
2235 .Mubi (1'b0)
2236 ) u_working_state (
2237 .clk_i (clk_i),
2238 .rst_ni (rst_ni),
2239
2240 // from register interface
2241 .we (1'b0),
2242 .wd ('0),
2243
2244 // from internal hardware
2245 .de (hw2reg.working_state.de),
2246 .d (hw2reg.working_state.d),
2247
2248 // to internal hardware
2249 .qe (),
2250 .q (),
2251 .ds (),
2252
2253 // to register interface (read)
2254 .qs (working_state_qs)
2255 );
2256
2257
2258 // R[op_status]: V(False)
2259 prim_subreg #(
2260 .DW (2),
2261 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2262 .RESVAL (2'h0),
2263 .Mubi (1'b0)
2264 ) u_op_status (
2265 .clk_i (clk_i),
2266 .rst_ni (rst_ni),
2267
2268 // from register interface
2269 .we (op_status_we),
2270 .wd (op_status_wd),
2271
2272 // from internal hardware
2273 .de (hw2reg.op_status.de),
2274 .d (hw2reg.op_status.d),
2275
2276 // to internal hardware
2277 .qe (),
2278 .q (),
2279 .ds (),
2280
2281 // to register interface (read)
2282 .qs (op_status_qs)
2283 );
2284
2285
2286 // R[err_code]: V(False)
2287 // F[invalid_op]: 0:0
2288 prim_subreg #(
2289 .DW (1),
2290 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2291 .RESVAL (1'h0),
2292 .Mubi (1'b0)
2293 ) u_err_code_invalid_op (
2294 .clk_i (clk_i),
2295 .rst_ni (rst_ni),
2296
2297 // from register interface
2298 .we (err_code_we),
2299 .wd (err_code_invalid_op_wd),
2300
2301 // from internal hardware
2302 .de (hw2reg.err_code.invalid_op.de),
2303 .d (hw2reg.err_code.invalid_op.d),
2304
2305 // to internal hardware
2306 .qe (),
2307 .q (),
2308 .ds (),
2309
2310 // to register interface (read)
2311 .qs (err_code_invalid_op_qs)
2312 );
2313
2314 // F[invalid_kmac_input]: 1:1
2315 prim_subreg #(
2316 .DW (1),
2317 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2318 .RESVAL (1'h0),
2319 .Mubi (1'b0)
2320 ) u_err_code_invalid_kmac_input (
2321 .clk_i (clk_i),
2322 .rst_ni (rst_ni),
2323
2324 // from register interface
2325 .we (err_code_we),
2326 .wd (err_code_invalid_kmac_input_wd),
2327
2328 // from internal hardware
2329 .de (hw2reg.err_code.invalid_kmac_input.de),
2330 .d (hw2reg.err_code.invalid_kmac_input.d),
2331
2332 // to internal hardware
2333 .qe (),
2334 .q (),
2335 .ds (),
2336
2337 // to register interface (read)
2338 .qs (err_code_invalid_kmac_input_qs)
2339 );
2340
2341 // F[invalid_shadow_update]: 2:2
2342 prim_subreg #(
2343 .DW (1),
2344 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2345 .RESVAL (1'h0),
2346 .Mubi (1'b0)
2347 ) u_err_code_invalid_shadow_update (
2348 .clk_i (clk_i),
2349 .rst_ni (rst_ni),
2350
2351 // from register interface
2352 .we (err_code_we),
2353 .wd (err_code_invalid_shadow_update_wd),
2354
2355 // from internal hardware
2356 .de (hw2reg.err_code.invalid_shadow_update.de),
2357 .d (hw2reg.err_code.invalid_shadow_update.d),
2358
2359 // to internal hardware
2360 .qe (),
2361 .q (),
2362 .ds (),
2363
2364 // to register interface (read)
2365 .qs (err_code_invalid_shadow_update_qs)
2366 );
2367
2368
2369 // R[fault_status]: V(False)
2370 // F[cmd]: 0:0
2371 prim_subreg #(
2372 .DW (1),
2373 .SwAccess(prim_subreg_pkg::SwAccessRO),
2374 .RESVAL (1'h0),
2375 .Mubi (1'b0)
2376 ) u_fault_status_cmd (
2377 .clk_i (clk_i),
2378 .rst_ni (rst_ni),
2379
2380 // from register interface
2381 .we (1'b0),
2382 .wd ('0),
2383
2384 // from internal hardware
2385 .de (hw2reg.fault_status.cmd.de),
2386 .d (hw2reg.fault_status.cmd.d),
2387
2388 // to internal hardware
2389 .qe (),
2390 .q (reg2hw.fault_status.cmd.q),
2391 .ds (),
2392
2393 // to register interface (read)
2394 .qs (fault_status_cmd_qs)
2395 );
2396
2397 // F[kmac_fsm]: 1:1
2398 prim_subreg #(
2399 .DW (1),
2400 .SwAccess(prim_subreg_pkg::SwAccessRO),
2401 .RESVAL (1'h0),
2402 .Mubi (1'b0)
2403 ) u_fault_status_kmac_fsm (
2404 .clk_i (clk_i),
2405 .rst_ni (rst_ni),
2406
2407 // from register interface
2408 .we (1'b0),
2409 .wd ('0),
2410
2411 // from internal hardware
2412 .de (hw2reg.fault_status.kmac_fsm.de),
2413 .d (hw2reg.fault_status.kmac_fsm.d),
2414
2415 // to internal hardware
2416 .qe (),
2417 .q (reg2hw.fault_status.kmac_fsm.q),
2418 .ds (),
2419
2420 // to register interface (read)
2421 .qs (fault_status_kmac_fsm_qs)
2422 );
2423
2424 // F[kmac_done]: 2:2
2425 prim_subreg #(
2426 .DW (1),
2427 .SwAccess(prim_subreg_pkg::SwAccessRO),
2428 .RESVAL (1'h0),
2429 .Mubi (1'b0)
2430 ) u_fault_status_kmac_done (
2431 .clk_i (clk_i),
2432 .rst_ni (rst_ni),
2433
2434 // from register interface
2435 .we (1'b0),
2436 .wd ('0),
2437
2438 // from internal hardware
2439 .de (hw2reg.fault_status.kmac_done.de),
2440 .d (hw2reg.fault_status.kmac_done.d),
2441
2442 // to internal hardware
2443 .qe (),
2444 .q (reg2hw.fault_status.kmac_done.q),
2445 .ds (),
2446
2447 // to register interface (read)
2448 .qs (fault_status_kmac_done_qs)
2449 );
2450
2451 // F[kmac_op]: 3:3
2452 prim_subreg #(
2453 .DW (1),
2454 .SwAccess(prim_subreg_pkg::SwAccessRO),
2455 .RESVAL (1'h0),
2456 .Mubi (1'b0)
2457 ) u_fault_status_kmac_op (
2458 .clk_i (clk_i),
2459 .rst_ni (rst_ni),
2460
2461 // from register interface
2462 .we (1'b0),
2463 .wd ('0),
2464
2465 // from internal hardware
2466 .de (hw2reg.fault_status.kmac_op.de),
2467 .d (hw2reg.fault_status.kmac_op.d),
2468
2469 // to internal hardware
2470 .qe (),
2471 .q (reg2hw.fault_status.kmac_op.q),
2472 .ds (),
2473
2474 // to register interface (read)
2475 .qs (fault_status_kmac_op_qs)
2476 );
2477
2478 // F[kmac_out]: 4:4
2479 prim_subreg #(
2480 .DW (1),
2481 .SwAccess(prim_subreg_pkg::SwAccessRO),
2482 .RESVAL (1'h0),
2483 .Mubi (1'b0)
2484 ) u_fault_status_kmac_out (
2485 .clk_i (clk_i),
2486 .rst_ni (rst_ni),
2487
2488 // from register interface
2489 .we (1'b0),
2490 .wd ('0),
2491
2492 // from internal hardware
2493 .de (hw2reg.fault_status.kmac_out.de),
2494 .d (hw2reg.fault_status.kmac_out.d),
2495
2496 // to internal hardware
2497 .qe (),
2498 .q (reg2hw.fault_status.kmac_out.q),
2499 .ds (),
2500
2501 // to register interface (read)
2502 .qs (fault_status_kmac_out_qs)
2503 );
2504
2505 // F[regfile_intg]: 5:5
2506 prim_subreg #(
2507 .DW (1),
2508 .SwAccess(prim_subreg_pkg::SwAccessRO),
2509 .RESVAL (1'h0),
2510 .Mubi (1'b0)
2511 ) u_fault_status_regfile_intg (
2512 .clk_i (clk_i),
2513 .rst_ni (rst_ni),
2514
2515 // from register interface
2516 .we (1'b0),
2517 .wd ('0),
2518
2519 // from internal hardware
2520 .de (hw2reg.fault_status.regfile_intg.de),
2521 .d (hw2reg.fault_status.regfile_intg.d),
2522
2523 // to internal hardware
2524 .qe (),
2525 .q (reg2hw.fault_status.regfile_intg.q),
2526 .ds (),
2527
2528 // to register interface (read)
2529 .qs (fault_status_regfile_intg_qs)
2530 );
2531
2532 // F[shadow]: 6:6
2533 prim_subreg #(
2534 .DW (1),
2535 .SwAccess(prim_subreg_pkg::SwAccessRO),
2536 .RESVAL (1'h0),
2537 .Mubi (1'b0)
2538 ) u_fault_status_shadow (
2539 .clk_i (clk_i),
2540 .rst_ni (rst_ni),
2541
2542 // from register interface
2543 .we (1'b0),
2544 .wd ('0),
2545
2546 // from internal hardware
2547 .de (hw2reg.fault_status.shadow.de),
2548 .d (hw2reg.fault_status.shadow.d),
2549
2550 // to internal hardware
2551 .qe (),
2552 .q (reg2hw.fault_status.shadow.q),
2553 .ds (),
2554
2555 // to register interface (read)
2556 .qs (fault_status_shadow_qs)
2557 );
2558
2559 // F[ctrl_fsm_intg]: 7:7
2560 prim_subreg #(
2561 .DW (1),
2562 .SwAccess(prim_subreg_pkg::SwAccessRO),
2563 .RESVAL (1'h0),
2564 .Mubi (1'b0)
2565 ) u_fault_status_ctrl_fsm_intg (
2566 .clk_i (clk_i),
2567 .rst_ni (rst_ni),
2568
2569 // from register interface
2570 .we (1'b0),
2571 .wd ('0),
2572
2573 // from internal hardware
2574 .de (hw2reg.fault_status.ctrl_fsm_intg.de),
2575 .d (hw2reg.fault_status.ctrl_fsm_intg.d),
2576
2577 // to internal hardware
2578 .qe (),
2579 .q (reg2hw.fault_status.ctrl_fsm_intg.q),
2580 .ds (),
2581
2582 // to register interface (read)
2583 .qs (fault_status_ctrl_fsm_intg_qs)
2584 );
2585
2586 // F[ctrl_fsm_chk]: 8:8
2587 prim_subreg #(
2588 .DW (1),
2589 .SwAccess(prim_subreg_pkg::SwAccessRO),
2590 .RESVAL (1'h0),
2591 .Mubi (1'b0)
2592 ) u_fault_status_ctrl_fsm_chk (
2593 .clk_i (clk_i),
2594 .rst_ni (rst_ni),
2595
2596 // from register interface
2597 .we (1'b0),
2598 .wd ('0),
2599
2600 // from internal hardware
2601 .de (hw2reg.fault_status.ctrl_fsm_chk.de),
2602 .d (hw2reg.fault_status.ctrl_fsm_chk.d),
2603
2604 // to internal hardware
2605 .qe (),
2606 .q (reg2hw.fault_status.ctrl_fsm_chk.q),
2607 .ds (),
2608
2609 // to register interface (read)
2610 .qs (fault_status_ctrl_fsm_chk_qs)
2611 );
2612
2613 // F[ctrl_fsm_cnt]: 9:9
2614 prim_subreg #(
2615 .DW (1),
2616 .SwAccess(prim_subreg_pkg::SwAccessRO),
2617 .RESVAL (1'h0),
2618 .Mubi (1'b0)
2619 ) u_fault_status_ctrl_fsm_cnt (
2620 .clk_i (clk_i),
2621 .rst_ni (rst_ni),
2622
2623 // from register interface
2624 .we (1'b0),
2625 .wd ('0),
2626
2627 // from internal hardware
2628 .de (hw2reg.fault_status.ctrl_fsm_cnt.de),
2629 .d (hw2reg.fault_status.ctrl_fsm_cnt.d),
2630
2631 // to internal hardware
2632 .qe (),
2633 .q (reg2hw.fault_status.ctrl_fsm_cnt.q),
2634 .ds (),
2635
2636 // to register interface (read)
2637 .qs (fault_status_ctrl_fsm_cnt_qs)
2638 );
2639
2640 // F[reseed_cnt]: 10:10
2641 prim_subreg #(
2642 .DW (1),
2643 .SwAccess(prim_subreg_pkg::SwAccessRO),
2644 .RESVAL (1'h0),
2645 .Mubi (1'b0)
2646 ) u_fault_status_reseed_cnt (
2647 .clk_i (clk_i),
2648 .rst_ni (rst_ni),
2649
2650 // from register interface
2651 .we (1'b0),
2652 .wd ('0),
2653
2654 // from internal hardware
2655 .de (hw2reg.fault_status.reseed_cnt.de),
2656 .d (hw2reg.fault_status.reseed_cnt.d),
2657
2658 // to internal hardware
2659 .qe (),
2660 .q (reg2hw.fault_status.reseed_cnt.q),
2661 .ds (),
2662
2663 // to register interface (read)
2664 .qs (fault_status_reseed_cnt_qs)
2665 );
2666
2667 // F[side_ctrl_fsm]: 11:11
2668 prim_subreg #(
2669 .DW (1),
2670 .SwAccess(prim_subreg_pkg::SwAccessRO),
2671 .RESVAL (1'h0),
2672 .Mubi (1'b0)
2673 ) u_fault_status_side_ctrl_fsm (
2674 .clk_i (clk_i),
2675 .rst_ni (rst_ni),
2676
2677 // from register interface
2678 .we (1'b0),
2679 .wd ('0),
2680
2681 // from internal hardware
2682 .de (hw2reg.fault_status.side_ctrl_fsm.de),
2683 .d (hw2reg.fault_status.side_ctrl_fsm.d),
2684
2685 // to internal hardware
2686 .qe (),
2687 .q (reg2hw.fault_status.side_ctrl_fsm.q),
2688 .ds (),
2689
2690 // to register interface (read)
2691 .qs (fault_status_side_ctrl_fsm_qs)
2692 );
2693
2694 // F[side_ctrl_sel]: 12:12
2695 prim_subreg #(
2696 .DW (1),
2697 .SwAccess(prim_subreg_pkg::SwAccessRO),
2698 .RESVAL (1'h0),
2699 .Mubi (1'b0)
2700 ) u_fault_status_side_ctrl_sel (
2701 .clk_i (clk_i),
2702 .rst_ni (rst_ni),
2703
2704 // from register interface
2705 .we (1'b0),
2706 .wd ('0),
2707
2708 // from internal hardware
2709 .de (hw2reg.fault_status.side_ctrl_sel.de),
2710 .d (hw2reg.fault_status.side_ctrl_sel.d),
2711
2712 // to internal hardware
2713 .qe (),
2714 .q (reg2hw.fault_status.side_ctrl_sel.q),
2715 .ds (),
2716
2717 // to register interface (read)
2718 .qs (fault_status_side_ctrl_sel_qs)
2719 );
2720
2721 // F[key_ecc]: 13:13
2722 prim_subreg #(
2723 .DW (1),
2724 .SwAccess(prim_subreg_pkg::SwAccessRO),
2725 .RESVAL (1'h0),
2726 .Mubi (1'b0)
2727 ) u_fault_status_key_ecc (
2728 .clk_i (clk_i),
2729 .rst_ni (rst_ni),
2730
2731 // from register interface
2732 .we (1'b0),
2733 .wd ('0),
2734
2735 // from internal hardware
2736 .de (hw2reg.fault_status.key_ecc.de),
2737 .d (hw2reg.fault_status.key_ecc.d),
2738
2739 // to internal hardware
2740 .qe (),
2741 .q (reg2hw.fault_status.key_ecc.q),
2742 .ds (),
2743
2744 // to register interface (read)
2745 .qs (fault_status_key_ecc_qs)
2746 );
2747
2748
2749 // R[debug]: V(False)
2750 // F[invalid_creator_seed]: 0:0
2751 prim_subreg #(
2752 .DW (1),
2753 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2754 .RESVAL (1'h0),
2755 .Mubi (1'b0)
2756 ) u_debug_invalid_creator_seed (
2757 .clk_i (clk_i),
2758 .rst_ni (rst_ni),
2759
2760 // from register interface
2761 .we (debug_we),
2762 .wd (debug_invalid_creator_seed_wd),
2763
2764 // from internal hardware
2765 .de (hw2reg.debug.invalid_creator_seed.de),
2766 .d (hw2reg.debug.invalid_creator_seed.d),
2767
2768 // to internal hardware
2769 .qe (),
2770 .q (),
2771 .ds (),
2772
2773 // to register interface (read)
2774 .qs (debug_invalid_creator_seed_qs)
2775 );
2776
2777 // F[invalid_owner_seed]: 1:1
2778 prim_subreg #(
2779 .DW (1),
2780 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2781 .RESVAL (1'h0),
2782 .Mubi (1'b0)
2783 ) u_debug_invalid_owner_seed (
2784 .clk_i (clk_i),
2785 .rst_ni (rst_ni),
2786
2787 // from register interface
2788 .we (debug_we),
2789 .wd (debug_invalid_owner_seed_wd),
2790
2791 // from internal hardware
2792 .de (hw2reg.debug.invalid_owner_seed.de),
2793 .d (hw2reg.debug.invalid_owner_seed.d),
2794
2795 // to internal hardware
2796 .qe (),
2797 .q (),
2798 .ds (),
2799
2800 // to register interface (read)
2801 .qs (debug_invalid_owner_seed_qs)
2802 );
2803
2804 // F[invalid_dev_id]: 2:2
2805 prim_subreg #(
2806 .DW (1),
2807 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2808 .RESVAL (1'h0),
2809 .Mubi (1'b0)
2810 ) u_debug_invalid_dev_id (
2811 .clk_i (clk_i),
2812 .rst_ni (rst_ni),
2813
2814 // from register interface
2815 .we (debug_we),
2816 .wd (debug_invalid_dev_id_wd),
2817
2818 // from internal hardware
2819 .de (hw2reg.debug.invalid_dev_id.de),
2820 .d (hw2reg.debug.invalid_dev_id.d),
2821
2822 // to internal hardware
2823 .qe (),
2824 .q (),
2825 .ds (),
2826
2827 // to register interface (read)
2828 .qs (debug_invalid_dev_id_qs)
2829 );
2830
2831 // F[invalid_health_state]: 3:3
2832 prim_subreg #(
2833 .DW (1),
2834 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2835 .RESVAL (1'h0),
2836 .Mubi (1'b0)
2837 ) u_debug_invalid_health_state (
2838 .clk_i (clk_i),
2839 .rst_ni (rst_ni),
2840
2841 // from register interface
2842 .we (debug_we),
2843 .wd (debug_invalid_health_state_wd),
2844
2845 // from internal hardware
2846 .de (hw2reg.debug.invalid_health_state.de),
2847 .d (hw2reg.debug.invalid_health_state.d),
2848
2849 // to internal hardware
2850 .qe (),
2851 .q (),
2852 .ds (),
2853
2854 // to register interface (read)
2855 .qs (debug_invalid_health_state_qs)
2856 );
2857
2858 // F[invalid_key_version]: 4:4
2859 prim_subreg #(
2860 .DW (1),
2861 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2862 .RESVAL (1'h0),
2863 .Mubi (1'b0)
2864 ) u_debug_invalid_key_version (
2865 .clk_i (clk_i),
2866 .rst_ni (rst_ni),
2867
2868 // from register interface
2869 .we (debug_we),
2870 .wd (debug_invalid_key_version_wd),
2871
2872 // from internal hardware
2873 .de (hw2reg.debug.invalid_key_version.de),
2874 .d (hw2reg.debug.invalid_key_version.d),
2875
2876 // to internal hardware
2877 .qe (),
2878 .q (),
2879 .ds (),
2880
2881 // to register interface (read)
2882 .qs (debug_invalid_key_version_qs)
2883 );
2884
2885 // F[invalid_key]: 5:5
2886 prim_subreg #(
2887 .DW (1),
2888 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2889 .RESVAL (1'h0),
2890 .Mubi (1'b0)
2891 ) u_debug_invalid_key (
2892 .clk_i (clk_i),
2893 .rst_ni (rst_ni),
2894
2895 // from register interface
2896 .we (debug_we),
2897 .wd (debug_invalid_key_wd),
2898
2899 // from internal hardware
2900 .de (hw2reg.debug.invalid_key.de),
2901 .d (hw2reg.debug.invalid_key.d),
2902
2903 // to internal hardware
2904 .qe (),
2905 .q (),
2906 .ds (),
2907
2908 // to register interface (read)
2909 .qs (debug_invalid_key_qs)
2910 );
2911
2912 // F[invalid_digest]: 6:6
2913 prim_subreg #(
2914 .DW (1),
2915 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2916 .RESVAL (1'h0),
2917 .Mubi (1'b0)
2918 ) u_debug_invalid_digest (
2919 .clk_i (clk_i),
2920 .rst_ni (rst_ni),
2921
2922 // from register interface
2923 .we (debug_we),
2924 .wd (debug_invalid_digest_wd),
2925
2926 // from internal hardware
2927 .de (hw2reg.debug.invalid_digest.de),
2928 .d (hw2reg.debug.invalid_digest.d),
2929
2930 // to internal hardware
2931 .qe (),
2932 .q (),
2933 .ds (),
2934
2935 // to register interface (read)
2936 .qs (debug_invalid_digest_qs)
2937 );
2938
2939
2940
2941 logic [62:0] addr_hit;
2942 always_comb begin
2943 1/1 addr_hit = '0;
Tests: T1 T2 T3
2944 1/1 addr_hit[ 0] = (reg_addr == KEYMGR_INTR_STATE_OFFSET);
Tests: T1 T2 T3
2945 1/1 addr_hit[ 1] = (reg_addr == KEYMGR_INTR_ENABLE_OFFSET);
Tests: T1 T2 T3
2946 1/1 addr_hit[ 2] = (reg_addr == KEYMGR_INTR_TEST_OFFSET);
Tests: T1 T2 T3
2947 1/1 addr_hit[ 3] = (reg_addr == KEYMGR_ALERT_TEST_OFFSET);
Tests: T1 T2 T3
2948 1/1 addr_hit[ 4] = (reg_addr == KEYMGR_CFG_REGWEN_OFFSET);
Tests: T1 T2 T3
2949 1/1 addr_hit[ 5] = (reg_addr == KEYMGR_START_OFFSET);
Tests: T1 T2 T3
2950 1/1 addr_hit[ 6] = (reg_addr == KEYMGR_CONTROL_SHADOWED_OFFSET);
Tests: T1 T2 T3
2951 1/1 addr_hit[ 7] = (reg_addr == KEYMGR_SIDELOAD_CLEAR_OFFSET);
Tests: T1 T2 T3
2952 1/1 addr_hit[ 8] = (reg_addr == KEYMGR_RESEED_INTERVAL_REGWEN_OFFSET);
Tests: T1 T2 T3
2953 1/1 addr_hit[ 9] = (reg_addr == KEYMGR_RESEED_INTERVAL_SHADOWED_OFFSET);
Tests: T1 T2 T3
2954 1/1 addr_hit[10] = (reg_addr == KEYMGR_SW_BINDING_REGWEN_OFFSET);
Tests: T1 T2 T3
2955 1/1 addr_hit[11] = (reg_addr == KEYMGR_SEALING_SW_BINDING_0_OFFSET);
Tests: T1 T2 T3
2956 1/1 addr_hit[12] = (reg_addr == KEYMGR_SEALING_SW_BINDING_1_OFFSET);
Tests: T1 T2 T3
2957 1/1 addr_hit[13] = (reg_addr == KEYMGR_SEALING_SW_BINDING_2_OFFSET);
Tests: T1 T2 T3
2958 1/1 addr_hit[14] = (reg_addr == KEYMGR_SEALING_SW_BINDING_3_OFFSET);
Tests: T1 T2 T3
2959 1/1 addr_hit[15] = (reg_addr == KEYMGR_SEALING_SW_BINDING_4_OFFSET);
Tests: T1 T2 T3
2960 1/1 addr_hit[16] = (reg_addr == KEYMGR_SEALING_SW_BINDING_5_OFFSET);
Tests: T1 T2 T3
2961 1/1 addr_hit[17] = (reg_addr == KEYMGR_SEALING_SW_BINDING_6_OFFSET);
Tests: T1 T2 T3
2962 1/1 addr_hit[18] = (reg_addr == KEYMGR_SEALING_SW_BINDING_7_OFFSET);
Tests: T1 T2 T3
2963 1/1 addr_hit[19] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_0_OFFSET);
Tests: T1 T2 T3
2964 1/1 addr_hit[20] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_1_OFFSET);
Tests: T1 T2 T3
2965 1/1 addr_hit[21] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_2_OFFSET);
Tests: T1 T2 T3
2966 1/1 addr_hit[22] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_3_OFFSET);
Tests: T1 T2 T3
2967 1/1 addr_hit[23] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_4_OFFSET);
Tests: T1 T2 T3
2968 1/1 addr_hit[24] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_5_OFFSET);
Tests: T1 T2 T3
2969 1/1 addr_hit[25] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_6_OFFSET);
Tests: T1 T2 T3
2970 1/1 addr_hit[26] = (reg_addr == KEYMGR_ATTEST_SW_BINDING_7_OFFSET);
Tests: T1 T2 T3
2971 1/1 addr_hit[27] = (reg_addr == KEYMGR_SALT_0_OFFSET);
Tests: T1 T2 T3
2972 1/1 addr_hit[28] = (reg_addr == KEYMGR_SALT_1_OFFSET);
Tests: T1 T2 T3
2973 1/1 addr_hit[29] = (reg_addr == KEYMGR_SALT_2_OFFSET);
Tests: T1 T2 T3
2974 1/1 addr_hit[30] = (reg_addr == KEYMGR_SALT_3_OFFSET);
Tests: T1 T2 T3
2975 1/1 addr_hit[31] = (reg_addr == KEYMGR_SALT_4_OFFSET);
Tests: T1 T2 T3
2976 1/1 addr_hit[32] = (reg_addr == KEYMGR_SALT_5_OFFSET);
Tests: T1 T2 T3
2977 1/1 addr_hit[33] = (reg_addr == KEYMGR_SALT_6_OFFSET);
Tests: T1 T2 T3
2978 1/1 addr_hit[34] = (reg_addr == KEYMGR_SALT_7_OFFSET);
Tests: T1 T2 T3
2979 1/1 addr_hit[35] = (reg_addr == KEYMGR_KEY_VERSION_OFFSET);
Tests: T1 T2 T3
2980 1/1 addr_hit[36] = (reg_addr == KEYMGR_MAX_CREATOR_KEY_VER_REGWEN_OFFSET);
Tests: T1 T2 T3
2981 1/1 addr_hit[37] = (reg_addr == KEYMGR_MAX_CREATOR_KEY_VER_SHADOWED_OFFSET);
Tests: T1 T2 T3
2982 1/1 addr_hit[38] = (reg_addr == KEYMGR_MAX_OWNER_INT_KEY_VER_REGWEN_OFFSET);
Tests: T1 T2 T3
2983 1/1 addr_hit[39] = (reg_addr == KEYMGR_MAX_OWNER_INT_KEY_VER_SHADOWED_OFFSET);
Tests: T1 T2 T3
2984 1/1 addr_hit[40] = (reg_addr == KEYMGR_MAX_OWNER_KEY_VER_REGWEN_OFFSET);
Tests: T1 T2 T3
2985 1/1 addr_hit[41] = (reg_addr == KEYMGR_MAX_OWNER_KEY_VER_SHADOWED_OFFSET);
Tests: T1 T2 T3
2986 1/1 addr_hit[42] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_0_OFFSET);
Tests: T1 T2 T3
2987 1/1 addr_hit[43] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_1_OFFSET);
Tests: T1 T2 T3
2988 1/1 addr_hit[44] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_2_OFFSET);
Tests: T1 T2 T3
2989 1/1 addr_hit[45] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_3_OFFSET);
Tests: T1 T2 T3
2990 1/1 addr_hit[46] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_4_OFFSET);
Tests: T1 T2 T3
2991 1/1 addr_hit[47] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_5_OFFSET);
Tests: T1 T2 T3
2992 1/1 addr_hit[48] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_6_OFFSET);
Tests: T1 T2 T3
2993 1/1 addr_hit[49] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_7_OFFSET);
Tests: T1 T2 T3
2994 1/1 addr_hit[50] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_0_OFFSET);
Tests: T1 T2 T3
2995 1/1 addr_hit[51] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_1_OFFSET);
Tests: T1 T2 T3
2996 1/1 addr_hit[52] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_2_OFFSET);
Tests: T1 T2 T3
2997 1/1 addr_hit[53] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_3_OFFSET);
Tests: T1 T2 T3
2998 1/1 addr_hit[54] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_4_OFFSET);
Tests: T1 T2 T3
2999 1/1 addr_hit[55] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_5_OFFSET);
Tests: T1 T2 T3
3000 1/1 addr_hit[56] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_6_OFFSET);
Tests: T1 T2 T3
3001 1/1 addr_hit[57] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_7_OFFSET);
Tests: T1 T2 T3
3002 1/1 addr_hit[58] = (reg_addr == KEYMGR_WORKING_STATE_OFFSET);
Tests: T1 T2 T3
3003 1/1 addr_hit[59] = (reg_addr == KEYMGR_OP_STATUS_OFFSET);
Tests: T1 T2 T3
3004 1/1 addr_hit[60] = (reg_addr == KEYMGR_ERR_CODE_OFFSET);
Tests: T1 T2 T3
3005 1/1 addr_hit[61] = (reg_addr == KEYMGR_FAULT_STATUS_OFFSET);
Tests: T1 T2 T3
3006 1/1 addr_hit[62] = (reg_addr == KEYMGR_DEBUG_OFFSET);
Tests: T1 T2 T3
3007 end
3008
3009 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T1 T2 T3
3010
3011 // Check sub-word write is permitted
3012 always_comb begin
3013 1/1 wr_err = (reg_we &
Tests: T1 T2 T3
3014 ((addr_hit[ 0] & (|(KEYMGR_PERMIT[ 0] & ~reg_be))) |
3015 (addr_hit[ 1] & (|(KEYMGR_PERMIT[ 1] & ~reg_be))) |
3016 (addr_hit[ 2] & (|(KEYMGR_PERMIT[ 2] & ~reg_be))) |
3017 (addr_hit[ 3] & (|(KEYMGR_PERMIT[ 3] & ~reg_be))) |
3018 (addr_hit[ 4] & (|(KEYMGR_PERMIT[ 4] & ~reg_be))) |
3019 (addr_hit[ 5] & (|(KEYMGR_PERMIT[ 5] & ~reg_be))) |
3020 (addr_hit[ 6] & (|(KEYMGR_PERMIT[ 6] & ~reg_be))) |
3021 (addr_hit[ 7] & (|(KEYMGR_PERMIT[ 7] & ~reg_be))) |
3022 (addr_hit[ 8] & (|(KEYMGR_PERMIT[ 8] & ~reg_be))) |
3023 (addr_hit[ 9] & (|(KEYMGR_PERMIT[ 9] & ~reg_be))) |
3024 (addr_hit[10] & (|(KEYMGR_PERMIT[10] & ~reg_be))) |
3025 (addr_hit[11] & (|(KEYMGR_PERMIT[11] & ~reg_be))) |
3026 (addr_hit[12] & (|(KEYMGR_PERMIT[12] & ~reg_be))) |
3027 (addr_hit[13] & (|(KEYMGR_PERMIT[13] & ~reg_be))) |
3028 (addr_hit[14] & (|(KEYMGR_PERMIT[14] & ~reg_be))) |
3029 (addr_hit[15] & (|(KEYMGR_PERMIT[15] & ~reg_be))) |
3030 (addr_hit[16] & (|(KEYMGR_PERMIT[16] & ~reg_be))) |
3031 (addr_hit[17] & (|(KEYMGR_PERMIT[17] & ~reg_be))) |
3032 (addr_hit[18] & (|(KEYMGR_PERMIT[18] & ~reg_be))) |
3033 (addr_hit[19] & (|(KEYMGR_PERMIT[19] & ~reg_be))) |
3034 (addr_hit[20] & (|(KEYMGR_PERMIT[20] & ~reg_be))) |
3035 (addr_hit[21] & (|(KEYMGR_PERMIT[21] & ~reg_be))) |
3036 (addr_hit[22] & (|(KEYMGR_PERMIT[22] & ~reg_be))) |
3037 (addr_hit[23] & (|(KEYMGR_PERMIT[23] & ~reg_be))) |
3038 (addr_hit[24] & (|(KEYMGR_PERMIT[24] & ~reg_be))) |
3039 (addr_hit[25] & (|(KEYMGR_PERMIT[25] & ~reg_be))) |
3040 (addr_hit[26] & (|(KEYMGR_PERMIT[26] & ~reg_be))) |
3041 (addr_hit[27] & (|(KEYMGR_PERMIT[27] & ~reg_be))) |
3042 (addr_hit[28] & (|(KEYMGR_PERMIT[28] & ~reg_be))) |
3043 (addr_hit[29] & (|(KEYMGR_PERMIT[29] & ~reg_be))) |
3044 (addr_hit[30] & (|(KEYMGR_PERMIT[30] & ~reg_be))) |
3045 (addr_hit[31] & (|(KEYMGR_PERMIT[31] & ~reg_be))) |
3046 (addr_hit[32] & (|(KEYMGR_PERMIT[32] & ~reg_be))) |
3047 (addr_hit[33] & (|(KEYMGR_PERMIT[33] & ~reg_be))) |
3048 (addr_hit[34] & (|(KEYMGR_PERMIT[34] & ~reg_be))) |
3049 (addr_hit[35] & (|(KEYMGR_PERMIT[35] & ~reg_be))) |
3050 (addr_hit[36] & (|(KEYMGR_PERMIT[36] & ~reg_be))) |
3051 (addr_hit[37] & (|(KEYMGR_PERMIT[37] & ~reg_be))) |
3052 (addr_hit[38] & (|(KEYMGR_PERMIT[38] & ~reg_be))) |
3053 (addr_hit[39] & (|(KEYMGR_PERMIT[39] & ~reg_be))) |
3054 (addr_hit[40] & (|(KEYMGR_PERMIT[40] & ~reg_be))) |
3055 (addr_hit[41] & (|(KEYMGR_PERMIT[41] & ~reg_be))) |
3056 (addr_hit[42] & (|(KEYMGR_PERMIT[42] & ~reg_be))) |
3057 (addr_hit[43] & (|(KEYMGR_PERMIT[43] & ~reg_be))) |
3058 (addr_hit[44] & (|(KEYMGR_PERMIT[44] & ~reg_be))) |
3059 (addr_hit[45] & (|(KEYMGR_PERMIT[45] & ~reg_be))) |
3060 (addr_hit[46] & (|(KEYMGR_PERMIT[46] & ~reg_be))) |
3061 (addr_hit[47] & (|(KEYMGR_PERMIT[47] & ~reg_be))) |
3062 (addr_hit[48] & (|(KEYMGR_PERMIT[48] & ~reg_be))) |
3063 (addr_hit[49] & (|(KEYMGR_PERMIT[49] & ~reg_be))) |
3064 (addr_hit[50] & (|(KEYMGR_PERMIT[50] & ~reg_be))) |
3065 (addr_hit[51] & (|(KEYMGR_PERMIT[51] & ~reg_be))) |
3066 (addr_hit[52] & (|(KEYMGR_PERMIT[52] & ~reg_be))) |
3067 (addr_hit[53] & (|(KEYMGR_PERMIT[53] & ~reg_be))) |
3068 (addr_hit[54] & (|(KEYMGR_PERMIT[54] & ~reg_be))) |
3069 (addr_hit[55] & (|(KEYMGR_PERMIT[55] & ~reg_be))) |
3070 (addr_hit[56] & (|(KEYMGR_PERMIT[56] & ~reg_be))) |
3071 (addr_hit[57] & (|(KEYMGR_PERMIT[57] & ~reg_be))) |
3072 (addr_hit[58] & (|(KEYMGR_PERMIT[58] & ~reg_be))) |
3073 (addr_hit[59] & (|(KEYMGR_PERMIT[59] & ~reg_be))) |
3074 (addr_hit[60] & (|(KEYMGR_PERMIT[60] & ~reg_be))) |
3075 (addr_hit[61] & (|(KEYMGR_PERMIT[61] & ~reg_be))) |
3076 (addr_hit[62] & (|(KEYMGR_PERMIT[62] & ~reg_be)))));
3077 end
3078
3079 // Generate write-enables
3080 1/1 assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
Tests: T1 T2 T3
3081
3082 1/1 assign intr_state_wd = reg_wdata[0];
Tests: T1 T2 T3
3083 1/1 assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
Tests: T1 T2 T3
3084
3085 1/1 assign intr_enable_wd = reg_wdata[0];
Tests: T1 T2 T3
3086 1/1 assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
Tests: T1 T2 T3
3087
3088 1/1 assign intr_test_wd = reg_wdata[0];
Tests: T1 T2 T3
3089 1/1 assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
Tests: T1 T2 T3
3090
3091 1/1 assign alert_test_recov_operation_err_wd = reg_wdata[0];
Tests: T1 T2 T3
3092
3093 1/1 assign alert_test_fatal_fault_err_wd = reg_wdata[1];
Tests: T1 T2 T3
3094 1/1 assign cfg_regwen_re = addr_hit[4] & reg_re & !reg_error;
Tests: T1 T2 T3
3095 1/1 assign start_we = addr_hit[5] & reg_we & !reg_error;
Tests: T1 T2 T3
3096
3097 1/1 assign start_wd = reg_wdata[0];
Tests: T1 T2 T3
3098 1/1 assign control_shadowed_re = addr_hit[6] & reg_re & !reg_error;
Tests: T1 T2 T3
3099 1/1 assign control_shadowed_we = addr_hit[6] & reg_we & !reg_error;
Tests: T1 T2 T3
3100
3101 1/1 assign control_shadowed_operation_wd = reg_wdata[6:4];
Tests: T1 T2 T3
3102
3103 1/1 assign control_shadowed_cdi_sel_wd = reg_wdata[7];
Tests: T1 T2 T3
3104
3105 1/1 assign control_shadowed_dest_sel_wd = reg_wdata[13:12];
Tests: T1 T2 T3
3106 1/1 assign sideload_clear_we = addr_hit[7] & reg_we & !reg_error;
Tests: T1 T2 T3
3107
3108 1/1 assign sideload_clear_wd = reg_wdata[2:0];
Tests: T1 T2 T3
3109 1/1 assign reseed_interval_regwen_we = addr_hit[8] & reg_we & !reg_error;
Tests: T1 T2 T3
3110
3111 1/1 assign reseed_interval_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
3112 1/1 assign reseed_interval_shadowed_re = addr_hit[9] & reg_re & !reg_error;
Tests: T1 T2 T3
3113 1/1 assign reseed_interval_shadowed_we = addr_hit[9] & reg_we & !reg_error;
Tests: T1 T2 T3
3114
3115 1/1 assign reseed_interval_shadowed_wd = reg_wdata[15:0];
Tests: T1 T2 T3
3116 1/1 assign sw_binding_regwen_re = addr_hit[10] & reg_re & !reg_error;
Tests: T1 T2 T3
3117 1/1 assign sw_binding_regwen_we = addr_hit[10] & reg_we & !reg_error;
Tests: T1 T2 T3
3118
3119 1/1 assign sw_binding_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
3120 1/1 assign sealing_sw_binding_0_we = addr_hit[11] & reg_we & !reg_error;
Tests: T1 T2 T3
3121
3122 1/1 assign sealing_sw_binding_0_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3123 1/1 assign sealing_sw_binding_1_we = addr_hit[12] & reg_we & !reg_error;
Tests: T1 T2 T3
3124
3125 1/1 assign sealing_sw_binding_1_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3126 1/1 assign sealing_sw_binding_2_we = addr_hit[13] & reg_we & !reg_error;
Tests: T1 T2 T3
3127
3128 1/1 assign sealing_sw_binding_2_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3129 1/1 assign sealing_sw_binding_3_we = addr_hit[14] & reg_we & !reg_error;
Tests: T1 T2 T3
3130
3131 1/1 assign sealing_sw_binding_3_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3132 1/1 assign sealing_sw_binding_4_we = addr_hit[15] & reg_we & !reg_error;
Tests: T1 T2 T3
3133
3134 1/1 assign sealing_sw_binding_4_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3135 1/1 assign sealing_sw_binding_5_we = addr_hit[16] & reg_we & !reg_error;
Tests: T1 T2 T3
3136
3137 1/1 assign sealing_sw_binding_5_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3138 1/1 assign sealing_sw_binding_6_we = addr_hit[17] & reg_we & !reg_error;
Tests: T1 T2 T3
3139
3140 1/1 assign sealing_sw_binding_6_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3141 1/1 assign sealing_sw_binding_7_we = addr_hit[18] & reg_we & !reg_error;
Tests: T1 T2 T3
3142
3143 1/1 assign sealing_sw_binding_7_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3144 1/1 assign attest_sw_binding_0_we = addr_hit[19] & reg_we & !reg_error;
Tests: T1 T2 T3
3145
3146 1/1 assign attest_sw_binding_0_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3147 1/1 assign attest_sw_binding_1_we = addr_hit[20] & reg_we & !reg_error;
Tests: T1 T2 T3
3148
3149 1/1 assign attest_sw_binding_1_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3150 1/1 assign attest_sw_binding_2_we = addr_hit[21] & reg_we & !reg_error;
Tests: T1 T2 T3
3151
3152 1/1 assign attest_sw_binding_2_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3153 1/1 assign attest_sw_binding_3_we = addr_hit[22] & reg_we & !reg_error;
Tests: T1 T2 T3
3154
3155 1/1 assign attest_sw_binding_3_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3156 1/1 assign attest_sw_binding_4_we = addr_hit[23] & reg_we & !reg_error;
Tests: T1 T2 T3
3157
3158 1/1 assign attest_sw_binding_4_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3159 1/1 assign attest_sw_binding_5_we = addr_hit[24] & reg_we & !reg_error;
Tests: T1 T2 T3
3160
3161 1/1 assign attest_sw_binding_5_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3162 1/1 assign attest_sw_binding_6_we = addr_hit[25] & reg_we & !reg_error;
Tests: T1 T2 T3
3163
3164 1/1 assign attest_sw_binding_6_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3165 1/1 assign attest_sw_binding_7_we = addr_hit[26] & reg_we & !reg_error;
Tests: T1 T2 T3
3166
3167 1/1 assign attest_sw_binding_7_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3168 1/1 assign salt_0_we = addr_hit[27] & reg_we & !reg_error;
Tests: T1 T2 T3
3169
3170 1/1 assign salt_0_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3171 1/1 assign salt_1_we = addr_hit[28] & reg_we & !reg_error;
Tests: T1 T2 T3
3172
3173 1/1 assign salt_1_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3174 1/1 assign salt_2_we = addr_hit[29] & reg_we & !reg_error;
Tests: T1 T2 T3
3175
3176 1/1 assign salt_2_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3177 1/1 assign salt_3_we = addr_hit[30] & reg_we & !reg_error;
Tests: T1 T2 T3
3178
3179 1/1 assign salt_3_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3180 1/1 assign salt_4_we = addr_hit[31] & reg_we & !reg_error;
Tests: T1 T2 T3
3181
3182 1/1 assign salt_4_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3183 1/1 assign salt_5_we = addr_hit[32] & reg_we & !reg_error;
Tests: T1 T2 T3
3184
3185 1/1 assign salt_5_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3186 1/1 assign salt_6_we = addr_hit[33] & reg_we & !reg_error;
Tests: T1 T2 T3
3187
3188 1/1 assign salt_6_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3189 1/1 assign salt_7_we = addr_hit[34] & reg_we & !reg_error;
Tests: T1 T2 T3
3190
3191 1/1 assign salt_7_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3192 1/1 assign key_version_we = addr_hit[35] & reg_we & !reg_error;
Tests: T1 T2 T3
3193
3194 1/1 assign key_version_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3195 1/1 assign max_creator_key_ver_regwen_we = addr_hit[36] & reg_we & !reg_error;
Tests: T1 T2 T3
3196
3197 1/1 assign max_creator_key_ver_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
3198 1/1 assign max_creator_key_ver_shadowed_re = addr_hit[37] & reg_re & !reg_error;
Tests: T1 T2 T3
3199 1/1 assign max_creator_key_ver_shadowed_we = addr_hit[37] & reg_we & !reg_error;
Tests: T1 T2 T3
3200
3201 1/1 assign max_creator_key_ver_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3202 1/1 assign max_owner_int_key_ver_regwen_we = addr_hit[38] & reg_we & !reg_error;
Tests: T1 T2 T3
3203
3204 1/1 assign max_owner_int_key_ver_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
3205 1/1 assign max_owner_int_key_ver_shadowed_re = addr_hit[39] & reg_re & !reg_error;
Tests: T1 T2 T3
3206 1/1 assign max_owner_int_key_ver_shadowed_we = addr_hit[39] & reg_we & !reg_error;
Tests: T1 T2 T3
3207
3208 1/1 assign max_owner_int_key_ver_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3209 1/1 assign max_owner_key_ver_regwen_we = addr_hit[40] & reg_we & !reg_error;
Tests: T1 T2 T3
3210
3211 1/1 assign max_owner_key_ver_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
3212 1/1 assign max_owner_key_ver_shadowed_re = addr_hit[41] & reg_re & !reg_error;
Tests: T1 T2 T3
3213 1/1 assign max_owner_key_ver_shadowed_we = addr_hit[41] & reg_we & !reg_error;
Tests: T1 T2 T3
3214
3215 1/1 assign max_owner_key_ver_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
3216 1/1 assign sw_share0_output_0_re = addr_hit[42] & reg_re & !reg_error;
Tests: T1 T2 T3
3217
3218 assign sw_share0_output_0_wd = '1;
3219 1/1 assign sw_share0_output_1_re = addr_hit[43] & reg_re & !reg_error;
Tests: T1 T2 T3
3220
3221 assign sw_share0_output_1_wd = '1;
3222 1/1 assign sw_share0_output_2_re = addr_hit[44] & reg_re & !reg_error;
Tests: T1 T2 T3
3223
3224 assign sw_share0_output_2_wd = '1;
3225 1/1 assign sw_share0_output_3_re = addr_hit[45] & reg_re & !reg_error;
Tests: T1 T2 T3
3226
3227 assign sw_share0_output_3_wd = '1;
3228 1/1 assign sw_share0_output_4_re = addr_hit[46] & reg_re & !reg_error;
Tests: T1 T2 T3
3229
3230 assign sw_share0_output_4_wd = '1;
3231 1/1 assign sw_share0_output_5_re = addr_hit[47] & reg_re & !reg_error;
Tests: T1 T2 T3
3232
3233 assign sw_share0_output_5_wd = '1;
3234 1/1 assign sw_share0_output_6_re = addr_hit[48] & reg_re & !reg_error;
Tests: T1 T2 T3
3235
3236 assign sw_share0_output_6_wd = '1;
3237 1/1 assign sw_share0_output_7_re = addr_hit[49] & reg_re & !reg_error;
Tests: T1 T2 T3
3238
3239 assign sw_share0_output_7_wd = '1;
3240 1/1 assign sw_share1_output_0_re = addr_hit[50] & reg_re & !reg_error;
Tests: T1 T2 T3
3241
3242 assign sw_share1_output_0_wd = '1;
3243 1/1 assign sw_share1_output_1_re = addr_hit[51] & reg_re & !reg_error;
Tests: T1 T2 T3
3244
3245 assign sw_share1_output_1_wd = '1;
3246 1/1 assign sw_share1_output_2_re = addr_hit[52] & reg_re & !reg_error;
Tests: T1 T2 T3
3247
3248 assign sw_share1_output_2_wd = '1;
3249 1/1 assign sw_share1_output_3_re = addr_hit[53] & reg_re & !reg_error;
Tests: T1 T2 T3
3250
3251 assign sw_share1_output_3_wd = '1;
3252 1/1 assign sw_share1_output_4_re = addr_hit[54] & reg_re & !reg_error;
Tests: T1 T2 T3
3253
3254 assign sw_share1_output_4_wd = '1;
3255 1/1 assign sw_share1_output_5_re = addr_hit[55] & reg_re & !reg_error;
Tests: T1 T2 T3
3256
3257 assign sw_share1_output_5_wd = '1;
3258 1/1 assign sw_share1_output_6_re = addr_hit[56] & reg_re & !reg_error;
Tests: T1 T2 T3
3259
3260 assign sw_share1_output_6_wd = '1;
3261 1/1 assign sw_share1_output_7_re = addr_hit[57] & reg_re & !reg_error;
Tests: T1 T2 T3
3262
3263 assign sw_share1_output_7_wd = '1;
3264 1/1 assign op_status_we = addr_hit[59] & reg_we & !reg_error;
Tests: T1 T2 T3
3265
3266 1/1 assign op_status_wd = reg_wdata[1:0];
Tests: T1 T2 T3
3267 1/1 assign err_code_we = addr_hit[60] & reg_we & !reg_error;
Tests: T1 T2 T3
3268
3269 1/1 assign err_code_invalid_op_wd = reg_wdata[0];
Tests: T1 T2 T3
3270
3271 1/1 assign err_code_invalid_kmac_input_wd = reg_wdata[1];
Tests: T1 T2 T3
3272
3273 1/1 assign err_code_invalid_shadow_update_wd = reg_wdata[2];
Tests: T1 T2 T3
3274 1/1 assign debug_we = addr_hit[62] & reg_we & !reg_error;
Tests: T1 T2 T3
3275
3276 1/1 assign debug_invalid_creator_seed_wd = reg_wdata[0];
Tests: T1 T2 T3
3277
3278 1/1 assign debug_invalid_owner_seed_wd = reg_wdata[1];
Tests: T1 T2 T3
3279
3280 1/1 assign debug_invalid_dev_id_wd = reg_wdata[2];
Tests: T1 T2 T3
3281
3282 1/1 assign debug_invalid_health_state_wd = reg_wdata[3];
Tests: T1 T2 T3
3283
3284 1/1 assign debug_invalid_key_version_wd = reg_wdata[4];
Tests: T1 T2 T3
3285
3286 1/1 assign debug_invalid_key_wd = reg_wdata[5];
Tests: T1 T2 T3
3287
3288 1/1 assign debug_invalid_digest_wd = reg_wdata[6];
Tests: T1 T2 T3
3289
3290 // Assign write-enables to checker logic vector.
3291 always_comb begin
3292 1/1 reg_we_check = '0;
Tests: T1 T2 T3
3293 1/1 reg_we_check[0] = intr_state_we;
Tests: T1 T2 T3
3294 1/1 reg_we_check[1] = intr_enable_we;
Tests: T1 T2 T3
3295 1/1 reg_we_check[2] = intr_test_we;
Tests: T1 T2 T3
3296 1/1 reg_we_check[3] = alert_test_we;
Tests: T1 T2 T3
3297 1/1 reg_we_check[4] = 1'b0;
Tests: T1 T2 T3
3298 1/1 reg_we_check[5] = start_gated_we;
Tests: T1 T2 T3
3299 1/1 reg_we_check[6] = control_shadowed_gated_we;
Tests: T1 T2 T3
3300 1/1 reg_we_check[7] = sideload_clear_gated_we;
Tests: T1 T2 T3
3301 1/1 reg_we_check[8] = reseed_interval_regwen_we;
Tests: T1 T2 T3
3302 1/1 reg_we_check[9] = reseed_interval_shadowed_gated_we;
Tests: T1 T2 T3
3303 1/1 reg_we_check[10] = sw_binding_regwen_we;
Tests: T1 T2 T3
3304 1/1 reg_we_check[11] = sealing_sw_binding_0_gated_we;
Tests: T1 T2 T3
3305 1/1 reg_we_check[12] = sealing_sw_binding_1_gated_we;
Tests: T1 T2 T3
3306 1/1 reg_we_check[13] = sealing_sw_binding_2_gated_we;
Tests: T1 T2 T3
3307 1/1 reg_we_check[14] = sealing_sw_binding_3_gated_we;
Tests: T1 T2 T3
3308 1/1 reg_we_check[15] = sealing_sw_binding_4_gated_we;
Tests: T1 T2 T3
3309 1/1 reg_we_check[16] = sealing_sw_binding_5_gated_we;
Tests: T1 T2 T3
3310 1/1 reg_we_check[17] = sealing_sw_binding_6_gated_we;
Tests: T1 T2 T3
3311 1/1 reg_we_check[18] = sealing_sw_binding_7_gated_we;
Tests: T1 T2 T3
3312 1/1 reg_we_check[19] = attest_sw_binding_0_gated_we;
Tests: T1 T2 T3
3313 1/1 reg_we_check[20] = attest_sw_binding_1_gated_we;
Tests: T1 T2 T3
3314 1/1 reg_we_check[21] = attest_sw_binding_2_gated_we;
Tests: T1 T2 T3
3315 1/1 reg_we_check[22] = attest_sw_binding_3_gated_we;
Tests: T1 T2 T3
3316 1/1 reg_we_check[23] = attest_sw_binding_4_gated_we;
Tests: T1 T2 T3
3317 1/1 reg_we_check[24] = attest_sw_binding_5_gated_we;
Tests: T1 T2 T3
3318 1/1 reg_we_check[25] = attest_sw_binding_6_gated_we;
Tests: T1 T2 T3
3319 1/1 reg_we_check[26] = attest_sw_binding_7_gated_we;
Tests: T1 T2 T3
3320 1/1 reg_we_check[27] = salt_0_gated_we;
Tests: T1 T2 T3
3321 1/1 reg_we_check[28] = salt_1_gated_we;
Tests: T1 T2 T3
3322 1/1 reg_we_check[29] = salt_2_gated_we;
Tests: T1 T2 T3
3323 1/1 reg_we_check[30] = salt_3_gated_we;
Tests: T1 T2 T3
3324 1/1 reg_we_check[31] = salt_4_gated_we;
Tests: T1 T2 T3
3325 1/1 reg_we_check[32] = salt_5_gated_we;
Tests: T1 T2 T3
3326 1/1 reg_we_check[33] = salt_6_gated_we;
Tests: T1 T2 T3
3327 1/1 reg_we_check[34] = salt_7_gated_we;
Tests: T1 T2 T3
3328 1/1 reg_we_check[35] = key_version_gated_we;
Tests: T1 T2 T3
3329 1/1 reg_we_check[36] = max_creator_key_ver_regwen_we;
Tests: T1 T2 T3
3330 1/1 reg_we_check[37] = max_creator_key_ver_shadowed_gated_we;
Tests: T1 T2 T3
3331 1/1 reg_we_check[38] = max_owner_int_key_ver_regwen_we;
Tests: T1 T2 T3
3332 1/1 reg_we_check[39] = max_owner_int_key_ver_shadowed_gated_we;
Tests: T1 T2 T3
3333 1/1 reg_we_check[40] = max_owner_key_ver_regwen_we;
Tests: T1 T2 T3
3334 1/1 reg_we_check[41] = max_owner_key_ver_shadowed_gated_we;
Tests: T1 T2 T3
3335 1/1 reg_we_check[42] = 1'b0;
Tests: T1 T2 T3
3336 1/1 reg_we_check[43] = 1'b0;
Tests: T1 T2 T3
3337 1/1 reg_we_check[44] = 1'b0;
Tests: T1 T2 T3
3338 1/1 reg_we_check[45] = 1'b0;
Tests: T1 T2 T3
3339 1/1 reg_we_check[46] = 1'b0;
Tests: T1 T2 T3
3340 1/1 reg_we_check[47] = 1'b0;
Tests: T1 T2 T3
3341 1/1 reg_we_check[48] = 1'b0;
Tests: T1 T2 T3
3342 1/1 reg_we_check[49] = 1'b0;
Tests: T1 T2 T3
3343 1/1 reg_we_check[50] = 1'b0;
Tests: T1 T2 T3
3344 1/1 reg_we_check[51] = 1'b0;
Tests: T1 T2 T3
3345 1/1 reg_we_check[52] = 1'b0;
Tests: T1 T2 T3
3346 1/1 reg_we_check[53] = 1'b0;
Tests: T1 T2 T3
3347 1/1 reg_we_check[54] = 1'b0;
Tests: T1 T2 T3
3348 1/1 reg_we_check[55] = 1'b0;
Tests: T1 T2 T3
3349 1/1 reg_we_check[56] = 1'b0;
Tests: T1 T2 T3
3350 1/1 reg_we_check[57] = 1'b0;
Tests: T1 T2 T3
3351 1/1 reg_we_check[58] = 1'b0;
Tests: T1 T2 T3
3352 1/1 reg_we_check[59] = op_status_we;
Tests: T1 T2 T3
3353 1/1 reg_we_check[60] = err_code_we;
Tests: T1 T2 T3
3354 1/1 reg_we_check[61] = 1'b0;
Tests: T1 T2 T3
3355 1/1 reg_we_check[62] = debug_we;
Tests: T1 T2 T3
3356 end
3357
3358 // Read data return
3359 always_comb begin
3360 1/1 reg_rdata_next = '0;
Tests: T1 T2 T3
3361 1/1 unique case (1'b1)
Tests: T1 T2 T3
3362 addr_hit[0]: begin
3363 1/1 reg_rdata_next[0] = intr_state_qs;
Tests: T1 T2 T3
3364 end
3365
3366 addr_hit[1]: begin
3367 1/1 reg_rdata_next[0] = intr_enable_qs;
Tests: T1 T2 T3
3368 end
3369
3370 addr_hit[2]: begin
3371 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
3372 end
3373
3374 addr_hit[3]: begin
3375 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
3376 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T3
3377 end
3378
3379 addr_hit[4]: begin
3380 1/1 reg_rdata_next[0] = cfg_regwen_qs;
Tests: T1 T2 T3
3381 end
3382
3383 addr_hit[5]: begin
3384 1/1 reg_rdata_next[0] = start_qs;
Tests: T1 T2 T3
3385 end
3386
3387 addr_hit[6]: begin
3388 1/1 reg_rdata_next[6:4] = control_shadowed_operation_qs;
Tests: T1 T2 T3
3389 1/1 reg_rdata_next[7] = control_shadowed_cdi_sel_qs;
Tests: T1 T2 T3
3390 1/1 reg_rdata_next[13:12] = control_shadowed_dest_sel_qs;
Tests: T1 T2 T3
3391 end
3392
3393 addr_hit[7]: begin
3394 1/1 reg_rdata_next[2:0] = sideload_clear_qs;
Tests: T1 T2 T3
3395 end
3396
3397 addr_hit[8]: begin
3398 1/1 reg_rdata_next[0] = reseed_interval_regwen_qs;
Tests: T1 T2 T3
3399 end
3400
3401 addr_hit[9]: begin
3402 1/1 reg_rdata_next[15:0] = reseed_interval_shadowed_qs;
Tests: T1 T2 T3
3403 end
3404
3405 addr_hit[10]: begin
3406 1/1 reg_rdata_next[0] = sw_binding_regwen_qs;
Tests: T1 T2 T3
3407 end
3408
3409 addr_hit[11]: begin
3410 1/1 reg_rdata_next[31:0] = sealing_sw_binding_0_qs;
Tests: T1 T2 T3
3411 end
3412
3413 addr_hit[12]: begin
3414 1/1 reg_rdata_next[31:0] = sealing_sw_binding_1_qs;
Tests: T1 T2 T3
3415 end
3416
3417 addr_hit[13]: begin
3418 1/1 reg_rdata_next[31:0] = sealing_sw_binding_2_qs;
Tests: T1 T2 T3
3419 end
3420
3421 addr_hit[14]: begin
3422 1/1 reg_rdata_next[31:0] = sealing_sw_binding_3_qs;
Tests: T1 T2 T3
3423 end
3424
3425 addr_hit[15]: begin
3426 1/1 reg_rdata_next[31:0] = sealing_sw_binding_4_qs;
Tests: T1 T2 T3
3427 end
3428
3429 addr_hit[16]: begin
3430 1/1 reg_rdata_next[31:0] = sealing_sw_binding_5_qs;
Tests: T1 T2 T3
3431 end
3432
3433 addr_hit[17]: begin
3434 1/1 reg_rdata_next[31:0] = sealing_sw_binding_6_qs;
Tests: T1 T2 T3
3435 end
3436
3437 addr_hit[18]: begin
3438 1/1 reg_rdata_next[31:0] = sealing_sw_binding_7_qs;
Tests: T1 T2 T3
3439 end
3440
3441 addr_hit[19]: begin
3442 1/1 reg_rdata_next[31:0] = attest_sw_binding_0_qs;
Tests: T1 T2 T3
3443 end
3444
3445 addr_hit[20]: begin
3446 1/1 reg_rdata_next[31:0] = attest_sw_binding_1_qs;
Tests: T1 T2 T3
3447 end
3448
3449 addr_hit[21]: begin
3450 1/1 reg_rdata_next[31:0] = attest_sw_binding_2_qs;
Tests: T1 T2 T3
3451 end
3452
3453 addr_hit[22]: begin
3454 1/1 reg_rdata_next[31:0] = attest_sw_binding_3_qs;
Tests: T1 T2 T3
3455 end
3456
3457 addr_hit[23]: begin
3458 1/1 reg_rdata_next[31:0] = attest_sw_binding_4_qs;
Tests: T1 T2 T3
3459 end
3460
3461 addr_hit[24]: begin
3462 1/1 reg_rdata_next[31:0] = attest_sw_binding_5_qs;
Tests: T1 T2 T3
3463 end
3464
3465 addr_hit[25]: begin
3466 1/1 reg_rdata_next[31:0] = attest_sw_binding_6_qs;
Tests: T1 T2 T3
3467 end
3468
3469 addr_hit[26]: begin
3470 1/1 reg_rdata_next[31:0] = attest_sw_binding_7_qs;
Tests: T1 T2 T3
3471 end
3472
3473 addr_hit[27]: begin
3474 1/1 reg_rdata_next[31:0] = salt_0_qs;
Tests: T1 T2 T3
3475 end
3476
3477 addr_hit[28]: begin
3478 1/1 reg_rdata_next[31:0] = salt_1_qs;
Tests: T1 T2 T3
3479 end
3480
3481 addr_hit[29]: begin
3482 1/1 reg_rdata_next[31:0] = salt_2_qs;
Tests: T1 T2 T3
3483 end
3484
3485 addr_hit[30]: begin
3486 1/1 reg_rdata_next[31:0] = salt_3_qs;
Tests: T1 T2 T3
3487 end
3488
3489 addr_hit[31]: begin
3490 1/1 reg_rdata_next[31:0] = salt_4_qs;
Tests: T1 T2 T3
3491 end
3492
3493 addr_hit[32]: begin
3494 1/1 reg_rdata_next[31:0] = salt_5_qs;
Tests: T1 T2 T3
3495 end
3496
3497 addr_hit[33]: begin
3498 1/1 reg_rdata_next[31:0] = salt_6_qs;
Tests: T1 T2 T3
3499 end
3500
3501 addr_hit[34]: begin
3502 1/1 reg_rdata_next[31:0] = salt_7_qs;
Tests: T1 T2 T3
3503 end
3504
3505 addr_hit[35]: begin
3506 1/1 reg_rdata_next[31:0] = key_version_qs;
Tests: T1 T2 T3
3507 end
3508
3509 addr_hit[36]: begin
3510 1/1 reg_rdata_next[0] = max_creator_key_ver_regwen_qs;
Tests: T1 T2 T3
3511 end
3512
3513 addr_hit[37]: begin
3514 1/1 reg_rdata_next[31:0] = max_creator_key_ver_shadowed_qs;
Tests: T1 T2 T3
3515 end
3516
3517 addr_hit[38]: begin
3518 1/1 reg_rdata_next[0] = max_owner_int_key_ver_regwen_qs;
Tests: T1 T2 T3
3519 end
3520
3521 addr_hit[39]: begin
3522 1/1 reg_rdata_next[31:0] = max_owner_int_key_ver_shadowed_qs;
Tests: T1 T2 T3
3523 end
3524
3525 addr_hit[40]: begin
3526 1/1 reg_rdata_next[0] = max_owner_key_ver_regwen_qs;
Tests: T1 T2 T3
3527 end
3528
3529 addr_hit[41]: begin
3530 1/1 reg_rdata_next[31:0] = max_owner_key_ver_shadowed_qs;
Tests: T1 T2 T3
3531 end
3532
3533 addr_hit[42]: begin
3534 1/1 reg_rdata_next[31:0] = sw_share0_output_0_qs;
Tests: T1 T2 T3
3535 end
3536
3537 addr_hit[43]: begin
3538 1/1 reg_rdata_next[31:0] = sw_share0_output_1_qs;
Tests: T1 T2 T3
3539 end
3540
3541 addr_hit[44]: begin
3542 1/1 reg_rdata_next[31:0] = sw_share0_output_2_qs;
Tests: T1 T2 T3
3543 end
3544
3545 addr_hit[45]: begin
3546 1/1 reg_rdata_next[31:0] = sw_share0_output_3_qs;
Tests: T1 T2 T3
3547 end
3548
3549 addr_hit[46]: begin
3550 1/1 reg_rdata_next[31:0] = sw_share0_output_4_qs;
Tests: T1 T2 T3
3551 end
3552
3553 addr_hit[47]: begin
3554 1/1 reg_rdata_next[31:0] = sw_share0_output_5_qs;
Tests: T1 T2 T3
3555 end
3556
3557 addr_hit[48]: begin
3558 1/1 reg_rdata_next[31:0] = sw_share0_output_6_qs;
Tests: T1 T2 T3
3559 end
3560
3561 addr_hit[49]: begin
3562 1/1 reg_rdata_next[31:0] = sw_share0_output_7_qs;
Tests: T1 T2 T3
3563 end
3564
3565 addr_hit[50]: begin
3566 1/1 reg_rdata_next[31:0] = sw_share1_output_0_qs;
Tests: T1 T2 T3
3567 end
3568
3569 addr_hit[51]: begin
3570 1/1 reg_rdata_next[31:0] = sw_share1_output_1_qs;
Tests: T1 T2 T3
3571 end
3572
3573 addr_hit[52]: begin
3574 1/1 reg_rdata_next[31:0] = sw_share1_output_2_qs;
Tests: T1 T2 T3
3575 end
3576
3577 addr_hit[53]: begin
3578 1/1 reg_rdata_next[31:0] = sw_share1_output_3_qs;
Tests: T1 T2 T3
3579 end
3580
3581 addr_hit[54]: begin
3582 1/1 reg_rdata_next[31:0] = sw_share1_output_4_qs;
Tests: T1 T2 T3
3583 end
3584
3585 addr_hit[55]: begin
3586 1/1 reg_rdata_next[31:0] = sw_share1_output_5_qs;
Tests: T1 T2 T3
3587 end
3588
3589 addr_hit[56]: begin
3590 1/1 reg_rdata_next[31:0] = sw_share1_output_6_qs;
Tests: T1 T2 T3
3591 end
3592
3593 addr_hit[57]: begin
3594 1/1 reg_rdata_next[31:0] = sw_share1_output_7_qs;
Tests: T1 T2 T3
3595 end
3596
3597 addr_hit[58]: begin
3598 1/1 reg_rdata_next[2:0] = working_state_qs;
Tests: T1 T2 T3
3599 end
3600
3601 addr_hit[59]: begin
3602 1/1 reg_rdata_next[1:0] = op_status_qs;
Tests: T1 T2 T3
3603 end
3604
3605 addr_hit[60]: begin
3606 1/1 reg_rdata_next[0] = err_code_invalid_op_qs;
Tests: T1 T2 T3
3607 1/1 reg_rdata_next[1] = err_code_invalid_kmac_input_qs;
Tests: T1 T2 T3
3608 1/1 reg_rdata_next[2] = err_code_invalid_shadow_update_qs;
Tests: T1 T2 T3
3609 end
3610
3611 addr_hit[61]: begin
3612 1/1 reg_rdata_next[0] = fault_status_cmd_qs;
Tests: T1 T2 T3
3613 1/1 reg_rdata_next[1] = fault_status_kmac_fsm_qs;
Tests: T1 T2 T3
3614 1/1 reg_rdata_next[2] = fault_status_kmac_done_qs;
Tests: T1 T2 T3
3615 1/1 reg_rdata_next[3] = fault_status_kmac_op_qs;
Tests: T1 T2 T3
3616 1/1 reg_rdata_next[4] = fault_status_kmac_out_qs;
Tests: T1 T2 T3
3617 1/1 reg_rdata_next[5] = fault_status_regfile_intg_qs;
Tests: T1 T2 T3
3618 1/1 reg_rdata_next[6] = fault_status_shadow_qs;
Tests: T1 T2 T3
3619 1/1 reg_rdata_next[7] = fault_status_ctrl_fsm_intg_qs;
Tests: T1 T2 T3
3620 1/1 reg_rdata_next[8] = fault_status_ctrl_fsm_chk_qs;
Tests: T1 T2 T3
3621 1/1 reg_rdata_next[9] = fault_status_ctrl_fsm_cnt_qs;
Tests: T1 T2 T3
3622 1/1 reg_rdata_next[10] = fault_status_reseed_cnt_qs;
Tests: T1 T2 T3
3623 1/1 reg_rdata_next[11] = fault_status_side_ctrl_fsm_qs;
Tests: T1 T2 T3
3624 1/1 reg_rdata_next[12] = fault_status_side_ctrl_sel_qs;
Tests: T1 T2 T3
3625 1/1 reg_rdata_next[13] = fault_status_key_ecc_qs;
Tests: T1 T2 T3
3626 end
3627
3628 addr_hit[62]: begin
3629 1/1 reg_rdata_next[0] = debug_invalid_creator_seed_qs;
Tests: T1 T2 T3
3630 1/1 reg_rdata_next[1] = debug_invalid_owner_seed_qs;
Tests: T1 T2 T3
3631 1/1 reg_rdata_next[2] = debug_invalid_dev_id_qs;
Tests: T1 T2 T3
3632 1/1 reg_rdata_next[3] = debug_invalid_health_state_qs;
Tests: T1 T2 T3
3633 1/1 reg_rdata_next[4] = debug_invalid_key_version_qs;
Tests: T1 T2 T3
3634 1/1 reg_rdata_next[5] = debug_invalid_key_qs;
Tests: T1 T2 T3
3635 1/1 reg_rdata_next[6] = debug_invalid_digest_qs;
Tests: T1 T2 T3
3636 end
3637
3638 default: begin
3639 reg_rdata_next = '1;
3640 end
3641 endcase
3642 end
3643
3644 // shadow busy
3645 logic shadow_busy;
3646 logic rst_done;
3647 logic shadow_rst_done;
3648 always_ff @(posedge clk_i or negedge rst_ni) begin
3649 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
3650 1/1 rst_done <= '0;
Tests: T1 T2 T3
3651 end else begin
3652 1/1 rst_done <= 1'b1;
Tests: T1 T2 T3
3653 end
3654 end
3655
3656 always_ff @(posedge clk_i or negedge rst_shadowed_ni) begin
3657 1/1 if (!rst_shadowed_ni) begin
Tests: T1 T2 T3
3658 1/1 shadow_rst_done <= '0;
Tests: T1 T2 T3
3659 end else begin
3660 1/1 shadow_rst_done <= 1'b1;
Tests: T1 T2 T3
3661 end
3662 end
3663
3664 // both shadow and normal resets have been released
3665 1/1 assign shadow_busy = ~(rst_done & shadow_rst_done);
Tests: T1 T2 T3
3666
3667 // Collect up storage and update errors
3668 1/1 assign shadowed_storage_err_o = |{
Tests: T1 T2 T3
3669 control_shadowed_operation_storage_err,
3670 control_shadowed_cdi_sel_storage_err,
3671 control_shadowed_dest_sel_storage_err,
3672 reseed_interval_shadowed_storage_err,
3673 max_creator_key_ver_shadowed_storage_err,
3674 max_owner_int_key_ver_shadowed_storage_err,
3675 max_owner_key_ver_shadowed_storage_err
3676 };
3677 1/1 assign shadowed_update_err_o = |{
Tests: T1 T2 T3
3678 control_shadowed_operation_update_err,
3679 control_shadowed_cdi_sel_update_err,
3680 control_shadowed_dest_sel_update_err,
3681 reseed_interval_shadowed_update_err,
3682 max_creator_key_ver_shadowed_update_err,
3683 max_owner_int_key_ver_shadowed_update_err,
3684 max_owner_key_ver_shadowed_update_err
3685 };
3686
3687 // register busy
3688 1/1 assign reg_busy = shadow_busy;
Tests: T1 T2 T3
3689
3690 // Unused signal tieoff
3691
3692 // wdata / byte enable are not always fully used
3693 // add a blanket unused statement to handle lint waivers
3694 logic unused_wdata;
3695 logic unused_be;
3696 1/1 assign unused_wdata = ^reg_wdata;
Tests: T1 T2 T3
3697 1/1 assign unused_be = ^reg_be;
Tests: T1 T2 T3