Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.75	99.04	98.15	98.28	100.00	99.02	98.63	91.14

Total test records in report: 1085

T1005	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_intr_test.3902585492	Sep 11 06:10:19 AM UTC 24	Sep 11 06:10:21 AM UTC 24	176496916 ps
T1006	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_rw.4128126490	Sep 11 06:10:19 AM UTC 24	Sep 11 06:10:21 AM UTC 24	17287048 ps
T1007	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_errors.1544162598	Sep 11 06:10:17 AM UTC 24	Sep 11 06:10:22 AM UTC 24	50710079 ps
T1008	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2135045253	Sep 11 06:10:19 AM UTC 24	Sep 11 06:10:22 AM UTC 24	92316190 ps
T1009	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4057828576	Sep 11 06:10:19 AM UTC 24	Sep 11 06:10:22 AM UTC 24	38669288 ps
T1010	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.3273388338	Sep 11 06:10:22 AM UTC 24	Sep 11 06:10:25 AM UTC 24	57365359 ps
T1011	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3116897313	Sep 11 06:10:20 AM UTC 24	Sep 11 06:10:25 AM UTC 24	91760209 ps
T1012	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.1209163633	Sep 11 06:10:23 AM UTC 24	Sep 11 06:10:25 AM UTC 24	33649750 ps
T1013	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.1213087595	Sep 11 06:10:23 AM UTC 24	Sep 11 06:10:25 AM UTC 24	21296588 ps
T1014	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.456099696	Sep 11 06:10:23 AM UTC 24	Sep 11 06:10:27 AM UTC 24	300869520 ps
T1015	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2766939711	Sep 11 06:10:11 AM UTC 24	Sep 11 06:10:28 AM UTC 24	801682503 ps
T1016	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1455872558	Sep 11 06:10:22 AM UTC 24	Sep 11 06:10:28 AM UTC 24	738565846 ps
T1017	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.3882914363	Sep 11 06:10:22 AM UTC 24	Sep 11 06:10:28 AM UTC 24	2494627858 ps
T1018	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1429934789	Sep 11 06:10:16 AM UTC 24	Sep 11 06:10:29 AM UTC 24	3032071275 ps
T1019	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.785382226	Sep 11 06:10:26 AM UTC 24	Sep 11 06:10:29 AM UTC 24	615416911 ps
T1020	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.1412339148	Sep 11 06:10:26 AM UTC 24	Sep 11 06:10:30 AM UTC 24	48078928 ps
T1021	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1413334197	Sep 11 06:10:26 AM UTC 24	Sep 11 06:10:31 AM UTC 24	188729509 ps
T1022	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.277940153	Sep 11 06:10:29 AM UTC 24	Sep 11 06:10:31 AM UTC 24	11209537 ps
T1023	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.885588211	Sep 11 06:10:29 AM UTC 24	Sep 11 06:10:31 AM UTC 24	98728934 ps
T1024	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1825866763	Sep 11 06:10:30 AM UTC 24	Sep 11 06:10:32 AM UTC 24	48258368 ps
T175	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.708855973	Sep 11 06:10:27 AM UTC 24	Sep 11 06:10:33 AM UTC 24	333507582 ps
T1025	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3336907001	Sep 11 06:10:29 AM UTC 24	Sep 11 06:10:33 AM UTC 24	39475395 ps
T1026	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.985524869	Sep 11 06:10:26 AM UTC 24	Sep 11 06:10:34 AM UTC 24	125705031 ps
T1027	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.2104736439	Sep 11 06:10:33 AM UTC 24	Sep 11 06:10:34 AM UTC 24	65352956 ps
T1028	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3640094763	Sep 11 06:10:30 AM UTC 24	Sep 11 06:10:35 AM UTC 24	716654593 ps
T178	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.2106285628	Sep 11 06:10:31 AM UTC 24	Sep 11 06:10:36 AM UTC 24	405875869 ps
T1029	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.203192953	Sep 11 06:10:31 AM UTC 24	Sep 11 06:10:36 AM UTC 24	45711632 ps
T1030	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.1672509533	Sep 11 06:10:34 AM UTC 24	Sep 11 06:10:36 AM UTC 24	40131706 ps
T1031	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1014237491	Sep 11 06:10:34 AM UTC 24	Sep 11 06:10:36 AM UTC 24	146621095 ps
T1032	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3641592853	Sep 11 06:10:35 AM UTC 24	Sep 11 06:10:38 AM UTC 24	111243623 ps
T1033	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2369940115	Sep 11 06:10:31 AM UTC 24	Sep 11 06:10:38 AM UTC 24	215646272 ps
T1034	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.362383518	Sep 11 06:10:38 AM UTC 24	Sep 11 06:10:40 AM UTC 24	101087683 ps
T1035	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3633631145	Sep 11 06:10:34 AM UTC 24	Sep 11 06:10:39 AM UTC 24	112182101 ps
T1036	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.4141270342	Sep 11 06:10:38 AM UTC 24	Sep 11 06:10:40 AM UTC 24	13997892 ps
T1037	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.4120717142	Sep 11 06:10:38 AM UTC 24	Sep 11 06:10:41 AM UTC 24	45953634 ps
T1038	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.4017528156	Sep 11 06:10:36 AM UTC 24	Sep 11 06:10:41 AM UTC 24	92009365 ps
T1039	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3739463414	Sep 11 06:10:39 AM UTC 24	Sep 11 06:10:42 AM UTC 24	421791117 ps
T1040	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2713925050	Sep 11 06:10:39 AM UTC 24	Sep 11 06:10:42 AM UTC 24	41615594 ps
T1041	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.1224384322	Sep 11 06:10:42 AM UTC 24	Sep 11 06:10:43 AM UTC 24	8131187 ps
T1042	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.1399156622	Sep 11 06:10:40 AM UTC 24	Sep 11 06:10:44 AM UTC 24	246143562 ps
T1043	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.2548481087	Sep 11 06:10:42 AM UTC 24	Sep 11 06:10:44 AM UTC 24	46075107 ps
T164	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.4109081659	Sep 11 06:10:38 AM UTC 24	Sep 11 06:10:45 AM UTC 24	104790693 ps
T1044	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1607144766	Sep 11 06:10:43 AM UTC 24	Sep 11 06:10:46 AM UTC 24	26533057 ps
T1045	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3749825662	Sep 11 06:10:43 AM UTC 24	Sep 11 06:10:47 AM UTC 24	222682263 ps
T1046	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1685881974	Sep 11 06:10:44 AM UTC 24	Sep 11 06:10:48 AM UTC 24	197026594 ps
T1047	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.1429610910	Sep 11 06:10:46 AM UTC 24	Sep 11 06:10:48 AM UTC 24	83491869 ps
T1048	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1278088314	Sep 11 06:10:40 AM UTC 24	Sep 11 06:10:49 AM UTC 24	1235624326 ps
T170	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.3313742002	Sep 11 06:10:41 AM UTC 24	Sep 11 06:10:49 AM UTC 24	539203324 ps
T1049	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.3576608609	Sep 11 06:10:45 AM UTC 24	Sep 11 06:10:49 AM UTC 24	387491646 ps
T1050	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.135879630	Sep 11 06:10:35 AM UTC 24	Sep 11 06:10:51 AM UTC 24	1399673268 ps
T1051	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.3362959652	Sep 11 06:10:49 AM UTC 24	Sep 11 06:10:51 AM UTC 24	45164254 ps
T1052	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3628016307	Sep 11 06:10:49 AM UTC 24	Sep 11 06:10:51 AM UTC 24	39560932 ps
T1053	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.46345170	Sep 11 06:10:50 AM UTC 24	Sep 11 06:10:52 AM UTC 24	7243067 ps
T1054	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.3671018412	Sep 11 06:10:46 AM UTC 24	Sep 11 06:10:52 AM UTC 24	439434628 ps
T1055	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.3682477526	Sep 11 06:10:50 AM UTC 24	Sep 11 06:10:52 AM UTC 24	6745990 ps
T1056	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.1762425994	Sep 11 06:10:50 AM UTC 24	Sep 11 06:10:52 AM UTC 24	105925387 ps
T1057	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.3106151418	Sep 11 06:10:51 AM UTC 24	Sep 11 06:10:53 AM UTC 24	44644208 ps
T1058	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.2170776258	Sep 11 06:10:51 AM UTC 24	Sep 11 06:10:54 AM UTC 24	45761806 ps
T1059	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.3122098079	Sep 11 06:10:53 AM UTC 24	Sep 11 06:10:55 AM UTC 24	33952716 ps
T1060	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3035058949	Sep 11 06:10:49 AM UTC 24	Sep 11 06:10:55 AM UTC 24	2438101026 ps
T1061	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.1743382690	Sep 11 06:10:53 AM UTC 24	Sep 11 06:10:55 AM UTC 24	11217213 ps
T1062	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.3096811350	Sep 11 06:10:53 AM UTC 24	Sep 11 06:10:55 AM UTC 24	15308828 ps
T1063	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.3594884900	Sep 11 06:10:53 AM UTC 24	Sep 11 06:10:55 AM UTC 24	21022213 ps
T1064	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.3612260799	Sep 11 06:10:53 AM UTC 24	Sep 11 06:10:55 AM UTC 24	42457917 ps
T1065	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.3639168194	Sep 11 06:10:54 AM UTC 24	Sep 11 06:10:56 AM UTC 24	53466090 ps
T1066	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.2977266096	Sep 11 06:10:54 AM UTC 24	Sep 11 06:10:56 AM UTC 24	152543891 ps
T1067	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.801144049	Sep 11 06:10:56 AM UTC 24	Sep 11 06:10:58 AM UTC 24	43841628 ps
T1068	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.2913029521	Sep 11 06:10:56 AM UTC 24	Sep 11 06:10:58 AM UTC 24	14340298 ps
T1069	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.1022532830	Sep 11 06:10:56 AM UTC 24	Sep 11 06:10:58 AM UTC 24	38585917 ps
T1070	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.2346393689	Sep 11 06:10:56 AM UTC 24	Sep 11 06:10:58 AM UTC 24	106550938 ps
T1071	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.3018094407	Sep 11 06:10:56 AM UTC 24	Sep 11 06:10:58 AM UTC 24	18308720 ps
T1072	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.544824243	Sep 11 06:10:56 AM UTC 24	Sep 11 06:10:58 AM UTC 24	13886829 ps
T1073	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.2551420506	Sep 11 06:10:57 AM UTC 24	Sep 11 06:10:59 AM UTC 24	80388388 ps
T1074	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.1828075463	Sep 11 06:10:57 AM UTC 24	Sep 11 06:10:59 AM UTC 24	11380066 ps
T1075	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.2029055391	Sep 11 06:10:59 AM UTC 24	Sep 11 06:11:01 AM UTC 24	47213558 ps
T1076	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.3969716986	Sep 11 06:10:59 AM UTC 24	Sep 11 06:11:01 AM UTC 24	24643416 ps
T1077	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.618599904	Sep 11 06:10:59 AM UTC 24	Sep 11 06:11:01 AM UTC 24	27006519 ps
T1078	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.3337189590	Sep 11 06:10:59 AM UTC 24	Sep 11 06:11:01 AM UTC 24	11213983 ps
T1079	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.1317442839	Sep 11 06:10:59 AM UTC 24	Sep 11 06:11:01 AM UTC 24	27504698 ps
T1080	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.1794234074	Sep 11 06:10:59 AM UTC 24	Sep 11 06:11:01 AM UTC 24	24317154 ps
T1081	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3025367809	Sep 11 06:10:45 AM UTC 24	Sep 11 06:11:02 AM UTC 24	1645624734 ps
T1082	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.1308382668	Sep 11 06:11:00 AM UTC 24	Sep 11 06:11:02 AM UTC 24	12040380 ps
T1083	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.224344104	Sep 11 06:11:00 AM UTC 24	Sep 11 06:11:02 AM UTC 24	27297380 ps
T1084	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.2668701062	Sep 11 06:11:02 AM UTC 24	Sep 11 06:11:04 AM UTC 24	35408397 ps
T1085	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.696017059	Sep 11 06:11:02 AM UTC 24	Sep 11 06:11:04 AM UTC 24	13261490 ps

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/0.keymgr_cfg_regwen.625135378
Short name	T13
Test name
Test status
Simulation time	283046971 ps
CPU time	12.47 seconds
Started	Sep 11 05:47:12 AM UTC 24
Finished	Sep 11 05:47:26 AM UTC 24
Peak memory	226140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625135378 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.625135378
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/3.keymgr_stress_all.2624026203
Short name	T68
Test name
Test status
Simulation time	6064830153 ps
CPU time	58.22 seconds
Started	Sep 11 05:50:38 AM UTC 24
Finished	Sep 11 05:51:38 AM UTC 24
Peak memory	232568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624026203 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2624026203
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/0.keymgr_hwsw_invalid_input.2397569663
Short name	T17
Test name
Test status
Simulation time	123177381 ps
CPU time	4.1 seconds
Started	Sep 11 05:47:46 AM UTC 24
Finished	Sep 11 05:47:51 AM UTC 24
Peak memory	226140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397569663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2397569663
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all_with_rand_reset.3840512037
Short name	T18
Test name
Test status
Simulation time	1291607226 ps
CPU time	25.36 seconds
Started	Sep 11 05:48:05 AM UTC 24
Finished	Sep 11 05:48:32 AM UTC 24
Peak memory	232764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3840512037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr _stress_all_with_rand_reset.3840512037
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/0.keymgr_sec_cm.3652055894
Short name	T10
Test name
Test status
Simulation time	408844904 ps
CPU time	8.47 seconds
Started	Sep 11 05:48:12 AM UTC 24
Finished	Sep 11 05:48:22 AM UTC 24
Peak memory	252568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652055894 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3652055894
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3204330115
Short name	T81
Test name
Test status
Simulation time	1684876896 ps
CPU time	11.6 seconds
Started	Sep 11 06:08:42 AM UTC 24
Finished	Sep 11 06:08:54 AM UTC 24
Peak memory	226560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204330115 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors_with_csr_rw.3204330115
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/2.keymgr_custom_cm.2939776362
Short name	T6
Test name
Test status
Simulation time	248338357 ps
CPU time	3.41 seconds
Started	Sep 11 05:49:57 AM UTC 24
Finished	Sep 11 05:50:02 AM UTC 24
Peak memory	232584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939776362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2939776362
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/6.keymgr_custom_cm.2299386138
Short name	T29
Test name
Test status
Simulation time	272213000 ps
CPU time	6.18 seconds
Started	Sep 11 05:52:45 AM UTC 24
Finished	Sep 11 05:52:53 AM UTC 24
Peak memory	228136 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299386138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2299386138
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all.2238078489
Short name	T154
Test name
Test status
Simulation time	7263195746 ps
CPU time	45.54 seconds
Started	Sep 11 05:53:15 AM UTC 24
Finished	Sep 11 05:54:02 AM UTC 24
Peak memory	226136 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238078489 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2238078489
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/7.keymgr_custom_cm.1585418636
Short name	T9
Test name
Test status
Simulation time	79201274 ps
CPU time	3.64 seconds
Started	Sep 11 05:53:12 AM UTC 24
Finished	Sep 11 05:53:17 AM UTC 24
Peak memory	231072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585418636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1585418636
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/5.keymgr_cfg_regwen.1663617306
Short name	T110
Test name
Test status
Simulation time	1827844556 ps
CPU time	14.92 seconds
Started	Sep 11 05:52:05 AM UTC 24
Finished	Sep 11 05:52:21 AM UTC 24
Peak memory	226396 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663617306 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1663617306
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/35.keymgr_cfg_regwen.3960930537
Short name	T360
Test name
Test status
Simulation time	1369197453 ps
CPU time	19.6 seconds
Started	Sep 11 06:04:15 AM UTC 24
Finished	Sep 11 06:04:36 AM UTC 24
Peak memory	226072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960930537 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3960930537
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/35.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/1.keymgr_stress_all_with_rand_reset.555513301
Short name	T66
Test name
Test status
Simulation time	2030701275 ps
CPU time	25.14 seconds
Started	Sep 11 05:49:17 AM UTC 24
Finished	Sep 11 05:49:44 AM UTC 24
Peak memory	232376 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=555513301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_ stress_all_with_rand_reset.555513301
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/18.keymgr_hwsw_invalid_input.3064622082
Short name	T54
Test name
Test status
Simulation time	1057648423 ps
CPU time	9.49 seconds
Started	Sep 11 05:58:05 AM UTC 24
Finished	Sep 11 05:58:16 AM UTC 24
Peak memory	223932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064622082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3064622082
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/13.keymgr_cfg_regwen.2163824670
Short name	T380
Test name
Test status
Simulation time	150453137 ps
CPU time	8.64 seconds
Started	Sep 11 05:56:05 AM UTC 24
Finished	Sep 11 05:56:14 AM UTC 24
Peak memory	226144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163824670 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2163824670
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.506948264
Short name	T91
Test name
Test status
Simulation time	1950852853 ps
CPU time	5.23 seconds
Started	Sep 11 06:09:34 AM UTC 24
Finished	Sep 11 06:09:40 AM UTC 24
Peak memory	226408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506948264 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors.506948264
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all_with_rand_reset.1148007757
Short name	T97
Test name
Test status
Simulation time	3464940880 ps
CPU time	48.65 seconds
Started	Sep 11 05:54:59 AM UTC 24
Finished	Sep 11 05:55:49 AM UTC 24
Peak memory	231708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1148007757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymg r_stress_all_with_rand_reset.1148007757
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/4.keymgr_kmac_rsp_err.698304096
Short name	T42
Test name
Test status
Simulation time	786780331 ps
CPU time	5.87 seconds
Started	Sep 11 05:51:31 AM UTC 24
Finished	Sep 11 05:51:38 AM UTC 24
Peak memory	225996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698304096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.698304096
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/17.keymgr_cfg_regwen.3555077409
Short name	T296
Test name
Test status
Simulation time	2586480251 ps
CPU time	75.64 seconds
Started	Sep 11 05:57:34 AM UTC 24
Finished	Sep 11 05:58:51 AM UTC 24
Peak memory	226212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555077409 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3555077409
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all.600047559
Short name	T111
Test name
Test status
Simulation time	569013187 ps
CPU time	23.08 seconds
Started	Sep 11 05:52:23 AM UTC 24
Finished	Sep 11 05:52:47 AM UTC 24
Peak memory	232252 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600047559 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.600047559
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/1.keymgr_custom_cm.2363901381
Short name	T38
Test name
Test status
Simulation time	262916629 ps
CPU time	8.68 seconds
Started	Sep 11 05:49:07 AM UTC 24
Finished	Sep 11 05:49:17 AM UTC 24
Peak memory	220344 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363901381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2363901381
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/9.keymgr_custom_cm.4250558781
Short name	T19
Test name
Test status
Simulation time	214344683 ps
CPU time	4.68 seconds
Started	Sep 11 05:54:12 AM UTC 24
Finished	Sep 11 05:54:17 AM UTC 24
Peak memory	231556 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250558781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.4250558781
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/32.keymgr_cfg_regwen.163624032
Short name	T368
Test name
Test status
Simulation time	234623503 ps
CPU time	12.74 seconds
Started	Sep 11 06:03:22 AM UTC 24
Finished	Sep 11 06:03:36 AM UTC 24
Peak memory	226064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163624032 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.163624032
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/32.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all.589513115
Short name	T7
Test name
Test status
Simulation time	1575868496 ps
CPU time	37.1 seconds
Started	Sep 11 05:56:36 AM UTC 24
Finished	Sep 11 05:57:15 AM UTC 24
Peak memory	228256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589513115 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.589513115
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/30.keymgr_hwsw_invalid_input.535953271
Short name	T59
Test name
Test status
Simulation time	145104175 ps
CPU time	6.34 seconds
Started	Sep 11 06:02:39 AM UTC 24
Finished	Sep 11 06:02:46 AM UTC 24
Peak memory	226104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535953271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.535953271
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/30.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/1.keymgr_cfg_regwen.3761481674
Short name	T84
Test name
Test status
Simulation time	572269897 ps
CPU time	9.66 seconds
Started	Sep 11 05:48:51 AM UTC 24
Finished	Sep 11 05:49:01 AM UTC 24
Peak memory	226176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761481674 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3761481674
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/4.keymgr_custom_cm.847760956
Short name	T129
Test name
Test status
Simulation time	111960048 ps
CPU time	2.86 seconds
Started	Sep 11 05:51:34 AM UTC 24
Finished	Sep 11 05:51:38 AM UTC 24
Peak memory	232528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847760956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.847760956
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/40.keymgr_cfg_regwen.389764252
Short name	T341
Test name
Test status
Simulation time	231137215 ps
CPU time	6.93 seconds
Started	Sep 11 06:05:49 AM UTC 24
Finished	Sep 11 06:05:57 AM UTC 24
Peak memory	224016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389764252 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.389764252
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/40.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/0.keymgr_sw_invalid_input.4212591698
Short name	T16
Test name
Test status
Simulation time	117150375 ps
CPU time	5.23 seconds
Started	Sep 11 05:47:39 AM UTC 24
Finished	Sep 11 05:47:45 AM UTC 24
Peak memory	217872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212591698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.4212591698
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/22.keymgr_stress_all.3692170243
Short name	T141
Test name
Test status
Simulation time	1391788173 ps
CPU time	29.27 seconds
Started	Sep 11 05:59:39 AM UTC 24
Finished	Sep 11 06:00:10 AM UTC 24
Peak memory	226140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692170243 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3692170243
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/22.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/10.keymgr_kmac_rsp_err.1926591555
Short name	T274
Test name
Test status
Simulation time	717984260 ps
CPU time	6.01 seconds
Started	Sep 11 05:54:51 AM UTC 24
Finished	Sep 11 05:54:58 AM UTC 24
Peak memory	226044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926591555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1926591555
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/4.keymgr_sync_async_fault_cross.1513550419
Short name	T79
Test name
Test status
Simulation time	439797151 ps
CPU time	3.79 seconds
Started	Sep 11 05:51:39 AM UTC 24
Finished	Sep 11 05:51:44 AM UTC 24
Peak memory	219928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513550419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1513550419
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/0.keymgr_alert_test.1656263212
Short name	T63
Test name
Test status
Simulation time	13447609 ps
CPU time	1.13 seconds
Started	Sep 11 05:48:22 AM UTC 24
Finished	Sep 11 05:48:24 AM UTC 24
Peak memory	213588 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656263212 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1656263212
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_intg_err.3427776891
Short name	T160
Test name
Test status
Simulation time	208938941 ps
CPU time	9.19 seconds
Started	Sep 11 06:10:03 AM UTC 24
Finished	Sep 11 06:10:13 AM UTC 24
Peak memory	226404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427776891 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err.3427776891
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all.2542974594
Short name	T196
Test name
Test status
Simulation time	1274637148 ps
CPU time	28.44 seconds
Started	Sep 11 05:55:25 AM UTC 24
Finished	Sep 11 05:55:55 AM UTC 24
Peak memory	232172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542974594 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2542974594
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/2.keymgr_cfg_regwen.892428764
Short name	T108
Test name
Test status
Simulation time	81488237 ps
CPU time	4.19 seconds
Started	Sep 11 05:49:46 AM UTC 24
Finished	Sep 11 05:49:51 AM UTC 24
Peak memory	226140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892428764 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.892428764
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/46.keymgr_cfg_regwen.1597776628
Short name	T382
Test name
Test status
Simulation time	239372727 ps
CPU time	13.24 seconds
Started	Sep 11 06:07:45 AM UTC 24
Finished	Sep 11 06:07:59 AM UTC 24
Peak memory	226072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597776628 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1597776628
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/46.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_intg_err.550643612
Short name	T161
Test name
Test status
Simulation time	335990134 ps
CPU time	6 seconds
Started	Sep 11 06:09:13 AM UTC 24
Finished	Sep 11 06:09:20 AM UTC 24
Peak memory	226140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550643612 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.550643612
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_intg_err.3006743418
Short name	T168
Test name
Test status
Simulation time	987145972 ps
CPU time	11.99 seconds
Started	Sep 11 06:09:41 AM UTC 24
Finished	Sep 11 06:09:55 AM UTC 24
Peak memory	226140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006743418 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.3006743418
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all.3189850757
Short name	T198
Test name
Test status
Simulation time	6306969640 ps
CPU time	55.59 seconds
Started	Sep 11 05:59:58 AM UTC 24
Finished	Sep 11 06:00:56 AM UTC 24
Peak memory	232664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189850757 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3189850757
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/23.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/4.keymgr_stress_all.3384506113
Short name	T189
Test name
Test status
Simulation time	1269170086 ps
CPU time	18.94 seconds
Started	Sep 11 05:51:39 AM UTC 24
Finished	Sep 11 05:51:59 AM UTC 24
Peak memory	226144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384506113 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3384506113
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/11.keymgr_hwsw_invalid_input.3174886039
Short name	T57
Test name
Test status
Simulation time	375205418 ps
CPU time	5.75 seconds
Started	Sep 11 05:55:18 AM UTC 24
Finished	Sep 11 05:55:25 AM UTC 24
Peak memory	226140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174886039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3174886039
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/27.keymgr_stress_all.1402195724
Short name	T326
Test name
Test status
Simulation time	939791344 ps
CPU time	37.87 seconds
Started	Sep 11 06:01:35 AM UTC 24
Finished	Sep 11 06:02:14 AM UTC 24
Peak memory	230864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402195724 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1402195724
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/27.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/28.keymgr_cfg_regwen.1143458350
Short name	T324
Test name
Test status
Simulation time	2089469449 ps
CPU time	24.66 seconds
Started	Sep 11 06:01:43 AM UTC 24
Finished	Sep 11 06:02:09 AM UTC 24
Peak memory	226068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143458350 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1143458350
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/28.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/40.keymgr_hwsw_invalid_input.1598257258
Short name	T289
Test name
Test status
Simulation time	73767373 ps
CPU time	4.08 seconds
Started	Sep 11 06:05:52 AM UTC 24
Finished	Sep 11 06:05:57 AM UTC 24
Peak memory	230500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598257258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1598257258
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/40.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/12.keymgr_kmac_rsp_err.1283844412
Short name	T303
Test name
Test status
Simulation time	425383679 ps
CPU time	4.14 seconds
Started	Sep 11 05:55:52 AM UTC 24
Finished	Sep 11 05:55:57 AM UTC 24
Peak memory	226336 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283844412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1283844412
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/16.keymgr_stress_all.3168535602
Short name	T369
Test name
Test status
Simulation time	14685591855 ps
CPU time	246.01 seconds
Started	Sep 11 05:57:24 AM UTC 24
Finished	Sep 11 06:01:35 AM UTC 24
Peak memory	230268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168535602 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3168535602
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/20.keymgr_kmac_rsp_err.2233103719
Short name	T540
Test name
Test status
Simulation time	245144892 ps
CPU time	6.31 seconds
Started	Sep 11 05:58:54 AM UTC 24
Finished	Sep 11 05:59:02 AM UTC 24
Peak memory	232108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233103719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2233103719
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/20.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/6.keymgr_sync_async_fault_cross.4281047520
Short name	T144
Test name
Test status
Simulation time	60346914 ps
CPU time	2.7 seconds
Started	Sep 11 05:52:48 AM UTC 24
Finished	Sep 11 05:52:51 AM UTC 24
Peak memory	218028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281047520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.4281047520
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.4109081659
Short name	T164
Test name
Test status
Simulation time	104790693 ps
CPU time	6.24 seconds
Started	Sep 11 06:10:38 AM UTC 24
Finished	Sep 11 06:10:45 AM UTC 24
Peak memory	226396 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109081659 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err.4109081659
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_intg_err.2719634598
Short name	T167
Test name
Test status
Simulation time	74337557 ps
CPU time	3.34 seconds
Started	Sep 11 06:09:36 AM UTC 24
Finished	Sep 11 06:09:41 AM UTC 24
Peak memory	226068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719634598 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.2719634598
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/3.keymgr_sec_cm.3897961112
Short name	T43
Test name
Test status
Simulation time	2093284956 ps
CPU time	13.85 seconds
Started	Sep 11 05:50:41 AM UTC 24
Finished	Sep 11 05:50:56 AM UTC 24
Peak memory	262364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897961112 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3897961112
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/38.keymgr_custom_cm.3591934595
Short name	T182
Test name
Test status
Simulation time	291479052 ps
CPU time	3.64 seconds
Started	Sep 11 06:05:13 AM UTC 24
Finished	Sep 11 06:05:17 AM UTC 24
Peak memory	226484 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591934595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3591934595
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/38.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/44.keymgr_custom_cm.1884872953
Short name	T130
Test name
Test status
Simulation time	275033028 ps
CPU time	4.25 seconds
Started	Sep 11 06:07:13 AM UTC 24
Finished	Sep 11 06:07:18 AM UTC 24
Peak memory	232780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884872953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1884872953
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/44.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/27.keymgr_custom_cm.1622453234
Short name	T132
Test name
Test status
Simulation time	88591071 ps
CPU time	2.55 seconds
Started	Sep 11 06:01:34 AM UTC 24
Finished	Sep 11 06:01:37 AM UTC 24
Peak memory	228384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622453234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1622453234
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/27.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/39.keymgr_custom_cm.380010128
Short name	T131
Test name
Test status
Simulation time	79989314 ps
CPU time	3.3 seconds
Started	Sep 11 06:05:36 AM UTC 24
Finished	Sep 11 06:05:40 AM UTC 24
Peak memory	228400 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380010128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.380010128
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/39.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/12.keymgr_stress_all_with_rand_reset.477445125
Short name	T98
Test name
Test status
Simulation time	907960263 ps
CPU time	12.66 seconds
Started	Sep 11 05:55:57 AM UTC 24
Finished	Sep 11 05:56:11 AM UTC 24
Peak memory	232180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=477445125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr _stress_all_with_rand_reset.477445125
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/14.keymgr_cfg_regwen.137467223
Short name	T247
Test name
Test status
Simulation time	224899065 ps
CPU time	4.8 seconds
Started	Sep 11 05:56:25 AM UTC 24
Finished	Sep 11 05:56:31 AM UTC 24
Peak memory	226068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137467223 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.137467223
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/16.keymgr_cfg_regwen.2223687388
Short name	T399
Test name
Test status
Simulation time	60685539 ps
CPU time	4.75 seconds
Started	Sep 11 05:57:16 AM UTC 24
Finished	Sep 11 05:57:22 AM UTC 24
Peak memory	226156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223687388 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2223687388
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/27.keymgr_kmac_rsp_err.2203985731
Short name	T257
Test name
Test status
Simulation time	165245720 ps
CPU time	2.09 seconds
Started	Sep 11 06:01:30 AM UTC 24
Finished	Sep 11 06:01:34 AM UTC 24
Peak memory	230704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203985731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2203985731
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/27.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/4.keymgr_cfg_regwen.2456930309
Short name	T128
Test name
Test status
Simulation time	624785355 ps
CPU time	10.18 seconds
Started	Sep 11 05:51:09 AM UTC 24
Finished	Sep 11 05:51:20 AM UTC 24
Peak memory	232240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456930309 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2456930309
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_kmac.981252933
Short name	T3
Test name
Test status
Simulation time	695603978 ps
CPU time	5.62 seconds
Started	Sep 11 05:46:53 AM UTC 24
Finished	Sep 11 05:47:00 AM UTC 24
Peak memory	216160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981252933 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.981252933
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_kmac.972079087
Short name	T74
Test name
Test status
Simulation time	575553419 ps
CPU time	4.24 seconds
Started	Sep 11 05:48:34 AM UTC 24
Finished	Sep 11 05:48:40 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972079087 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.972079087
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/10.keymgr_sync_async_fault_cross.342135222
Short name	T461
Test name
Test status
Simulation time	454673966 ps
CPU time	3.09 seconds
Started	Sep 11 05:54:55 AM UTC 24
Finished	Sep 11 05:54:59 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342135222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.342135222
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/13.keymgr_kmac_rsp_err.966798349
Short name	T24
Test name
Test status
Simulation time	65095118 ps
CPU time	4.2 seconds
Started	Sep 11 05:56:12 AM UTC 24
Finished	Sep 11 05:56:18 AM UTC 24
Peak memory	232164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966798349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.966798349
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/14.keymgr_random.3760153827
Short name	T390
Test name
Test status
Simulation time	58527520 ps
CPU time	3.64 seconds
Started	Sep 11 05:56:25 AM UTC 24
Finished	Sep 11 05:56:30 AM UTC 24
Peak memory	218212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760153827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3760153827
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/15.keymgr_cfg_regwen.1056242422
Short name	T241
Test name
Test status
Simulation time	68489199 ps
CPU time	3.1 seconds
Started	Sep 11 05:56:49 AM UTC 24
Finished	Sep 11 05:56:53 AM UTC 24
Peak memory	224352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056242422 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1056242422
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/19.keymgr_hwsw_invalid_input.3096646877
Short name	T304
Test name
Test status
Simulation time	232946002 ps
CPU time	3.52 seconds
Started	Sep 11 05:58:29 AM UTC 24
Finished	Sep 11 05:58:34 AM UTC 24
Peak memory	224356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096646877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3096646877
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_otbn.241345099
Short name	T413
Test name
Test status
Simulation time	773811387 ps
CPU time	7.33 seconds
Started	Sep 11 05:59:07 AM UTC 24
Finished	Sep 11 05:59:15 AM UTC 24
Peak memory	215900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241345099 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.241345099
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/21.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all.3120812379
Short name	T351
Test name
Test status
Simulation time	10787336155 ps
CPU time	53.61 seconds
Started	Sep 11 06:01:58 AM UTC 24
Finished	Sep 11 06:02:53 AM UTC 24
Peak memory	232336 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120812379 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3120812379
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/28.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/34.keymgr_hwsw_invalid_input.1514531812
Short name	T239
Test name
Test status
Simulation time	1919354803 ps
CPU time	5.46 seconds
Started	Sep 11 06:04:07 AM UTC 24
Finished	Sep 11 06:04:13 AM UTC 24
Peak memory	224352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514531812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1514531812
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/34.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/39.keymgr_kmac_rsp_err.959848726
Short name	T377
Test name
Test status
Simulation time	43763940 ps
CPU time	3.41 seconds
Started	Sep 11 06:05:35 AM UTC 24
Finished	Sep 11 06:05:39 AM UTC 24
Peak memory	226380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959848726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.959848726
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/39.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/41.keymgr_hwsw_invalid_input.831927987
Short name	T797
Test name
Test status
Simulation time	97501779 ps
CPU time	4.03 seconds
Started	Sep 11 06:06:11 AM UTC 24
Finished	Sep 11 06:06:16 AM UTC 24
Peak memory	226400 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831927987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.831927987
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/41.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all.344921329
Short name	T863
Test name
Test status
Simulation time	9132938729 ps
CPU time	71.42 seconds
Started	Sep 11 06:06:30 AM UTC 24
Finished	Sep 11 06:07:44 AM UTC 24
Peak memory	230304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344921329 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.344921329
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/42.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/47.keymgr_hwsw_invalid_input.2240331525
Short name	T315
Test name
Test status
Simulation time	188698105 ps
CPU time	3.04 seconds
Started	Sep 11 06:08:01 AM UTC 24
Finished	Sep 11 06:08:05 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240331525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2240331525
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/47.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_aes.978043
Short name	T343
Test name
Test status
Simulation time	1782566494 ps
CPU time	4.72 seconds
Started	Sep 11 05:53:21 AM UTC 24
Finished	Sep 11 05:53:27 AM UTC 24
Peak memory	215920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978043 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.978043
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all_with_rand_reset.295153125
Short name	T96
Test name
Test status
Simulation time	4939425609 ps
CPU time	24.83 seconds
Started	Sep 11 05:54:18 AM UTC 24
Finished	Sep 11 05:54:44 AM UTC 24
Peak memory	232360 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=295153125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_ stress_all_with_rand_reset.295153125
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_intg_err.767818447
Short name	T176
Test name
Test status
Simulation time	130588212 ps
CPU time	3.99 seconds
Started	Sep 11 06:10:07 AM UTC 24
Finished	Sep 11 06:10:12 AM UTC 24
Peak memory	226260 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767818447 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err.767818447
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.2106285628
Short name	T178
Test name
Test status
Simulation time	405875869 ps
CPU time	3.41 seconds
Started	Sep 11 06:10:31 AM UTC 24
Finished	Sep 11 06:10:36 AM UTC 24
Peak memory	226340 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106285628 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err.2106285628
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_intg_err.1359023183
Short name	T171
Test name
Test status
Simulation time	603188287 ps
CPU time	6.13 seconds
Started	Sep 11 06:09:56 AM UTC 24
Finished	Sep 11 06:10:03 AM UTC 24
Peak memory	226124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359023183 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.1359023183
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/10.keymgr_custom_cm.3197835496
Short name	T115
Test name
Test status
Simulation time	187694200 ps
CPU time	8.89 seconds
Started	Sep 11 05:54:52 AM UTC 24
Finished	Sep 11 05:55:02 AM UTC 24
Peak memory	232468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197835496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3197835496
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/3.keymgr_custom_cm.3290887012
Short name	T127
Test name
Test status
Simulation time	82188033 ps
CPU time	2.75 seconds
Started	Sep 11 05:50:34 AM UTC 24
Finished	Sep 11 05:50:38 AM UTC 24
Peak memory	226752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290887012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3290887012
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/0.keymgr_custom_cm.3374054064
Short name	T28
Test name
Test status
Simulation time	139610800 ps
CPU time	2.42 seconds
Started	Sep 11 05:47:57 AM UTC 24
Finished	Sep 11 05:48:00 AM UTC 24
Peak memory	226172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374054064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3374054064
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/0.keymgr_lc_disable.1728615415
Short name	T15
Test name
Test status
Simulation time	303584719 ps
CPU time	4.1 seconds
Started	Sep 11 05:47:32 AM UTC 24
Finished	Sep 11 05:47:38 AM UTC 24
Peak memory	230344 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728615415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1728615415
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/11.keymgr_lc_disable.4209619901
Short name	T116
Test name
Test status
Simulation time	272656238 ps
CPU time	7.12 seconds
Started	Sep 11 05:55:15 AM UTC 24
Finished	Sep 11 05:55:23 AM UTC 24
Peak memory	232248 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209619901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.4209619901
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/15.keymgr_sw_invalid_input.2076518072
Short name	T345
Test name
Test status
Simulation time	139800069 ps
CPU time	3.06 seconds
Started	Sep 11 05:56:54 AM UTC 24
Finished	Sep 11 05:56:58 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076518072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2076518072
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/18.keymgr_kmac_rsp_err.397057757
Short name	T318
Test name
Test status
Simulation time	112364035 ps
CPU time	3.41 seconds
Started	Sep 11 05:58:05 AM UTC 24
Finished	Sep 11 05:58:10 AM UTC 24
Peak memory	232084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397057757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.397057757
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/19.keymgr_lc_disable.3893916464
Short name	T220
Test name
Test status
Simulation time	75212853 ps
CPU time	3.64 seconds
Started	Sep 11 05:58:27 AM UTC 24
Finished	Sep 11 05:58:32 AM UTC 24
Peak memory	217876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893916464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3893916464
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/19.keymgr_stress_all.227722382
Short name	T8
Test name
Test status
Simulation time	1243347129 ps
CPU time	15.58 seconds
Started	Sep 11 05:58:38 AM UTC 24
Finished	Sep 11 05:58:55 AM UTC 24
Peak memory	226140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227722382 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.227722382
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/24.keymgr_lc_disable.4102721533
Short name	T231
Test name
Test status
Simulation time	55168404 ps
CPU time	4.34 seconds
Started	Sep 11 06:00:15 AM UTC 24
Finished	Sep 11 06:00:20 AM UTC 24
Peak memory	224360 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102721533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.4102721533
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/24.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all.2622721727
Short name	T269
Test name
Test status
Simulation time	3655239176 ps
CPU time	39.52 seconds
Started	Sep 11 06:00:22 AM UTC 24
Finished	Sep 11 06:01:03 AM UTC 24
Peak memory	232128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622721727 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2622721727
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/24.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/25.keymgr_cfg_regwen.3482827445
Short name	T421
Test name
Test status
Simulation time	78434585 ps
CPU time	5.07 seconds
Started	Sep 11 06:00:30 AM UTC 24
Finished	Sep 11 06:00:36 AM UTC 24
Peak memory	224020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482827445 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3482827445
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/25.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_protect.1778882092
Short name	T339
Test name
Test status
Simulation time	1085960776 ps
CPU time	7.4 seconds
Started	Sep 11 06:00:38 AM UTC 24
Finished	Sep 11 06:00:47 AM UTC 24
Peak memory	230332 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778882092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1778882092
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/25.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all.2646995130
Short name	T276
Test name
Test status
Simulation time	5183895045 ps
CPU time	95.19 seconds
Started	Sep 11 06:02:24 AM UTC 24
Finished	Sep 11 06:04:01 AM UTC 24
Peak memory	228180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646995130 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2646995130
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/29.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/30.keymgr_lc_disable.210633451
Short name	T221
Test name
Test status
Simulation time	52839087 ps
CPU time	2.99 seconds
Started	Sep 11 06:02:35 AM UTC 24
Finished	Sep 11 06:02:40 AM UTC 24
Peak memory	226400 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210633451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.210633451
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/30.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all.4216944615
Short name	T233
Test name
Test status
Simulation time	1798798415 ps
CPU time	46.98 seconds
Started	Sep 11 06:02:45 AM UTC 24
Finished	Sep 11 06:03:33 AM UTC 24
Peak memory	226140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216944615 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.4216944615
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/30.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/33.keymgr_cfg_regwen.971253372
Short name	T308
Test name
Test status
Simulation time	1237964011 ps
CPU time	13.73 seconds
Started	Sep 11 06:03:43 AM UTC 24
Finished	Sep 11 06:03:58 AM UTC 24
Peak memory	226336 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971253372 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.971253372
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/33.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/44.keymgr_stress_all.4002299422
Short name	T361
Test name
Test status
Simulation time	2655479306 ps
CPU time	28.25 seconds
Started	Sep 11 06:07:14 AM UTC 24
Finished	Sep 11 06:07:44 AM UTC 24
Peak memory	232564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002299422 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.4002299422
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/44.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all.1216119960
Short name	T234
Test name
Test status
Simulation time	6699144007 ps
CPU time	47.18 seconds
Started	Sep 11 06:08:20 AM UTC 24
Finished	Sep 11 06:09:09 AM UTC 24
Peak memory	232628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216119960 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1216119960
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/48.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/6.keymgr_hwsw_invalid_input.119696068
Short name	T46
Test name
Test status
Simulation time	148723591 ps
CPU time	3.79 seconds
Started	Sep 11 05:52:42 AM UTC 24
Finished	Sep 11 05:52:47 AM UTC 24
Peak memory	226180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119696068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.119696068
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/8.keymgr_custom_cm.359824155
Short name	T133
Test name
Test status
Simulation time	329338731 ps
CPU time	3.35 seconds
Started	Sep 11 05:53:37 AM UTC 24
Finished	Sep 11 05:53:42 AM UTC 24
Peak memory	228840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359824155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.359824155
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_aliasing.1716904124
Short name	T119
Test name
Test status
Simulation time	143315636 ps
CPU time	5.56 seconds
Started	Sep 11 06:08:54 AM UTC 24
Finished	Sep 11 06:09:01 AM UTC 24
Peak memory	215964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716904124 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1716904124
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1818829179
Short name	T923
Test name
Test status
Simulation time	577458282 ps
CPU time	17.57 seconds
Started	Sep 11 06:08:53 AM UTC 24
Finished	Sep 11 06:09:12 AM UTC 24
Peak memory	215844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818829179 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1818829179
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2966070826
Short name	T159
Test name
Test status
Simulation time	18550297 ps
CPU time	1.49 seconds
Started	Sep 11 06:08:50 AM UTC 24
Finished	Sep 11 06:08:52 AM UTC 24
Peak memory	213644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966070826 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2966070826
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.51834441
Short name	T398
Test name
Test status
Simulation time	26103460 ps
CPU time	2.14 seconds
Started	Sep 11 06:08:56 AM UTC 24
Finished	Sep 11 06:08:59 AM UTC 24
Peak memory	226500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=51834441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_mem_rw_wit h_rand_reset.51834441
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_rw.2510827198
Short name	T117
Test name
Test status
Simulation time	24023081 ps
CPU time	1.51 seconds
Started	Sep 11 06:08:51 AM UTC 24
Finished	Sep 11 06:08:53 AM UTC 24
Peak memory	213116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510827198 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2510827198
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_intr_test.901864272
Short name	T920
Test name
Test status
Simulation time	37301607 ps
CPU time	1 seconds
Started	Sep 11 06:08:47 AM UTC 24
Finished	Sep 11 06:08:49 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901864272 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.901864272
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1300064413
Short name	T118
Test name
Test status
Simulation time	32387165 ps
CPU time	1.77 seconds
Started	Sep 11 06:08:55 AM UTC 24
Finished	Sep 11 06:08:58 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300064413 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_same_csr_outstanding.1300064413
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1265710798
Short name	T85
Test name
Test status
Simulation time	1033914719 ps
CPU time	3.5 seconds
Started	Sep 11 06:08:41 AM UTC 24
Finished	Sep 11 06:08:45 AM UTC 24
Peak memory	226672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265710798 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors.1265710798
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_errors.1479404687
Short name	T919
Test name
Test status
Simulation time	19900090 ps
CPU time	1.72 seconds
Started	Sep 11 06:08:44 AM UTC 24
Finished	Sep 11 06:08:46 AM UTC 24
Peak memory	223816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479404687 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1479404687
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_intg_err.1868776559
Short name	T158
Test name
Test status
Simulation time	942053880 ps
CPU time	3.61 seconds
Started	Sep 11 06:08:46 AM UTC 24
Finished	Sep 11 06:08:51 AM UTC 24
Peak memory	226264 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868776559 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.1868776559
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_aliasing.1352305378
Short name	T930
Test name
Test status
Simulation time	4915260298 ps
CPU time	14.39 seconds
Started	Sep 11 06:09:08 AM UTC 24
Finished	Sep 11 06:09:23 AM UTC 24
Peak memory	216220 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352305378 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1352305378
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3646279526
Short name	T925
Test name
Test status
Simulation time	453592837 ps
CPU time	7.08 seconds
Started	Sep 11 06:09:07 AM UTC 24
Finished	Sep 11 06:09:15 AM UTC 24
Peak memory	215868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646279526 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3646279526
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1368090256
Short name	T202
Test name
Test status
Simulation time	35602039 ps
CPU time	1.36 seconds
Started	Sep 11 06:09:05 AM UTC 24
Finished	Sep 11 06:09:07 AM UTC 24
Peak memory	213648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368090256 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1368090256
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.4207146072
Short name	T924
Test name
Test status
Simulation time	46255296 ps
CPU time	1.66 seconds
Started	Sep 11 06:09:10 AM UTC 24
Finished	Sep 11 06:09:12 AM UTC 24
Peak memory	223816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4207146072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_mem_rw_w ith_rand_reset.4207146072
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_rw.2239813160
Short name	T120
Test name
Test status
Simulation time	33025353 ps
CPU time	1.47 seconds
Started	Sep 11 06:09:07 AM UTC 24
Finished	Sep 11 06:09:09 AM UTC 24
Peak memory	213572 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239813160 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2239813160
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_intr_test.3804298170
Short name	T922
Test name
Test status
Simulation time	41062567 ps
CPU time	1.07 seconds
Started	Sep 11 06:09:03 AM UTC 24
Finished	Sep 11 06:09:06 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804298170 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3804298170
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3432113137
Short name	T121
Test name
Test status
Simulation time	464061606 ps
CPU time	3.6 seconds
Started	Sep 11 06:09:08 AM UTC 24
Finished	Sep 11 06:09:12 AM UTC 24
Peak memory	216028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432113137 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_same_csr_outstanding.3432113137
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2037072847
Short name	T86
Test name
Test status
Simulation time	300461225 ps
CPU time	3.13 seconds
Started	Sep 11 06:08:58 AM UTC 24
Finished	Sep 11 06:09:02 AM UTC 24
Peak memory	226416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037072847 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors.2037072847
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.480812254
Short name	T82
Test name
Test status
Simulation time	2134394543 ps
CPU time	10.64 seconds
Started	Sep 11 06:08:58 AM UTC 24
Finished	Sep 11 06:09:10 AM UTC 24
Peak memory	226420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480812254 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors_with_csr_rw.480812254
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_errors.1929548111
Short name	T921
Test name
Test status
Simulation time	73232890 ps
CPU time	1.94 seconds
Started	Sep 11 06:09:00 AM UTC 24
Finished	Sep 11 06:09:03 AM UTC 24
Peak memory	231248 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929548111 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1929548111
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_intg_err.1995014072
Short name	T162
Test name
Test status
Simulation time	180043288 ps
CPU time	4.89 seconds
Started	Sep 11 06:09:01 AM UTC 24
Finished	Sep 11 06:09:07 AM UTC 24
Peak memory	226144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995014072 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.1995014072
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.681988392
Short name	T987
Test name
Test status
Simulation time	49924938 ps
CPU time	1.84 seconds
Started	Sep 11 06:10:05 AM UTC 24
Finished	Sep 11 06:10:08 AM UTC 24
Peak memory	223820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=681988392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_mem_rw_w ith_rand_reset.681988392
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_rw.3812369767
Short name	T985
Test name
Test status
Simulation time	14070970 ps
CPU time	1.33 seconds
Started	Sep 11 06:10:04 AM UTC 24
Finished	Sep 11 06:10:06 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812369767 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3812369767
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_intr_test.968106744
Short name	T984
Test name
Test status
Simulation time	40422011 ps
CPU time	0.9 seconds
Started	Sep 11 06:10:03 AM UTC 24
Finished	Sep 11 06:10:05 AM UTC 24
Peak memory	213116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968106744 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.968106744
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2284177742
Short name	T986
Test name
Test status
Simulation time	49356471 ps
CPU time	1.82 seconds
Started	Sep 11 06:10:04 AM UTC 24
Finished	Sep 11 06:10:07 AM UTC 24
Peak memory	216252 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284177742 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_same_csr_outstanding.2284177742
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3525569105
Short name	T981
Test name
Test status
Simulation time	1198583009 ps
CPU time	3.24 seconds
Started	Sep 11 06:09:59 AM UTC 24
Finished	Sep 11 06:10:04 AM UTC 24
Peak memory	226508 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525569105 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors.3525569105
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2775232118
Short name	T991
Test name
Test status
Simulation time	207937004 ps
CPU time	8.37 seconds
Started	Sep 11 06:10:00 AM UTC 24
Finished	Sep 11 06:10:10 AM UTC 24
Peak memory	226720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775232118 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors_with_csr_rw.2775232118
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_errors.2649885279
Short name	T983
Test name
Test status
Simulation time	81605557 ps
CPU time	1.78 seconds
Started	Sep 11 06:10:01 AM UTC 24
Finished	Sep 11 06:10:04 AM UTC 24
Peak memory	223820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649885279 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2649885279
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3075050039
Short name	T995
Test name
Test status
Simulation time	23474410 ps
CPU time	1.7 seconds
Started	Sep 11 06:10:11 AM UTC 24
Finished	Sep 11 06:10:14 AM UTC 24
Peak memory	226200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3075050039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_mem_rw_ with_rand_reset.3075050039
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_rw.4215148510
Short name	T993
Test name
Test status
Simulation time	29774119 ps
CPU time	1.06 seconds
Started	Sep 11 06:10:08 AM UTC 24
Finished	Sep 11 06:10:10 AM UTC 24
Peak memory	213116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215148510 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.4215148510
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_intr_test.2856231858
Short name	T989
Test name
Test status
Simulation time	117483752 ps
CPU time	0.85 seconds
Started	Sep 11 06:10:07 AM UTC 24
Finished	Sep 11 06:10:09 AM UTC 24
Peak memory	213120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856231858 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2856231858
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3801489587
Short name	T994
Test name
Test status
Simulation time	187197805 ps
CPU time	1.99 seconds
Started	Sep 11 06:10:09 AM UTC 24
Finished	Sep 11 06:10:12 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801489587 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_same_csr_outstanding.3801489587
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2325030671
Short name	T988
Test name
Test status
Simulation time	237904112 ps
CPU time	2.36 seconds
Started	Sep 11 06:10:05 AM UTC 24
Finished	Sep 11 06:10:08 AM UTC 24
Peak memory	226480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325030671 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors.2325030671
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2655714520
Short name	T1003
Test name
Test status
Simulation time	1824230213 ps
CPU time	12.87 seconds
Started	Sep 11 06:10:05 AM UTC 24
Finished	Sep 11 06:10:19 AM UTC 24
Peak memory	232636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655714520 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors_with_csr_rw.2655714520
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_errors.1577372346
Short name	T990
Test name
Test status
Simulation time	374371930 ps
CPU time	3.27 seconds
Started	Sep 11 06:10:05 AM UTC 24
Finished	Sep 11 06:10:09 AM UTC 24
Peak memory	226076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577372346 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1577372346
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2194771328
Short name	T1001
Test name
Test status
Simulation time	60127212 ps
CPU time	2.44 seconds
Started	Sep 11 06:10:14 AM UTC 24
Finished	Sep 11 06:10:18 AM UTC 24
Peak memory	226200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2194771328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_mem_rw_ with_rand_reset.2194771328
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_rw.3841971147
Short name	T998
Test name
Test status
Simulation time	17546178 ps
CPU time	1.42 seconds
Started	Sep 11 06:10:13 AM UTC 24
Finished	Sep 11 06:10:16 AM UTC 24
Peak memory	213116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841971147 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3841971147
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_intr_test.3003731875
Short name	T997
Test name
Test status
Simulation time	14268187 ps
CPU time	0.91 seconds
Started	Sep 11 06:10:13 AM UTC 24
Finished	Sep 11 06:10:15 AM UTC 24
Peak memory	213580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003731875 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3003731875
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3964369610
Short name	T1000
Test name
Test status
Simulation time	62372708 ps
CPU time	2.27 seconds
Started	Sep 11 06:10:14 AM UTC 24
Finished	Sep 11 06:10:18 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964369610 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_same_csr_outstanding.3964369610
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3187875408
Short name	T1002
Test name
Test status
Simulation time	942391147 ps
CPU time	6.22 seconds
Started	Sep 11 06:10:11 AM UTC 24
Finished	Sep 11 06:10:18 AM UTC 24
Peak memory	226536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187875408 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors.3187875408
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2766939711
Short name	T1015
Test name
Test status
Simulation time	801682503 ps
CPU time	15.46 seconds
Started	Sep 11 06:10:11 AM UTC 24
Finished	Sep 11 06:10:28 AM UTC 24
Peak memory	226552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766939711 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors_with_csr_rw.2766939711
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_errors.4111654368
Short name	T996
Test name
Test status
Simulation time	78680416 ps
CPU time	1.91 seconds
Started	Sep 11 06:10:11 AM UTC 24
Finished	Sep 11 06:10:14 AM UTC 24
Peak memory	223820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111654368 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.4111654368
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_intg_err.1567080171
Short name	T173
Test name
Test status
Simulation time	51941027 ps
CPU time	3.62 seconds
Started	Sep 11 06:10:11 AM UTC 24
Finished	Sep 11 06:10:16 AM UTC 24
Peak memory	226160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567080171 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err.1567080171
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2135045253
Short name	T1008
Test name
Test status
Simulation time	92316190 ps
CPU time	1.69 seconds
Started	Sep 11 06:10:19 AM UTC 24
Finished	Sep 11 06:10:22 AM UTC 24
Peak memory	223816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2135045253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_mem_rw_ with_rand_reset.2135045253
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_rw.4128126490
Short name	T1006
Test name
Test status
Simulation time	17287048 ps
CPU time	1.04 seconds
Started	Sep 11 06:10:19 AM UTC 24
Finished	Sep 11 06:10:21 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128126490 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.4128126490
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_intr_test.3902585492
Short name	T1005
Test name
Test status
Simulation time	176496916 ps
CPU time	0.88 seconds
Started	Sep 11 06:10:19 AM UTC 24
Finished	Sep 11 06:10:21 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902585492 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3902585492
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4057828576
Short name	T1009
Test name
Test status
Simulation time	38669288 ps
CPU time	1.92 seconds
Started	Sep 11 06:10:19 AM UTC 24
Finished	Sep 11 06:10:22 AM UTC 24
Peak memory	216220 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057828576 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_same_csr_outstanding.4057828576
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3491225593
Short name	T999
Test name
Test status
Simulation time	156803591 ps
CPU time	2.19 seconds
Started	Sep 11 06:10:14 AM UTC 24
Finished	Sep 11 06:10:18 AM UTC 24
Peak memory	226504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491225593 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors.3491225593
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1429934789
Short name	T1018
Test name
Test status
Simulation time	3032071275 ps
CPU time	12.34 seconds
Started	Sep 11 06:10:16 AM UTC 24
Finished	Sep 11 06:10:29 AM UTC 24
Peak memory	226916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429934789 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors_with_csr_rw.1429934789
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_errors.1544162598
Short name	T1007
Test name
Test status
Simulation time	50710079 ps
CPU time	4.05 seconds
Started	Sep 11 06:10:17 AM UTC 24
Finished	Sep 11 06:10:22 AM UTC 24
Peak memory	228212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544162598 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1544162598
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.3982480131
Short name	T1004
Test name
Test status
Simulation time	79025475 ps
CPU time	2.95 seconds
Started	Sep 11 06:10:17 AM UTC 24
Finished	Sep 11 06:10:21 AM UTC 24
Peak memory	226148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982480131 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err.3982480131
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.785382226
Short name	T1019
Test name
Test status
Simulation time	615416911 ps
CPU time	1.97 seconds
Started	Sep 11 06:10:26 AM UTC 24
Finished	Sep 11 06:10:29 AM UTC 24
Peak memory	223820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=785382226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_mem_rw_w ith_rand_reset.785382226
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.1213087595
Short name	T1013
Test name
Test status
Simulation time	21296588 ps
CPU time	1.2 seconds
Started	Sep 11 06:10:23 AM UTC 24
Finished	Sep 11 06:10:25 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213087595 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1213087595
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.1209163633
Short name	T1012
Test name
Test status
Simulation time	33649750 ps
CPU time	0.88 seconds
Started	Sep 11 06:10:23 AM UTC 24
Finished	Sep 11 06:10:25 AM UTC 24
Peak memory	213580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209163633 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1209163633
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.456099696
Short name	T1014
Test name
Test status
Simulation time	300869520 ps
CPU time	2.75 seconds
Started	Sep 11 06:10:23 AM UTC 24
Finished	Sep 11 06:10:27 AM UTC 24
Peak memory	216156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456099696 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_same_csr_outstanding.456099696
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3116897313
Short name	T1011
Test name
Test status
Simulation time	91760209 ps
CPU time	3.49 seconds
Started	Sep 11 06:10:20 AM UTC 24
Finished	Sep 11 06:10:25 AM UTC 24
Peak memory	226480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116897313 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors.3116897313
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1455872558
Short name	T1016
Test name
Test status
Simulation time	738565846 ps
CPU time	5.19 seconds
Started	Sep 11 06:10:22 AM UTC 24
Finished	Sep 11 06:10:28 AM UTC 24
Peak memory	226476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455872558 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors_with_csr_rw.1455872558
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.3273388338
Short name	T1010
Test name
Test status
Simulation time	57365359 ps
CPU time	2.1 seconds
Started	Sep 11 06:10:22 AM UTC 24
Finished	Sep 11 06:10:25 AM UTC 24
Peak memory	226428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273388338 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3273388338
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.3882914363
Short name	T1017
Test name
Test status
Simulation time	2494627858 ps
CPU time	5.64 seconds
Started	Sep 11 06:10:22 AM UTC 24
Finished	Sep 11 06:10:28 AM UTC 24
Peak memory	226532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882914363 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err.3882914363
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1825866763
Short name	T1024
Test name
Test status
Simulation time	48258368 ps
CPU time	1.2 seconds
Started	Sep 11 06:10:30 AM UTC 24
Finished	Sep 11 06:10:32 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1825866763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_mem_rw_ with_rand_reset.1825866763
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.885588211
Short name	T1023
Test name
Test status
Simulation time	98728934 ps
CPU time	1.68 seconds
Started	Sep 11 06:10:29 AM UTC 24
Finished	Sep 11 06:10:31 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885588211 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.885588211
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.277940153
Short name	T1022
Test name
Test status
Simulation time	11209537 ps
CPU time	0.93 seconds
Started	Sep 11 06:10:29 AM UTC 24
Finished	Sep 11 06:10:31 AM UTC 24
Peak memory	213116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277940153 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.277940153
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3336907001
Short name	T1025
Test name
Test status
Simulation time	39475395 ps
CPU time	3.05 seconds
Started	Sep 11 06:10:29 AM UTC 24
Finished	Sep 11 06:10:33 AM UTC 24
Peak memory	226404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336907001 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_same_csr_outstanding.3336907001
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1413334197
Short name	T1021
Test name
Test status
Simulation time	188729509 ps
CPU time	3.38 seconds
Started	Sep 11 06:10:26 AM UTC 24
Finished	Sep 11 06:10:31 AM UTC 24
Peak memory	226408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413334197 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors.1413334197
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.985524869
Short name	T1026
Test name
Test status
Simulation time	125705031 ps
CPU time	6.67 seconds
Started	Sep 11 06:10:26 AM UTC 24
Finished	Sep 11 06:10:34 AM UTC 24
Peak memory	226428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985524869 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors_with_csr_rw.985524869
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.1412339148
Short name	T1020
Test name
Test status
Simulation time	48078928 ps
CPU time	3.03 seconds
Started	Sep 11 06:10:26 AM UTC 24
Finished	Sep 11 06:10:30 AM UTC 24
Peak memory	232540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412339148 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1412339148
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.708855973
Short name	T175
Test name
Test status
Simulation time	333507582 ps
CPU time	3.98 seconds
Started	Sep 11 06:10:27 AM UTC 24
Finished	Sep 11 06:10:33 AM UTC 24
Peak memory	226072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708855973 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err.708855973
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1014237491
Short name	T1031
Test name
Test status
Simulation time	146621095 ps
CPU time	1.69 seconds
Started	Sep 11 06:10:34 AM UTC 24
Finished	Sep 11 06:10:36 AM UTC 24
Peak memory	223816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1014237491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_mem_rw_ with_rand_reset.1014237491
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.1672509533
Short name	T1030
Test name
Test status
Simulation time	40131706 ps
CPU time	1.47 seconds
Started	Sep 11 06:10:34 AM UTC 24
Finished	Sep 11 06:10:36 AM UTC 24
Peak memory	213116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672509533 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1672509533
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.2104736439
Short name	T1027
Test name
Test status
Simulation time	65352956 ps
CPU time	0.88 seconds
Started	Sep 11 06:10:33 AM UTC 24
Finished	Sep 11 06:10:34 AM UTC 24
Peak memory	213580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104736439 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2104736439
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3633631145
Short name	T1035
Test name
Test status
Simulation time	112182101 ps
CPU time	4.36 seconds
Started	Sep 11 06:10:34 AM UTC 24
Finished	Sep 11 06:10:39 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633631145 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_same_csr_outstanding.3633631145
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3640094763
Short name	T1028
Test name
Test status
Simulation time	716654593 ps
CPU time	4.16 seconds
Started	Sep 11 06:10:30 AM UTC 24
Finished	Sep 11 06:10:35 AM UTC 24
Peak memory	226504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640094763 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors.3640094763
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2369940115
Short name	T1033
Test name
Test status
Simulation time	215646272 ps
CPU time	5.57 seconds
Started	Sep 11 06:10:31 AM UTC 24
Finished	Sep 11 06:10:38 AM UTC 24
Peak memory	226404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369940115 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors_with_csr_rw.2369940115
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.203192953
Short name	T1029
Test name
Test status
Simulation time	45711632 ps
CPU time	3.77 seconds
Started	Sep 11 06:10:31 AM UTC 24
Finished	Sep 11 06:10:36 AM UTC 24
Peak memory	225816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203192953 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.203192953
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2713925050
Short name	T1040
Test name
Test status
Simulation time	41615594 ps
CPU time	2.02 seconds
Started	Sep 11 06:10:39 AM UTC 24
Finished	Sep 11 06:10:42 AM UTC 24
Peak memory	226328 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2713925050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_mem_rw_ with_rand_reset.2713925050
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.362383518
Short name	T1034
Test name
Test status
Simulation time	101087683 ps
CPU time	1.36 seconds
Started	Sep 11 06:10:38 AM UTC 24
Finished	Sep 11 06:10:40 AM UTC 24
Peak memory	213116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362383518 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.362383518
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.4141270342
Short name	T1036
Test name
Test status
Simulation time	13997892 ps
CPU time	1.01 seconds
Started	Sep 11 06:10:38 AM UTC 24
Finished	Sep 11 06:10:40 AM UTC 24
Peak memory	213580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141270342 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.4141270342
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.4120717142
Short name	T1037
Test name
Test status
Simulation time	45953634 ps
CPU time	1.95 seconds
Started	Sep 11 06:10:38 AM UTC 24
Finished	Sep 11 06:10:41 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120717142 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_same_csr_outstanding.4120717142
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3641592853
Short name	T1032
Test name
Test status
Simulation time	111243623 ps
CPU time	2.02 seconds
Started	Sep 11 06:10:35 AM UTC 24
Finished	Sep 11 06:10:38 AM UTC 24
Peak memory	226672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641592853 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors.3641592853
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.135879630
Short name	T1050
Test name
Test status
Simulation time	1399673268 ps
CPU time	14.63 seconds
Started	Sep 11 06:10:35 AM UTC 24
Finished	Sep 11 06:10:51 AM UTC 24
Peak memory	232620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135879630 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors_with_csr_rw.135879630
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.4017528156
Short name	T1038
Test name
Test status
Simulation time	92009365 ps
CPU time	3.6 seconds
Started	Sep 11 06:10:36 AM UTC 24
Finished	Sep 11 06:10:41 AM UTC 24
Peak memory	226148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017528156 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.4017528156
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1607144766
Short name	T1044
Test name
Test status
Simulation time	26533057 ps
CPU time	1.97 seconds
Started	Sep 11 06:10:43 AM UTC 24
Finished	Sep 11 06:10:46 AM UTC 24
Peak memory	223816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1607144766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_mem_rw_ with_rand_reset.1607144766
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.2548481087
Short name	T1043
Test name
Test status
Simulation time	46075107 ps
CPU time	1.72 seconds
Started	Sep 11 06:10:42 AM UTC 24
Finished	Sep 11 06:10:44 AM UTC 24
Peak memory	213116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548481087 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2548481087
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.1224384322
Short name	T1041
Test name
Test status
Simulation time	8131187 ps
CPU time	1.03 seconds
Started	Sep 11 06:10:42 AM UTC 24
Finished	Sep 11 06:10:43 AM UTC 24
Peak memory	213580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224384322 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1224384322
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3749825662
Short name	T1045
Test name
Test status
Simulation time	222682263 ps
CPU time	3.54 seconds
Started	Sep 11 06:10:43 AM UTC 24
Finished	Sep 11 06:10:47 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749825662 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_same_csr_outstanding.3749825662
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3739463414
Short name	T1039
Test name
Test status
Simulation time	421791117 ps
CPU time	1.95 seconds
Started	Sep 11 06:10:39 AM UTC 24
Finished	Sep 11 06:10:42 AM UTC 24
Peak memory	226756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739463414 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors.3739463414
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1278088314
Short name	T1048
Test name
Test status
Simulation time	1235624326 ps
CPU time	7.37 seconds
Started	Sep 11 06:10:40 AM UTC 24
Finished	Sep 11 06:10:49 AM UTC 24
Peak memory	226732 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278088314 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors_with_csr_rw.1278088314
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.1399156622
Short name	T1042
Test name
Test status
Simulation time	246143562 ps
CPU time	2.68 seconds
Started	Sep 11 06:10:40 AM UTC 24
Finished	Sep 11 06:10:44 AM UTC 24
Peak memory	226172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399156622 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1399156622
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.3313742002
Short name	T170
Test name
Test status
Simulation time	539203324 ps
CPU time	6.33 seconds
Started	Sep 11 06:10:41 AM UTC 24
Finished	Sep 11 06:10:49 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313742002 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err.3313742002
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3628016307
Short name	T1052
Test name
Test status
Simulation time	39560932 ps
CPU time	1.68 seconds
Started	Sep 11 06:10:49 AM UTC 24
Finished	Sep 11 06:10:51 AM UTC 24
Peak memory	226240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3628016307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_mem_rw_ with_rand_reset.3628016307
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.3362959652
Short name	T1051
Test name
Test status
Simulation time	45164254 ps
CPU time	1.28 seconds
Started	Sep 11 06:10:49 AM UTC 24
Finished	Sep 11 06:10:51 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362959652 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3362959652
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.1429610910
Short name	T1047
Test name
Test status
Simulation time	83491869 ps
CPU time	0.9 seconds
Started	Sep 11 06:10:46 AM UTC 24
Finished	Sep 11 06:10:48 AM UTC 24
Peak memory	213580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429610910 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1429610910
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3035058949
Short name	T1060
Test name
Test status
Simulation time	2438101026 ps
CPU time	5.08 seconds
Started	Sep 11 06:10:49 AM UTC 24
Finished	Sep 11 06:10:55 AM UTC 24
Peak memory	216036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035058949 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_same_csr_outstanding.3035058949
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1685881974
Short name	T1046
Test name
Test status
Simulation time	197026594 ps
CPU time	2.63 seconds
Started	Sep 11 06:10:44 AM UTC 24
Finished	Sep 11 06:10:48 AM UTC 24
Peak memory	226528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685881974 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors.1685881974
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3025367809
Short name	T1081
Test name
Test status
Simulation time	1645624734 ps
CPU time	15.26 seconds
Started	Sep 11 06:10:45 AM UTC 24
Finished	Sep 11 06:11:02 AM UTC 24
Peak memory	232620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025367809 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors_with_csr_rw.3025367809
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.3576608609
Short name	T1049
Test name
Test status
Simulation time	387491646 ps
CPU time	2.77 seconds
Started	Sep 11 06:10:45 AM UTC 24
Finished	Sep 11 06:10:49 AM UTC 24
Peak memory	226236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576608609 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3576608609
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.3671018412
Short name	T1054
Test name
Test status
Simulation time	439434628 ps
CPU time	4.54 seconds
Started	Sep 11 06:10:46 AM UTC 24
Finished	Sep 11 06:10:52 AM UTC 24
Peak memory	226340 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671018412 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err.3671018412
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_aliasing.815144549
Short name	T124
Test name
Test status
Simulation time	135198223 ps
CPU time	4.27 seconds
Started	Sep 11 06:09:16 AM UTC 24
Finished	Sep 11 06:09:22 AM UTC 24
Peak memory	215956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815144549 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.815144549
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_bit_bash.522576226
Short name	T934
Test name
Test status
Simulation time	535678214 ps
CPU time	8.36 seconds
Started	Sep 11 06:09:16 AM UTC 24
Finished	Sep 11 06:09:26 AM UTC 24
Peak memory	215960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522576226 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.522576226
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2846350193
Short name	T927
Test name
Test status
Simulation time	44064152 ps
CPU time	1.09 seconds
Started	Sep 11 06:09:14 AM UTC 24
Finished	Sep 11 06:09:16 AM UTC 24
Peak memory	213648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846350193 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2846350193
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1536972435
Short name	T929
Test name
Test status
Simulation time	78862849 ps
CPU time	1.73 seconds
Started	Sep 11 06:09:19 AM UTC 24
Finished	Sep 11 06:09:21 AM UTC 24
Peak memory	228276 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1536972435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_mem_rw_w ith_rand_reset.1536972435
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_rw.1453820170
Short name	T122
Test name
Test status
Simulation time	16366500 ps
CPU time	1.26 seconds
Started	Sep 11 06:09:15 AM UTC 24
Finished	Sep 11 06:09:18 AM UTC 24
Peak memory	213116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453820170 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1453820170
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_intr_test.4276859988
Short name	T926
Test name
Test status
Simulation time	30847595 ps
CPU time	0.97 seconds
Started	Sep 11 06:09:13 AM UTC 24
Finished	Sep 11 06:09:15 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276859988 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.4276859988
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3929871095
Short name	T123
Test name
Test status
Simulation time	98317268 ps
CPU time	2.49 seconds
Started	Sep 11 06:09:17 AM UTC 24
Finished	Sep 11 06:09:21 AM UTC 24
Peak memory	216164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929871095 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_same_csr_outstanding.3929871095
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1370883558
Short name	T87
Test name
Test status
Simulation time	270290415 ps
CPU time	4.32 seconds
Started	Sep 11 06:09:10 AM UTC 24
Finished	Sep 11 06:09:15 AM UTC 24
Peak memory	226544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370883558 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors.1370883558
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.4008591272
Short name	T83
Test name
Test status
Simulation time	1348974150 ps
CPU time	14.07 seconds
Started	Sep 11 06:09:11 AM UTC 24
Finished	Sep 11 06:09:26 AM UTC 24
Peak memory	226736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008591272 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors_with_csr_rw.4008591272
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_errors.3932279298
Short name	T928
Test name
Test status
Simulation time	508258137 ps
CPU time	5.51 seconds
Started	Sep 11 06:09:12 AM UTC 24
Finished	Sep 11 06:09:19 AM UTC 24
Peak memory	228244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932279298 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3932279298
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.46345170
Short name	T1053
Test name
Test status
Simulation time	7243067 ps
CPU time	0.85 seconds
Started	Sep 11 06:10:50 AM UTC 24
Finished	Sep 11 06:10:52 AM UTC 24
Peak memory	213572 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46345170 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.46345170
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/20.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.3682477526
Short name	T1055
Test name
Test status
Simulation time	6745990 ps
CPU time	0.94 seconds
Started	Sep 11 06:10:50 AM UTC 24
Finished	Sep 11 06:10:52 AM UTC 24
Peak memory	213096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682477526 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3682477526
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/21.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.1762425994
Short name	T1056
Test name
Test status
Simulation time	105925387 ps
CPU time	0.93 seconds
Started	Sep 11 06:10:50 AM UTC 24
Finished	Sep 11 06:10:52 AM UTC 24
Peak memory	213120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762425994 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1762425994
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/22.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.3106151418
Short name	T1057
Test name
Test status
Simulation time	44644208 ps
CPU time	0.91 seconds
Started	Sep 11 06:10:51 AM UTC 24
Finished	Sep 11 06:10:53 AM UTC 24
Peak memory	213580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106151418 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3106151418
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/23.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.2170776258
Short name	T1058
Test name
Test status
Simulation time	45761806 ps
CPU time	1.04 seconds
Started	Sep 11 06:10:51 AM UTC 24
Finished	Sep 11 06:10:54 AM UTC 24
Peak memory	213580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170776258 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2170776258
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/24.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.3122098079
Short name	T1059
Test name
Test status
Simulation time	33952716 ps
CPU time	0.91 seconds
Started	Sep 11 06:10:53 AM UTC 24
Finished	Sep 11 06:10:55 AM UTC 24
Peak memory	213540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122098079 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3122098079
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/25.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.3096811350
Short name	T1062
Test name
Test status
Simulation time	15308828 ps
CPU time	1.11 seconds
Started	Sep 11 06:10:53 AM UTC 24
Finished	Sep 11 06:10:55 AM UTC 24
Peak memory	213472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096811350 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3096811350
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/26.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.1743382690
Short name	T1061
Test name
Test status
Simulation time	11217213 ps
CPU time	0.93 seconds
Started	Sep 11 06:10:53 AM UTC 24
Finished	Sep 11 06:10:55 AM UTC 24
Peak memory	213504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743382690 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1743382690
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/27.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.3594884900
Short name	T1063
Test name
Test status
Simulation time	21022213 ps
CPU time	1.03 seconds
Started	Sep 11 06:10:53 AM UTC 24
Finished	Sep 11 06:10:55 AM UTC 24
Peak memory	213580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594884900 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3594884900
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/28.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.3612260799
Short name	T1064
Test name
Test status
Simulation time	42457917 ps
CPU time	1.03 seconds
Started	Sep 11 06:10:53 AM UTC 24
Finished	Sep 11 06:10:55 AM UTC 24
Peak memory	213580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612260799 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3612260799
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/29.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_aliasing.4250761878
Short name	T944
Test name
Test status
Simulation time	255132217 ps
CPU time	8.52 seconds
Started	Sep 11 06:09:24 AM UTC 24
Finished	Sep 11 06:09:34 AM UTC 24
Peak memory	215868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250761878 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.4250761878
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_bit_bash.4155096336
Short name	T943
Test name
Test status
Simulation time	135654576 ps
CPU time	7.59 seconds
Started	Sep 11 06:09:24 AM UTC 24
Finished	Sep 11 06:09:33 AM UTC 24
Peak memory	215836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155096336 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.4155096336
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2019290213
Short name	T933
Test name
Test status
Simulation time	71508291 ps
CPU time	1.38 seconds
Started	Sep 11 06:09:23 AM UTC 24
Finished	Sep 11 06:09:25 AM UTC 24
Peak memory	213648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019290213 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2019290213
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.4132243092
Short name	T937
Test name
Test status
Simulation time	137959208 ps
CPU time	1.68 seconds
Started	Sep 11 06:09:26 AM UTC 24
Finished	Sep 11 06:09:29 AM UTC 24
Peak memory	223816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4132243092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_mem_rw_w ith_rand_reset.4132243092
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_rw.3874267672
Short name	T935
Test name
Test status
Simulation time	291726123 ps
CPU time	1.91 seconds
Started	Sep 11 06:09:24 AM UTC 24
Finished	Sep 11 06:09:27 AM UTC 24
Peak memory	213108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874267672 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3874267672
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_intr_test.2245047463
Short name	T931
Test name
Test status
Simulation time	82175472 ps
CPU time	0.87 seconds
Started	Sep 11 06:09:22 AM UTC 24
Finished	Sep 11 06:09:24 AM UTC 24
Peak memory	213572 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245047463 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2245047463
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.577176415
Short name	T936
Test name
Test status
Simulation time	58193016 ps
CPU time	2.01 seconds
Started	Sep 11 06:09:25 AM UTC 24
Finished	Sep 11 06:09:28 AM UTC 24
Peak memory	215996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577176415 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_same_csr_outstanding.577176415
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3422541379
Short name	T88
Test name
Test status
Simulation time	335138019 ps
CPU time	3.11 seconds
Started	Sep 11 06:09:20 AM UTC 24
Finished	Sep 11 06:09:24 AM UTC 24
Peak memory	226544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422541379 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors.3422541379
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3127632638
Short name	T89
Test name
Test status
Simulation time	2526846845 ps
CPU time	9.5 seconds
Started	Sep 11 06:09:21 AM UTC 24
Finished	Sep 11 06:09:31 AM UTC 24
Peak memory	226800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127632638 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors_with_csr_rw.3127632638
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_errors.1228519494
Short name	T932
Test name
Test status
Simulation time	101268577 ps
CPU time	2.12 seconds
Started	Sep 11 06:09:21 AM UTC 24
Finished	Sep 11 06:09:24 AM UTC 24
Peak memory	226428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228519494 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1228519494
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_intg_err.954239642
Short name	T938
Test name
Test status
Simulation time	188561199 ps
CPU time	6.36 seconds
Started	Sep 11 06:09:22 AM UTC 24
Finished	Sep 11 06:09:29 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954239642 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.954239642
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.3639168194
Short name	T1065
Test name
Test status
Simulation time	53466090 ps
CPU time	0.89 seconds
Started	Sep 11 06:10:54 AM UTC 24
Finished	Sep 11 06:10:56 AM UTC 24
Peak memory	213568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639168194 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3639168194
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/30.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.2977266096
Short name	T1066
Test name
Test status
Simulation time	152543891 ps
CPU time	0.96 seconds
Started	Sep 11 06:10:54 AM UTC 24
Finished	Sep 11 06:10:56 AM UTC 24
Peak memory	213120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977266096 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2977266096
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/31.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.801144049
Short name	T1067
Test name
Test status
Simulation time	43841628 ps
CPU time	0.93 seconds
Started	Sep 11 06:10:56 AM UTC 24
Finished	Sep 11 06:10:58 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801144049 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.801144049
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/32.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.2913029521
Short name	T1068
Test name
Test status
Simulation time	14340298 ps
CPU time	0.93 seconds
Started	Sep 11 06:10:56 AM UTC 24
Finished	Sep 11 06:10:58 AM UTC 24
Peak memory	213580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913029521 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2913029521
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/33.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.3018094407
Short name	T1071
Test name
Test status
Simulation time	18308720 ps
CPU time	0.97 seconds
Started	Sep 11 06:10:56 AM UTC 24
Finished	Sep 11 06:10:58 AM UTC 24
Peak memory	213120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018094407 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3018094407
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/34.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.544824243
Short name	T1072
Test name
Test status
Simulation time	13886829 ps
CPU time	1.11 seconds
Started	Sep 11 06:10:56 AM UTC 24
Finished	Sep 11 06:10:58 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544824243 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.544824243
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/35.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.1022532830
Short name	T1069
Test name
Test status
Simulation time	38585917 ps
CPU time	0.87 seconds
Started	Sep 11 06:10:56 AM UTC 24
Finished	Sep 11 06:10:58 AM UTC 24
Peak memory	213580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022532830 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1022532830
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/36.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.2346393689
Short name	T1070
Test name
Test status
Simulation time	106550938 ps
CPU time	0.86 seconds
Started	Sep 11 06:10:56 AM UTC 24
Finished	Sep 11 06:10:58 AM UTC 24
Peak memory	213580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346393689 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2346393689
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/37.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.1828075463
Short name	T1074
Test name
Test status
Simulation time	11380066 ps
CPU time	0.98 seconds
Started	Sep 11 06:10:57 AM UTC 24
Finished	Sep 11 06:10:59 AM UTC 24
Peak memory	213520 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828075463 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1828075463
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/38.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.2551420506
Short name	T1073
Test name
Test status
Simulation time	80388388 ps
CPU time	0.9 seconds
Started	Sep 11 06:10:57 AM UTC 24
Finished	Sep 11 06:10:59 AM UTC 24
Peak memory	213040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551420506 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2551420506
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/39.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_aliasing.2733662386
Short name	T949
Test name
Test status
Simulation time	196314673 ps
CPU time	5.29 seconds
Started	Sep 11 06:09:32 AM UTC 24
Finished	Sep 11 06:09:38 AM UTC 24
Peak memory	216156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733662386 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2733662386
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3723191855
Short name	T954
Test name
Test status
Simulation time	139265253 ps
CPU time	8.51 seconds
Started	Sep 11 06:09:32 AM UTC 24
Finished	Sep 11 06:09:42 AM UTC 24
Peak memory	216036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723191855 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3723191855
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_hw_reset.215842541
Short name	T942
Test name
Test status
Simulation time	38041059 ps
CPU time	1.41 seconds
Started	Sep 11 06:09:30 AM UTC 24
Finished	Sep 11 06:09:32 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215842541 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.215842541
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3465422268
Short name	T946
Test name
Test status
Simulation time	115296365 ps
CPU time	1.49 seconds
Started	Sep 11 06:09:33 AM UTC 24
Finished	Sep 11 06:09:36 AM UTC 24
Peak memory	223816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3465422268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_mem_rw_w ith_rand_reset.3465422268
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_rw.2999797632
Short name	T945
Test name
Test status
Simulation time	97559746 ps
CPU time	1.41 seconds
Started	Sep 11 06:09:32 AM UTC 24
Finished	Sep 11 06:09:34 AM UTC 24
Peak memory	213116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999797632 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2999797632
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_intr_test.3676762757
Short name	T941
Test name
Test status
Simulation time	13697123 ps
CPU time	1.11 seconds
Started	Sep 11 06:09:30 AM UTC 24
Finished	Sep 11 06:09:32 AM UTC 24
Peak memory	213116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676762757 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3676762757
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1249970385
Short name	T947
Test name
Test status
Simulation time	436680904 ps
CPU time	2.15 seconds
Started	Sep 11 06:09:33 AM UTC 24
Finished	Sep 11 06:09:36 AM UTC 24
Peak memory	215860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249970385 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_same_csr_outstanding.1249970385
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2160630503
Short name	T92
Test name
Test status
Simulation time	191995215 ps
CPU time	3.25 seconds
Started	Sep 11 06:09:26 AM UTC 24
Finished	Sep 11 06:09:30 AM UTC 24
Peak memory	226800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160630503 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors.2160630503
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.679976815
Short name	T948
Test name
Test status
Simulation time	281965802 ps
CPU time	9.22 seconds
Started	Sep 11 06:09:27 AM UTC 24
Finished	Sep 11 06:09:38 AM UTC 24
Peak memory	230448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679976815 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors_with_csr_rw.679976815
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_errors.2714733521
Short name	T940
Test name
Test status
Simulation time	441058395 ps
CPU time	2.77 seconds
Started	Sep 11 06:09:27 AM UTC 24
Finished	Sep 11 06:09:31 AM UTC 24
Peak memory	226032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714733521 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2714733521
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_intg_err.3614478939
Short name	T163
Test name
Test status
Simulation time	411338081 ps
CPU time	5.85 seconds
Started	Sep 11 06:09:28 AM UTC 24
Finished	Sep 11 06:09:36 AM UTC 24
Peak memory	226336 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614478939 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.3614478939
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.2029055391
Short name	T1075
Test name
Test status
Simulation time	47213558 ps
CPU time	0.87 seconds
Started	Sep 11 06:10:59 AM UTC 24
Finished	Sep 11 06:11:01 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029055391 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2029055391
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/40.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.618599904
Short name	T1077
Test name
Test status
Simulation time	27006519 ps
CPU time	0.98 seconds
Started	Sep 11 06:10:59 AM UTC 24
Finished	Sep 11 06:11:01 AM UTC 24
Peak memory	213116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618599904 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.618599904
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/41.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.3969716986
Short name	T1076
Test name
Test status
Simulation time	24643416 ps
CPU time	0.88 seconds
Started	Sep 11 06:10:59 AM UTC 24
Finished	Sep 11 06:11:01 AM UTC 24
Peak memory	213120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969716986 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3969716986
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/42.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.3337189590
Short name	T1078
Test name
Test status
Simulation time	11213983 ps
CPU time	0.9 seconds
Started	Sep 11 06:10:59 AM UTC 24
Finished	Sep 11 06:11:01 AM UTC 24
Peak memory	213120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337189590 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3337189590
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/43.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.1317442839
Short name	T1079
Test name
Test status
Simulation time	27504698 ps
CPU time	0.9 seconds
Started	Sep 11 06:10:59 AM UTC 24
Finished	Sep 11 06:11:01 AM UTC 24
Peak memory	213580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317442839 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1317442839
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/44.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.1794234074
Short name	T1080
Test name
Test status
Simulation time	24317154 ps
CPU time	1.14 seconds
Started	Sep 11 06:10:59 AM UTC 24
Finished	Sep 11 06:11:01 AM UTC 24
Peak memory	213120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794234074 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1794234074
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/45.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.224344104
Short name	T1083
Test name
Test status
Simulation time	27297380 ps
CPU time	0.96 seconds
Started	Sep 11 06:11:00 AM UTC 24
Finished	Sep 11 06:11:02 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224344104 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.224344104
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/46.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.1308382668
Short name	T1082
Test name
Test status
Simulation time	12040380 ps
CPU time	0.9 seconds
Started	Sep 11 06:11:00 AM UTC 24
Finished	Sep 11 06:11:02 AM UTC 24
Peak memory	213580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308382668 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1308382668
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/47.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.696017059
Short name	T1085
Test name
Test status
Simulation time	13261490 ps
CPU time	1.1 seconds
Started	Sep 11 06:11:02 AM UTC 24
Finished	Sep 11 06:11:04 AM UTC 24
Peak memory	213116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696017059 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.696017059
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/48.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.2668701062
Short name	T1084
Test name
Test status
Simulation time	35408397 ps
CPU time	1.02 seconds
Started	Sep 11 06:11:02 AM UTC 24
Finished	Sep 11 06:11:04 AM UTC 24
Peak memory	213580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668701062 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2668701062
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/49.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1624491619
Short name	T955
Test name
Test status
Simulation time	41374787 ps
CPU time	1.76 seconds
Started	Sep 11 06:09:40 AM UTC 24
Finished	Sep 11 06:09:43 AM UTC 24
Peak memory	213116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1624491619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_mem_rw_w ith_rand_reset.1624491619
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_rw.2785995253
Short name	T952
Test name
Test status
Simulation time	66336241 ps
CPU time	1.4 seconds
Started	Sep 11 06:09:37 AM UTC 24
Finished	Sep 11 06:09:40 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785995253 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2785995253
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_intr_test.1965435667
Short name	T950
Test name
Test status
Simulation time	40164506 ps
CPU time	1.05 seconds
Started	Sep 11 06:09:36 AM UTC 24
Finished	Sep 11 06:09:39 AM UTC 24
Peak memory	213116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965435667 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1965435667
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1694632436
Short name	T953
Test name
Test status
Simulation time	82591825 ps
CPU time	1.58 seconds
Started	Sep 11 06:09:38 AM UTC 24
Finished	Sep 11 06:09:41 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694632436 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_same_csr_outstanding.1694632436
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2911540308
Short name	T90
Test name
Test status
Simulation time	75256203 ps
CPU time	4.39 seconds
Started	Sep 11 06:09:34 AM UTC 24
Finished	Sep 11 06:09:39 AM UTC 24
Peak memory	232580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911540308 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors_with_csr_rw.2911540308
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_errors.931412039
Short name	T951
Test name
Test status
Simulation time	120272551 ps
CPU time	2.54 seconds
Started	Sep 11 06:09:35 AM UTC 24
Finished	Sep 11 06:09:39 AM UTC 24
Peak memory	226136 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931412039 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.931412039
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.645255930
Short name	T959
Test name
Test status
Simulation time	24546452 ps
CPU time	1.89 seconds
Started	Sep 11 06:09:42 AM UTC 24
Finished	Sep 11 06:09:46 AM UTC 24
Peak memory	223820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=645255930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_mem_rw_wi th_rand_reset.645255930
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_rw.1824204547
Short name	T958
Test name
Test status
Simulation time	27480076 ps
CPU time	1.12 seconds
Started	Sep 11 06:09:42 AM UTC 24
Finished	Sep 11 06:09:45 AM UTC 24
Peak memory	213116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824204547 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1824204547
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_intr_test.1123000870
Short name	T957
Test name
Test status
Simulation time	13117296 ps
CPU time	0.88 seconds
Started	Sep 11 06:09:41 AM UTC 24
Finished	Sep 11 06:09:44 AM UTC 24
Peak memory	213568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123000870 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1123000870
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2978429582
Short name	T962
Test name
Test status
Simulation time	350477043 ps
CPU time	4.08 seconds
Started	Sep 11 06:09:42 AM UTC 24
Finished	Sep 11 06:09:48 AM UTC 24
Peak memory	216164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978429582 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_same_csr_outstanding.2978429582
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3301522823
Short name	T956
Test name
Test status
Simulation time	85548946 ps
CPU time	2.16 seconds
Started	Sep 11 06:09:40 AM UTC 24
Finished	Sep 11 06:09:43 AM UTC 24
Peak memory	226512 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301522823 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors.3301522823
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2416587257
Short name	T966
Test name
Test status
Simulation time	1410335308 ps
CPU time	8.24 seconds
Started	Sep 11 06:09:40 AM UTC 24
Finished	Sep 11 06:09:50 AM UTC 24
Peak memory	226672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416587257 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors_with_csr_rw.2416587257
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_errors.3795344617
Short name	T960
Test name
Test status
Simulation time	44085715 ps
CPU time	3.16 seconds
Started	Sep 11 06:09:41 AM UTC 24
Finished	Sep 11 06:09:46 AM UTC 24
Peak memory	228212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795344617 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3795344617
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1353315987
Short name	T967
Test name
Test status
Simulation time	80684028 ps
CPU time	2.41 seconds
Started	Sep 11 06:09:49 AM UTC 24
Finished	Sep 11 06:09:52 AM UTC 24
Peak memory	226380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1353315987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_mem_rw_w ith_rand_reset.1353315987
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_rw.2150924891
Short name	T964
Test name
Test status
Simulation time	26662085 ps
CPU time	1.22 seconds
Started	Sep 11 06:09:47 AM UTC 24
Finished	Sep 11 06:09:49 AM UTC 24
Peak memory	212924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150924891 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2150924891
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_intr_test.3657699895
Short name	T963
Test name
Test status
Simulation time	14165408 ps
CPU time	0.85 seconds
Started	Sep 11 06:09:47 AM UTC 24
Finished	Sep 11 06:09:48 AM UTC 24
Peak memory	215516 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657699895 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3657699895
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.620605519
Short name	T969
Test name
Test status
Simulation time	71325013 ps
CPU time	2.72 seconds
Started	Sep 11 06:09:49 AM UTC 24
Finished	Sep 11 06:09:53 AM UTC 24
Peak memory	216008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620605519 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_same_csr_outstanding.620605519
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1166992552
Short name	T965
Test name
Test status
Simulation time	156368477 ps
CPU time	3.59 seconds
Started	Sep 11 06:09:44 AM UTC 24
Finished	Sep 11 06:09:49 AM UTC 24
Peak memory	226416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166992552 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors.1166992552
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.569162837
Short name	T971
Test name
Test status
Simulation time	338880206 ps
CPU time	9.13 seconds
Started	Sep 11 06:09:44 AM UTC 24
Finished	Sep 11 06:09:55 AM UTC 24
Peak memory	226456 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569162837 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors_with_csr_rw.569162837
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_errors.577699306
Short name	T961
Test name
Test status
Simulation time	76991494 ps
CPU time	1.85 seconds
Started	Sep 11 06:09:44 AM UTC 24
Finished	Sep 11 06:09:47 AM UTC 24
Peak memory	223816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577699306 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.577699306
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_intg_err.2452176766
Short name	T177
Test name
Test status
Simulation time	193533301 ps
CPU time	3.33 seconds
Started	Sep 11 06:09:45 AM UTC 24
Finished	Sep 11 06:09:50 AM UTC 24
Peak memory	226140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452176766 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.2452176766
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.597230482
Short name	T976
Test name
Test status
Simulation time	90408029 ps
CPU time	2.38 seconds
Started	Sep 11 06:09:54 AM UTC 24
Finished	Sep 11 06:09:58 AM UTC 24
Peak memory	226300 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=597230482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_mem_rw_wi th_rand_reset.597230482
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_rw.3432551486
Short name	T973
Test name
Test status
Simulation time	88610580 ps
CPU time	1.4 seconds
Started	Sep 11 06:09:53 AM UTC 24
Finished	Sep 11 06:09:56 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432551486 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3432551486
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_intr_test.1473784998
Short name	T939
Test name
Test status
Simulation time	17306856 ps
CPU time	0.98 seconds
Started	Sep 11 06:09:51 AM UTC 24
Finished	Sep 11 06:09:53 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473784998 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1473784998
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.864479382
Short name	T974
Test name
Test status
Simulation time	120895248 ps
CPU time	2.56 seconds
Started	Sep 11 06:09:53 AM UTC 24
Finished	Sep 11 06:09:57 AM UTC 24
Peak memory	216104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864479382 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_same_csr_outstanding.864479382
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.628057244
Short name	T970
Test name
Test status
Simulation time	98462250 ps
CPU time	3.85 seconds
Started	Sep 11 06:09:49 AM UTC 24
Finished	Sep 11 06:09:54 AM UTC 24
Peak memory	226484 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628057244 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors.628057244
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.4183824843
Short name	T972
Test name
Test status
Simulation time	287474986 ps
CPU time	3.93 seconds
Started	Sep 11 06:09:50 AM UTC 24
Finished	Sep 11 06:09:55 AM UTC 24
Peak memory	226736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183824843 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors_with_csr_rw.4183824843
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_errors.2238064692
Short name	T968
Test name
Test status
Simulation time	281893302 ps
CPU time	2.73 seconds
Started	Sep 11 06:09:50 AM UTC 24
Finished	Sep 11 06:09:54 AM UTC 24
Peak memory	226084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238064692 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2238064692
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_intg_err.824350347
Short name	T172
Test name
Test status
Simulation time	167126844 ps
CPU time	6.84 seconds
Started	Sep 11 06:09:51 AM UTC 24
Finished	Sep 11 06:09:59 AM UTC 24
Peak memory	215832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824350347 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.824350347
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3594789537
Short name	T980
Test name
Test status
Simulation time	92679060 ps
CPU time	2.46 seconds
Started	Sep 11 06:09:59 AM UTC 24
Finished	Sep 11 06:10:03 AM UTC 24
Peak memory	226112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3594789537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_mem_rw_w ith_rand_reset.3594789537
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_rw.1984978282
Short name	T977
Test name
Test status
Simulation time	118652959 ps
CPU time	1.92 seconds
Started	Sep 11 06:09:57 AM UTC 24
Finished	Sep 11 06:10:00 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984978282 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1984978282
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_intr_test.2654721208
Short name	T975
Test name
Test status
Simulation time	43081958 ps
CPU time	0.88 seconds
Started	Sep 11 06:09:56 AM UTC 24
Finished	Sep 11 06:09:58 AM UTC 24
Peak memory	213576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654721208 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2654721208
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1395358453
Short name	T978
Test name
Test status
Simulation time	62340535 ps
CPU time	2.05 seconds
Started	Sep 11 06:09:58 AM UTC 24
Finished	Sep 11 06:10:01 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395358453 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_same_csr_outstanding.1395358453
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3037417111
Short name	T979
Test name
Test status
Simulation time	184858260 ps
CPU time	6.07 seconds
Started	Sep 11 06:09:54 AM UTC 24
Finished	Sep 11 06:10:02 AM UTC 24
Peak memory	226680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037417111 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors.3037417111
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.883126658
Short name	T992
Test name
Test status
Simulation time	483684870 ps
CPU time	14.23 seconds
Started	Sep 11 06:09:55 AM UTC 24
Finished	Sep 11 06:10:10 AM UTC 24
Peak memory	226472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883126658 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors_with_csr_rw.883126658
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_errors.3612647692
Short name	T982
Test name
Test status
Simulation time	724648547 ps
CPU time	6.83 seconds
Started	Sep 11 06:09:56 AM UTC 24
Finished	Sep 11 06:10:04 AM UTC 24
Peak memory	226148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612647692 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3612647692
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/0.keymgr_direct_to_disabled.2787053695
Short name	T14
Test name
Test status
Simulation time	103913402 ps
CPU time	3.8 seconds
Started	Sep 11 05:47:26 AM UTC 24
Finished	Sep 11 05:47:31 AM UTC 24
Peak memory	215836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787053695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2787053695
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/0.keymgr_kmac_rsp_err.3945863960
Short name	T35
Test name
Test status
Simulation time	127003793 ps
CPU time	3.81 seconds
Started	Sep 11 05:47:52 AM UTC 24
Finished	Sep 11 05:47:57 AM UTC 24
Peak memory	226016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945863960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3945863960
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/0.keymgr_random.1355543443
Short name	T5
Test name
Test status
Simulation time	572572392 ps
CPU time	5.61 seconds
Started	Sep 11 05:47:05 AM UTC 24
Finished	Sep 11 05:47:12 AM UTC 24
Peak memory	215836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355543443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1355543443
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/0.keymgr_sideload.580296249
Short name	T2
Test name
Test status
Simulation time	787554924 ps
CPU time	4.22 seconds
Started	Sep 11 05:46:47 AM UTC 24
Finished	Sep 11 05:46:52 AM UTC 24
Peak memory	218028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580296249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.580296249
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_aes.2679618210
Short name	T4
Test name
Test status
Simulation time	75196725 ps
CPU time	2.86 seconds
Started	Sep 11 05:47:00 AM UTC 24
Finished	Sep 11 05:47:04 AM UTC 24
Peak memory	216160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679618210 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2679618210
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_otbn.963526659
Short name	T33
Test name
Test status
Simulation time	1296812513 ps
CPU time	51.98 seconds
Started	Sep 11 05:47:02 AM UTC 24
Finished	Sep 11 05:47:56 AM UTC 24
Peak memory	218204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963526659 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.963526659
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_protect.1732143062
Short name	T125
Test name
Test status
Simulation time	85172080 ps
CPU time	1.85 seconds
Started	Sep 11 05:47:58 AM UTC 24
Finished	Sep 11 05:48:01 AM UTC 24
Peak memory	223636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732143062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1732143062
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/0.keymgr_smoke.8304677
Short name	T1
Test name
Test status
Simulation time	95434739 ps
CPU time	2.73 seconds
Started	Sep 11 05:46:42 AM UTC 24
Finished	Sep 11 05:46:46 AM UTC 24
Peak memory	216028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8304677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=k eymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.8304677
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all.3588546623
Short name	T44
Test name
Test status
Simulation time	504002047 ps
CPU time	8.5 seconds
Started	Sep 11 05:48:02 AM UTC 24
Finished	Sep 11 05:48:12 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588546623 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3588546623
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/0.keymgr_sync_async_fault_cross.824868269
Short name	T34
Test name
Test status
Simulation time	66864324 ps
CPU time	2.15 seconds
Started	Sep 11 05:48:01 AM UTC 24
Finished	Sep 11 05:48:04 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824868269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.824868269
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/0.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/1.keymgr_alert_test.741036222
Short name	T64
Test name
Test status
Simulation time	45447818 ps
CPU time	0.92 seconds
Started	Sep 11 05:49:25 AM UTC 24
Finished	Sep 11 05:49:28 AM UTC 24
Peak memory	214224 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741036222 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.741036222
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/1.keymgr_direct_to_disabled.846862973
Short name	T78
Test name
Test status
Simulation time	97367606 ps
CPU time	1.97 seconds
Started	Sep 11 05:48:52 AM UTC 24
Finished	Sep 11 05:48:55 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846862973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.846862973
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/1.keymgr_hwsw_invalid_input.2854591263
Short name	T134
Test name
Test status
Simulation time	65417918 ps
CPU time	2.73 seconds
Started	Sep 11 05:49:03 AM UTC 24
Finished	Sep 11 05:49:07 AM UTC 24
Peak memory	226164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854591263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2854591263
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/1.keymgr_kmac_rsp_err.709827881
Short name	T48
Test name
Test status
Simulation time	127217972 ps
CPU time	3.79 seconds
Started	Sep 11 05:49:04 AM UTC 24
Finished	Sep 11 05:49:09 AM UTC 24
Peak memory	223968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709827881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.709827881
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/1.keymgr_lc_disable.3358251435
Short name	T99
Test name
Test status
Simulation time	96355040 ps
CPU time	5.45 seconds
Started	Sep 11 05:48:56 AM UTC 24
Finished	Sep 11 05:49:02 AM UTC 24
Peak memory	230348 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358251435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3358251435
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/1.keymgr_random.1881934747
Short name	T76
Test name
Test status
Simulation time	528422900 ps
CPU time	6.98 seconds
Started	Sep 11 05:48:42 AM UTC 24
Finished	Sep 11 05:48:50 AM UTC 24
Peak memory	217884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881934747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1881934747
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/1.keymgr_sec_cm.858542390
Short name	T11
Test name
Test status
Simulation time	2011887720 ps
CPU time	13.84 seconds
Started	Sep 11 05:49:18 AM UTC 24
Finished	Sep 11 05:49:33 AM UTC 24
Peak memory	254372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858542390 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.858542390
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/1.keymgr_sideload.4187517520
Short name	T73
Test name
Test status
Simulation time	303128511 ps
CPU time	3.26 seconds
Started	Sep 11 05:48:32 AM UTC 24
Finished	Sep 11 05:48:37 AM UTC 24
Peak memory	216156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187517520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.4187517520
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_aes.3975840267
Short name	T75
Test name
Test status
Simulation time	77941067 ps
CPU time	2.07 seconds
Started	Sep 11 05:48:37 AM UTC 24
Finished	Sep 11 05:48:41 AM UTC 24
Peak memory	216156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975840267 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3975840267
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_otbn.3976291367
Short name	T77
Test name
Test status
Simulation time	2687847691 ps
CPU time	9.44 seconds
Started	Sep 11 05:48:41 AM UTC 24
Finished	Sep 11 05:48:51 AM UTC 24
Peak memory	218012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976291367 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3976291367
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_protect.482602531
Short name	T212
Test name
Test status
Simulation time	62784180 ps
CPU time	2.25 seconds
Started	Sep 11 05:49:09 AM UTC 24
Finished	Sep 11 05:49:12 AM UTC 24
Peak memory	224252 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482602531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.482602531
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/1.keymgr_smoke.2791965139
Short name	T72
Test name
Test status
Simulation time	3848831722 ps
CPU time	6.77 seconds
Started	Sep 11 05:48:25 AM UTC 24
Finished	Sep 11 05:48:33 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791965139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2791965139
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/1.keymgr_stress_all.2125665534
Short name	T69
Test name
Test status
Simulation time	150786274 ps
CPU time	9.47 seconds
Started	Sep 11 05:49:14 AM UTC 24
Finished	Sep 11 05:49:25 AM UTC 24
Peak memory	230172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125665534 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2125665534
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/1.keymgr_sw_invalid_input.3191504895
Short name	T25
Test name
Test status
Simulation time	240451848 ps
CPU time	10.1 seconds
Started	Sep 11 05:49:02 AM UTC 24
Finished	Sep 11 05:49:13 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191504895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3191504895
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/1.keymgr_sync_async_fault_cross.3399883908
Short name	T36
Test name
Test status
Simulation time	86473005 ps
CPU time	3.7 seconds
Started	Sep 11 05:49:13 AM UTC 24
Finished	Sep 11 05:49:18 AM UTC 24
Peak memory	220116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399883908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3399883908
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/1.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/10.keymgr_alert_test.2509457250
Short name	T462
Test name
Test status
Simulation time	24014160 ps
CPU time	0.89 seconds
Started	Sep 11 05:55:00 AM UTC 24
Finished	Sep 11 05:55:02 AM UTC 24
Peak memory	213532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509457250 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2509457250
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/10.keymgr_cfg_regwen.2758274746
Short name	T114
Test name
Test status
Simulation time	61822641 ps
CPU time	4.68 seconds
Started	Sep 11 05:54:37 AM UTC 24
Finished	Sep 11 05:54:43 AM UTC 24
Peak memory	232284 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758274746 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2758274746
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/10.keymgr_direct_to_disabled.1831269321
Short name	T430
Test name
Test status
Simulation time	435288363 ps
CPU time	5.36 seconds
Started	Sep 11 05:54:44 AM UTC 24
Finished	Sep 11 05:54:51 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831269321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1831269321
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/10.keymgr_hwsw_invalid_input.2747872911
Short name	T47
Test name
Test status
Simulation time	83022366 ps
CPU time	2.87 seconds
Started	Sep 11 05:54:51 AM UTC 24
Finished	Sep 11 05:54:55 AM UTC 24
Peak memory	215836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747872911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2747872911
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/10.keymgr_lc_disable.1823952294
Short name	T217
Test name
Test status
Simulation time	114232161 ps
CPU time	4.32 seconds
Started	Sep 11 05:54:44 AM UTC 24
Finished	Sep 11 05:54:50 AM UTC 24
Peak memory	224360 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823952294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1823952294
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/10.keymgr_random.3097461817
Short name	T459
Test name
Test status
Simulation time	78522514 ps
CPU time	2.49 seconds
Started	Sep 11 05:54:32 AM UTC 24
Finished	Sep 11 05:54:36 AM UTC 24
Peak memory	217884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097461817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3097461817
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/10.keymgr_sideload.3384951404
Short name	T249
Test name
Test status
Simulation time	812239643 ps
CPU time	24.31 seconds
Started	Sep 11 05:54:21 AM UTC 24
Finished	Sep 11 05:54:47 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384951404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3384951404
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_aes.2917625783
Short name	T311
Test name
Test status
Simulation time	91276115 ps
CPU time	3.67 seconds
Started	Sep 11 05:54:26 AM UTC 24
Finished	Sep 11 05:54:31 AM UTC 24
Peak memory	217944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917625783 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2917625783
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_kmac.1540535266
Short name	T405
Test name
Test status
Simulation time	22029611 ps
CPU time	2.14 seconds
Started	Sep 11 05:54:22 AM UTC 24
Finished	Sep 11 05:54:25 AM UTC 24
Peak memory	215900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540535266 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1540535266
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_otbn.1735547911
Short name	T463
Test name
Test status
Simulation time	1776592698 ps
CPU time	50.01 seconds
Started	Sep 11 05:54:27 AM UTC 24
Finished	Sep 11 05:55:19 AM UTC 24
Peak memory	217980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735547911 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1735547911
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_protect.1779141723
Short name	T460
Test name
Test status
Simulation time	333850007 ps
CPU time	3.23 seconds
Started	Sep 11 05:54:54 AM UTC 24
Finished	Sep 11 05:54:58 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779141723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1779141723
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/10.keymgr_smoke.3316898221
Short name	T458
Test name
Test status
Simulation time	116563850 ps
CPU time	4.76 seconds
Started	Sep 11 05:54:21 AM UTC 24
Finished	Sep 11 05:54:27 AM UTC 24
Peak memory	215832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316898221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3316898221
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all.1309214500
Short name	T195
Test name
Test status
Simulation time	3529307299 ps
CPU time	9.79 seconds
Started	Sep 11 05:54:59 AM UTC 24
Finished	Sep 11 05:55:10 AM UTC 24
Peak memory	217936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309214500 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1309214500
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/10.keymgr_sw_invalid_input.3272187440
Short name	T309
Test name
Test status
Simulation time	67406579 ps
CPU time	4.93 seconds
Started	Sep 11 05:54:48 AM UTC 24
Finished	Sep 11 05:54:54 AM UTC 24
Peak memory	224416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272187440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3272187440
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/10.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/11.keymgr_alert_test.860222469
Short name	T464
Test name
Test status
Simulation time	56683812 ps
CPU time	0.83 seconds
Started	Sep 11 05:55:28 AM UTC 24
Finished	Sep 11 05:55:30 AM UTC 24
Peak memory	213596 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860222469 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.860222469
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/11.keymgr_cfg_regwen.1459936705
Short name	T293
Test name
Test status
Simulation time	139650314 ps
CPU time	3.59 seconds
Started	Sep 11 05:55:10 AM UTC 24
Finished	Sep 11 05:55:15 AM UTC 24
Peak memory	226148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459936705 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1459936705
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/11.keymgr_custom_cm.1994884983
Short name	T31
Test name
Test status
Simulation time	377828406 ps
CPU time	5.35 seconds
Started	Sep 11 05:55:22 AM UTC 24
Finished	Sep 11 05:55:28 AM UTC 24
Peak memory	232948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994884983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1994884983
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/11.keymgr_direct_to_disabled.3346883033
Short name	T314
Test name
Test status
Simulation time	1284551454 ps
CPU time	8.61 seconds
Started	Sep 11 05:55:12 AM UTC 24
Finished	Sep 11 05:55:21 AM UTC 24
Peak memory	226304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346883033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3346883033
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/11.keymgr_kmac_rsp_err.408455753
Short name	T270
Test name
Test status
Simulation time	112625477 ps
CPU time	3.45 seconds
Started	Sep 11 05:55:20 AM UTC 24
Finished	Sep 11 05:55:24 AM UTC 24
Peak memory	223964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408455753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.408455753
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/11.keymgr_random.3393085697
Short name	T389
Test name
Test status
Simulation time	237168201 ps
CPU time	6.69 seconds
Started	Sep 11 05:55:09 AM UTC 24
Finished	Sep 11 05:55:17 AM UTC 24
Peak memory	220296 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393085697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3393085697
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/11.keymgr_sideload.838322805
Short name	T299
Test name
Test status
Simulation time	58203330 ps
CPU time	2.75 seconds
Started	Sep 11 05:55:02 AM UTC 24
Finished	Sep 11 05:55:06 AM UTC 24
Peak memory	216160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838322805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.838322805
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_aes.3953403352
Short name	T352
Test name
Test status
Simulation time	40226676 ps
CPU time	2.63 seconds
Started	Sep 11 05:55:05 AM UTC 24
Finished	Sep 11 05:55:09 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953403352 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3953403352
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_kmac.526902787
Short name	T316
Test name
Test status
Simulation time	728538576 ps
CPU time	9.46 seconds
Started	Sep 11 05:55:03 AM UTC 24
Finished	Sep 11 05:55:14 AM UTC 24
Peak memory	218204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526902787 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.526902787
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_otbn.527835759
Short name	T344
Test name
Test status
Simulation time	621197162 ps
CPU time	2.86 seconds
Started	Sep 11 05:55:06 AM UTC 24
Finished	Sep 11 05:55:10 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527835759 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.527835759
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_protect.3783799200
Short name	T259
Test name
Test status
Simulation time	23138119 ps
CPU time	2.21 seconds
Started	Sep 11 05:55:24 AM UTC 24
Finished	Sep 11 05:55:27 AM UTC 24
Peak memory	218020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783799200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3783799200
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/11.keymgr_smoke.3827915799
Short name	T406
Test name
Test status
Simulation time	116697299 ps
CPU time	3.1 seconds
Started	Sep 11 05:55:00 AM UTC 24
Finished	Sep 11 05:55:04 AM UTC 24
Peak memory	217816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827915799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3827915799
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/11.keymgr_sw_invalid_input.509482578
Short name	T300
Test name
Test status
Simulation time	930139712 ps
CPU time	7.97 seconds
Started	Sep 11 05:55:16 AM UTC 24
Finished	Sep 11 05:55:25 AM UTC 24
Peak memory	228288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509482578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.509482578
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/11.keymgr_sync_async_fault_cross.4201876898
Short name	T418
Test name
Test status
Simulation time	745932833 ps
CPU time	16.64 seconds
Started	Sep 11 05:55:25 AM UTC 24
Finished	Sep 11 05:55:43 AM UTC 24
Peak memory	219932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201876898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.4201876898
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/11.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/12.keymgr_alert_test.3866306394
Short name	T470
Test name
Test status
Simulation time	11170277 ps
CPU time	0.94 seconds
Started	Sep 11 05:55:58 AM UTC 24
Finished	Sep 11 05:56:00 AM UTC 24
Peak memory	213532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866306394 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3866306394
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/12.keymgr_cfg_regwen.2428891214
Short name	T328
Test name
Test status
Simulation time	162969196 ps
CPU time	3.77 seconds
Started	Sep 11 05:55:47 AM UTC 24
Finished	Sep 11 05:55:51 AM UTC 24
Peak memory	232392 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428891214 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2428891214
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/12.keymgr_custom_cm.1806384209
Short name	T27
Test name
Test status
Simulation time	137904619 ps
CPU time	5.69 seconds
Started	Sep 11 05:55:55 AM UTC 24
Finished	Sep 11 05:56:02 AM UTC 24
Peak memory	232560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806384209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1806384209
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/12.keymgr_direct_to_disabled.3219762578
Short name	T155
Test name
Test status
Simulation time	387378125 ps
CPU time	4.27 seconds
Started	Sep 11 05:55:50 AM UTC 24
Finished	Sep 11 05:55:55 AM UTC 24
Peak memory	220096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219762578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3219762578
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/12.keymgr_hwsw_invalid_input.2371230808
Short name	T292
Test name
Test status
Simulation time	733320862 ps
CPU time	3.84 seconds
Started	Sep 11 05:55:52 AM UTC 24
Finished	Sep 11 05:55:57 AM UTC 24
Peak memory	224100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371230808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2371230808
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/12.keymgr_lc_disable.3932278015
Short name	T218
Test name
Test status
Simulation time	271868808 ps
CPU time	4.27 seconds
Started	Sep 11 05:55:51 AM UTC 24
Finished	Sep 11 05:55:56 AM UTC 24
Peak memory	219956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932278015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3932278015
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/12.keymgr_random.4157669325
Short name	T265
Test name
Test status
Simulation time	99437480 ps
CPU time	4.97 seconds
Started	Sep 11 05:55:43 AM UTC 24
Finished	Sep 11 05:55:50 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157669325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.4157669325
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/12.keymgr_sideload.322588658
Short name	T465
Test name
Test status
Simulation time	247916826 ps
CPU time	2.75 seconds
Started	Sep 11 05:55:31 AM UTC 24
Finished	Sep 11 05:55:35 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322588658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.322588658
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_aes.3416220157
Short name	T466
Test name
Test status
Simulation time	194836661 ps
CPU time	8.23 seconds
Started	Sep 11 05:55:36 AM UTC 24
Finished	Sep 11 05:55:46 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416220157 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3416220157
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_kmac.929025244
Short name	T338
Test name
Test status
Simulation time	878319737 ps
CPU time	3.44 seconds
Started	Sep 11 05:55:34 AM UTC 24
Finished	Sep 11 05:55:39 AM UTC 24
Peak memory	217872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929025244 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.929025244
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_otbn.2361480352
Short name	T467
Test name
Test status
Simulation time	761327243 ps
CPU time	10.7 seconds
Started	Sep 11 05:55:39 AM UTC 24
Finished	Sep 11 05:55:51 AM UTC 24
Peak memory	217948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361480352 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2361480352
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_protect.869007510
Short name	T468
Test name
Test status
Simulation time	20261017 ps
CPU time	1.68 seconds
Started	Sep 11 05:55:56 AM UTC 24
Finished	Sep 11 05:55:59 AM UTC 24
Peak memory	215568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869007510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.869007510
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/12.keymgr_smoke.2467583493
Short name	T415
Test name
Test status
Simulation time	95455245 ps
CPU time	2.97 seconds
Started	Sep 11 05:55:29 AM UTC 24
Finished	Sep 11 05:55:33 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467583493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2467583493
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/12.keymgr_stress_all.582584213
Short name	T250
Test name
Test status
Simulation time	1780843534 ps
CPU time	65.74 seconds
Started	Sep 11 05:55:57 AM UTC 24
Finished	Sep 11 05:57:05 AM UTC 24
Peak memory	230708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582584213 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.582584213
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/12.keymgr_sw_invalid_input.3351938065
Short name	T353
Test name
Test status
Simulation time	30741016 ps
CPU time	2.57 seconds
Started	Sep 11 05:55:51 AM UTC 24
Finished	Sep 11 05:55:54 AM UTC 24
Peak memory	215832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351938065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3351938065
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/12.keymgr_sync_async_fault_cross.1725165271
Short name	T469
Test name
Test status
Simulation time	53776035 ps
CPU time	2.72 seconds
Started	Sep 11 05:55:56 AM UTC 24
Finished	Sep 11 05:56:00 AM UTC 24
Peak memory	217948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725165271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1725165271
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/12.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/13.keymgr_alert_test.1786986049
Short name	T475
Test name
Test status
Simulation time	79492394 ps
CPU time	1 seconds
Started	Sep 11 05:56:17 AM UTC 24
Finished	Sep 11 05:56:19 AM UTC 24
Peak memory	213532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786986049 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1786986049
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/13.keymgr_custom_cm.2440271631
Short name	T150
Test name
Test status
Simulation time	477690297 ps
CPU time	6.59 seconds
Started	Sep 11 05:56:12 AM UTC 24
Finished	Sep 11 05:56:20 AM UTC 24
Peak memory	232568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440271631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2440271631
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/13.keymgr_direct_to_disabled.137166357
Short name	T474
Test name
Test status
Simulation time	362392474 ps
CPU time	4.17 seconds
Started	Sep 11 05:56:06 AM UTC 24
Finished	Sep 11 05:56:11 AM UTC 24
Peak memory	217948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137166357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.137166357
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/13.keymgr_hwsw_invalid_input.3144992509
Short name	T23
Test name
Test status
Simulation time	152550910 ps
CPU time	5.73 seconds
Started	Sep 11 05:56:10 AM UTC 24
Finished	Sep 11 05:56:17 AM UTC 24
Peak memory	226480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144992509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3144992509
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/13.keymgr_lc_disable.2090682236
Short name	T236
Test name
Test status
Simulation time	400347050 ps
CPU time	3.69 seconds
Started	Sep 11 05:56:08 AM UTC 24
Finished	Sep 11 05:56:13 AM UTC 24
Peak memory	217924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090682236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2090682236
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/13.keymgr_random.1219797516
Short name	T294
Test name
Test status
Simulation time	268672206 ps
CPU time	3.93 seconds
Started	Sep 11 05:56:04 AM UTC 24
Finished	Sep 11 05:56:09 AM UTC 24
Peak memory	228452 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219797516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1219797516
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/13.keymgr_sideload.2886729029
Short name	T472
Test name
Test status
Simulation time	273216921 ps
CPU time	1.94 seconds
Started	Sep 11 05:56:00 AM UTC 24
Finished	Sep 11 05:56:03 AM UTC 24
Peak memory	215644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886729029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2886729029
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_aes.4073284298
Short name	T473
Test name
Test status
Simulation time	59020087 ps
CPU time	3.28 seconds
Started	Sep 11 05:56:01 AM UTC 24
Finished	Sep 11 05:56:05 AM UTC 24
Peak memory	218292 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073284298 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.4073284298
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_kmac.157192657
Short name	T367
Test name
Test status
Simulation time	1161492973 ps
CPU time	6.71 seconds
Started	Sep 11 05:56:00 AM UTC 24
Finished	Sep 11 05:56:08 AM UTC 24
Peak memory	216144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157192657 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.157192657
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_otbn.715048974
Short name	T366
Test name
Test status
Simulation time	63183924 ps
CPU time	3.49 seconds
Started	Sep 11 05:56:03 AM UTC 24
Finished	Sep 11 05:56:07 AM UTC 24
Peak memory	216152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715048974 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.715048974
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_protect.1717450913
Short name	T310
Test name
Test status
Simulation time	240194093 ps
CPU time	3.71 seconds
Started	Sep 11 05:56:14 AM UTC 24
Finished	Sep 11 05:56:19 AM UTC 24
Peak memory	220424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717450913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1717450913
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/13.keymgr_smoke.1051450912
Short name	T471
Test name
Test status
Simulation time	159058630 ps
CPU time	2.76 seconds
Started	Sep 11 05:55:59 AM UTC 24
Finished	Sep 11 05:56:03 AM UTC 24
Peak memory	217812 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051450912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1051450912
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all.3620510061
Short name	T482
Test name
Test status
Simulation time	4513396884 ps
CPU time	26.73 seconds
Started	Sep 11 05:56:15 AM UTC 24
Finished	Sep 11 05:56:43 AM UTC 24
Peak memory	226460 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620510061 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3620510061
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/13.keymgr_sw_invalid_input.4129584020
Short name	T301
Test name
Test status
Simulation time	127678960 ps
CPU time	2.9 seconds
Started	Sep 11 05:56:10 AM UTC 24
Finished	Sep 11 05:56:14 AM UTC 24
Peak memory	224388 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129584020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.4129584020
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/13.keymgr_sync_async_fault_cross.472645547
Short name	T183
Test name
Test status
Simulation time	1086934803 ps
CPU time	8 seconds
Started	Sep 11 05:56:15 AM UTC 24
Finished	Sep 11 05:56:24 AM UTC 24
Peak memory	220004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472645547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.472645547
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/13.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/14.keymgr_alert_test.2217325409
Short name	T481
Test name
Test status
Simulation time	37609973 ps
CPU time	1.07 seconds
Started	Sep 11 05:56:37 AM UTC 24
Finished	Sep 11 05:56:39 AM UTC 24
Peak memory	213532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217325409 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2217325409
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/14.keymgr_custom_cm.3870134910
Short name	T30
Test name
Test status
Simulation time	37343595 ps
CPU time	2.62 seconds
Started	Sep 11 05:56:32 AM UTC 24
Finished	Sep 11 05:56:36 AM UTC 24
Peak memory	217880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870134910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3870134910
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/14.keymgr_direct_to_disabled.1847664869
Short name	T477
Test name
Test status
Simulation time	55123092 ps
CPU time	2.25 seconds
Started	Sep 11 05:56:26 AM UTC 24
Finished	Sep 11 05:56:29 AM UTC 24
Peak memory	215836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847664869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1847664869
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/14.keymgr_hwsw_invalid_input.3854490251
Short name	T51
Test name
Test status
Simulation time	115899430 ps
CPU time	2.9 seconds
Started	Sep 11 05:56:31 AM UTC 24
Finished	Sep 11 05:56:35 AM UTC 24
Peak memory	224108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854490251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3854490251
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/14.keymgr_kmac_rsp_err.2774501097
Short name	T261
Test name
Test status
Simulation time	108413139 ps
CPU time	5.4 seconds
Started	Sep 11 05:56:32 AM UTC 24
Finished	Sep 11 05:56:38 AM UTC 24
Peak memory	224060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774501097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2774501097
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/14.keymgr_lc_disable.873378296
Short name	T479
Test name
Test status
Simulation time	559450851 ps
CPU time	3.2 seconds
Started	Sep 11 05:56:27 AM UTC 24
Finished	Sep 11 05:56:31 AM UTC 24
Peak memory	230268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873378296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.873378296
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/14.keymgr_sideload.3281840872
Short name	T260
Test name
Test status
Simulation time	217892765 ps
CPU time	4.07 seconds
Started	Sep 11 05:56:20 AM UTC 24
Finished	Sep 11 05:56:26 AM UTC 24
Peak memory	218112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281840872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3281840872
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_aes.1548272572
Short name	T317
Test name
Test status
Simulation time	75942791 ps
CPU time	2.64 seconds
Started	Sep 11 05:56:21 AM UTC 24
Finished	Sep 11 05:56:24 AM UTC 24
Peak memory	217876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548272572 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1548272572
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_kmac.377079683
Short name	T476
Test name
Test status
Simulation time	20445861 ps
CPU time	1.93 seconds
Started	Sep 11 05:56:21 AM UTC 24
Finished	Sep 11 05:56:23 AM UTC 24
Peak memory	215696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377079683 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.377079683
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_otbn.3926086491
Short name	T478
Test name
Test status
Simulation time	444769837 ps
CPU time	8.04 seconds
Started	Sep 11 05:56:22 AM UTC 24
Finished	Sep 11 05:56:31 AM UTC 24
Peak memory	218204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926086491 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3926086491
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_protect.1671262489
Short name	T480
Test name
Test status
Simulation time	314611785 ps
CPU time	3.77 seconds
Started	Sep 11 05:56:32 AM UTC 24
Finished	Sep 11 05:56:37 AM UTC 24
Peak memory	230240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671262489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1671262489
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/14.keymgr_smoke.2605606649
Short name	T485
Test name
Test status
Simulation time	1315420867 ps
CPU time	30.99 seconds
Started	Sep 11 05:56:18 AM UTC 24
Finished	Sep 11 05:56:51 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605606649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2605606649
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/14.keymgr_sw_invalid_input.3763733663
Short name	T275
Test name
Test status
Simulation time	65099142 ps
CPU time	4.22 seconds
Started	Sep 11 05:56:30 AM UTC 24
Finished	Sep 11 05:56:35 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763733663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3763733663
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/14.keymgr_sync_async_fault_cross.1108252617
Short name	T174
Test name
Test status
Simulation time	74660890 ps
CPU time	2.73 seconds
Started	Sep 11 05:56:36 AM UTC 24
Finished	Sep 11 05:56:40 AM UTC 24
Peak memory	220004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108252617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1108252617
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/14.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/15.keymgr_alert_test.2744366535
Short name	T490
Test name
Test status
Simulation time	26690551 ps
CPU time	1.14 seconds
Started	Sep 11 05:57:06 AM UTC 24
Finished	Sep 11 05:57:09 AM UTC 24
Peak memory	214164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744366535 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2744366535
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/15.keymgr_custom_cm.2745628792
Short name	T151
Test name
Test status
Simulation time	405851035 ps
CPU time	5.55 seconds
Started	Sep 11 05:56:59 AM UTC 24
Finished	Sep 11 05:57:06 AM UTC 24
Peak memory	218548 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745628792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2745628792
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/15.keymgr_direct_to_disabled.653767276
Short name	T385
Test name
Test status
Simulation time	871733328 ps
CPU time	5.27 seconds
Started	Sep 11 05:56:52 AM UTC 24
Finished	Sep 11 05:56:58 AM UTC 24
Peak memory	217876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653767276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.653767276
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/15.keymgr_hwsw_invalid_input.3921723012
Short name	T61
Test name
Test status
Simulation time	1152170772 ps
CPU time	42.27 seconds
Started	Sep 11 05:56:59 AM UTC 24
Finished	Sep 11 05:57:43 AM UTC 24
Peak memory	231148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921723012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3921723012
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/15.keymgr_kmac_rsp_err.3771085009
Short name	T378
Test name
Test status
Simulation time	291835907 ps
CPU time	2.94 seconds
Started	Sep 11 05:56:59 AM UTC 24
Finished	Sep 11 05:57:03 AM UTC 24
Peak memory	224288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771085009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3771085009
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/15.keymgr_lc_disable.2116358380
Short name	T235
Test name
Test status
Simulation time	355170603 ps
CPU time	4.52 seconds
Started	Sep 11 05:56:53 AM UTC 24
Finished	Sep 11 05:56:58 AM UTC 24
Peak memory	218216 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116358380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2116358380
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/15.keymgr_random.3248731969
Short name	T279
Test name
Test status
Simulation time	4889875971 ps
CPU time	12.79 seconds
Started	Sep 11 05:56:46 AM UTC 24
Finished	Sep 11 05:57:00 AM UTC 24
Peak memory	228336 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248731969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3248731969
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/15.keymgr_sideload.162953794
Short name	T483
Test name
Test status
Simulation time	131441616 ps
CPU time	2.65 seconds
Started	Sep 11 05:56:40 AM UTC 24
Finished	Sep 11 05:56:44 AM UTC 24
Peak memory	215428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162953794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.162953794
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_aes.1161006986
Short name	T491
Test name
Test status
Simulation time	3830172030 ps
CPU time	26.91 seconds
Started	Sep 11 05:56:45 AM UTC 24
Finished	Sep 11 05:57:13 AM UTC 24
Peak memory	218284 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161006986 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1161006986
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_kmac.1902307067
Short name	T488
Test name
Test status
Simulation time	3703146496 ps
CPU time	25.39 seconds
Started	Sep 11 05:56:41 AM UTC 24
Finished	Sep 11 05:57:07 AM UTC 24
Peak memory	215436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902307067 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1902307067
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_otbn.1966994940
Short name	T486
Test name
Test status
Simulation time	140510684 ps
CPU time	6.28 seconds
Started	Sep 11 05:56:45 AM UTC 24
Finished	Sep 11 05:56:52 AM UTC 24
Peak memory	218236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966994940 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1966994940
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_protect.2350477452
Short name	T487
Test name
Test status
Simulation time	126179679 ps
CPU time	3.12 seconds
Started	Sep 11 05:57:00 AM UTC 24
Finished	Sep 11 05:57:04 AM UTC 24
Peak memory	218020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350477452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2350477452
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/15.keymgr_smoke.1187722797
Short name	T484
Test name
Test status
Simulation time	360656249 ps
CPU time	7.54 seconds
Started	Sep 11 05:56:39 AM UTC 24
Finished	Sep 11 05:56:48 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187722797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1187722797
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all.986893248
Short name	T224
Test name
Test status
Simulation time	7875666799 ps
CPU time	16.64 seconds
Started	Sep 11 05:57:05 AM UTC 24
Finished	Sep 11 05:57:23 AM UTC 24
Peak memory	232108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986893248 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.986893248
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all_with_rand_reset.3084825461
Short name	T100
Test name
Test status
Simulation time	227739006 ps
CPU time	14.03 seconds
Started	Sep 11 05:57:05 AM UTC 24
Finished	Sep 11 05:57:20 AM UTC 24
Peak memory	232392 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3084825461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymg r_stress_all_with_rand_reset.3084825461
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/15.keymgr_sync_async_fault_cross.3506062797
Short name	T489
Test name
Test status
Simulation time	120208284 ps
CPU time	3.19 seconds
Started	Sep 11 05:57:04 AM UTC 24
Finished	Sep 11 05:57:08 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506062797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3506062797
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/15.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/16.keymgr_alert_test.2155759811
Short name	T500
Test name
Test status
Simulation time	63700021 ps
CPU time	1.15 seconds
Started	Sep 11 05:57:26 AM UTC 24
Finished	Sep 11 05:57:29 AM UTC 24
Peak memory	213712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155759811 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2155759811
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/16.keymgr_custom_cm.3956890598
Short name	T219
Test name
Test status
Simulation time	108834658 ps
CPU time	4.64 seconds
Started	Sep 11 05:57:21 AM UTC 24
Finished	Sep 11 05:57:27 AM UTC 24
Peak memory	224356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956890598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3956890598
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/16.keymgr_direct_to_disabled.3682330231
Short name	T496
Test name
Test status
Simulation time	552719139 ps
CPU time	2.71 seconds
Started	Sep 11 05:57:17 AM UTC 24
Finished	Sep 11 05:57:21 AM UTC 24
Peak memory	217880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682330231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3682330231
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/16.keymgr_hwsw_invalid_input.286283982
Short name	T374
Test name
Test status
Simulation time	87633428 ps
CPU time	3.28 seconds
Started	Sep 11 05:57:21 AM UTC 24
Finished	Sep 11 05:57:25 AM UTC 24
Peak memory	224288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286283982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.286283982
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/16.keymgr_kmac_rsp_err.2433573417
Short name	T306
Test name
Test status
Simulation time	344028605 ps
CPU time	3.6 seconds
Started	Sep 11 05:57:21 AM UTC 24
Finished	Sep 11 05:57:26 AM UTC 24
Peak memory	230184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433573417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2433573417
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/16.keymgr_lc_disable.1244608028
Short name	T497
Test name
Test status
Simulation time	120032303 ps
CPU time	4.2 seconds
Started	Sep 11 05:57:18 AM UTC 24
Finished	Sep 11 05:57:23 AM UTC 24
Peak memory	226496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244608028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1244608028
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/16.keymgr_random.997336600
Short name	T416
Test name
Test status
Simulation time	107709751 ps
CPU time	4.56 seconds
Started	Sep 11 05:57:15 AM UTC 24
Finished	Sep 11 05:57:20 AM UTC 24
Peak memory	215860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997336600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.997336600
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/16.keymgr_sideload.3810172000
Short name	T288
Test name
Test status
Simulation time	854842427 ps
CPU time	3.77 seconds
Started	Sep 11 05:57:10 AM UTC 24
Finished	Sep 11 05:57:14 AM UTC 24
Peak memory	215832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810172000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3810172000
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_aes.1019288776
Short name	T495
Test name
Test status
Simulation time	855868492 ps
CPU time	3.52 seconds
Started	Sep 11 05:57:14 AM UTC 24
Finished	Sep 11 05:57:18 AM UTC 24
Peak memory	217944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019288776 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1019288776
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_kmac.1893263780
Short name	T493
Test name
Test status
Simulation time	189158123 ps
CPU time	5.29 seconds
Started	Sep 11 05:57:10 AM UTC 24
Finished	Sep 11 05:57:16 AM UTC 24
Peak memory	218204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893263780 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1893263780
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_otbn.3663750540
Short name	T494
Test name
Test status
Simulation time	199162332 ps
CPU time	2.48 seconds
Started	Sep 11 05:57:14 AM UTC 24
Finished	Sep 11 05:57:17 AM UTC 24
Peak memory	215900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663750540 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3663750540
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_protect.2724536804
Short name	T498
Test name
Test status
Simulation time	217498411 ps
CPU time	3.15 seconds
Started	Sep 11 05:57:22 AM UTC 24
Finished	Sep 11 05:57:26 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724536804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2724536804
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/16.keymgr_smoke.2850837038
Short name	T492
Test name
Test status
Simulation time	183804181 ps
CPU time	3.47 seconds
Started	Sep 11 05:57:08 AM UTC 24
Finished	Sep 11 05:57:13 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850837038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2850837038
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/16.keymgr_stress_all_with_rand_reset.1036543679
Short name	T101
Test name
Test status
Simulation time	526483177 ps
CPU time	18.28 seconds
Started	Sep 11 05:57:26 AM UTC 24
Finished	Sep 11 05:57:46 AM UTC 24
Peak memory	232396 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1036543679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymg r_stress_all_with_rand_reset.1036543679
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/16.keymgr_sw_invalid_input.558692236
Short name	T342
Test name
Test status
Simulation time	565204867 ps
CPU time	17.54 seconds
Started	Sep 11 05:57:19 AM UTC 24
Finished	Sep 11 05:57:38 AM UTC 24
Peak memory	217880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558692236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.558692236
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/16.keymgr_sync_async_fault_cross.1821205821
Short name	T499
Test name
Test status
Simulation time	52937640 ps
CPU time	2.77 seconds
Started	Sep 11 05:57:24 AM UTC 24
Finished	Sep 11 05:57:28 AM UTC 24
Peak memory	217884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821205821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1821205821
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/16.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/17.keymgr_alert_test.974655003
Short name	T508
Test name
Test status
Simulation time	12078975 ps
CPU time	0.92 seconds
Started	Sep 11 05:57:50 AM UTC 24
Finished	Sep 11 05:57:53 AM UTC 24
Peak memory	213596 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974655003 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.974655003
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/17.keymgr_custom_cm.1903930448
Short name	T152
Test name
Test status
Simulation time	200759242 ps
CPU time	3.44 seconds
Started	Sep 11 05:57:45 AM UTC 24
Finished	Sep 11 05:57:50 AM UTC 24
Peak memory	224712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903930448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1903930448
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/17.keymgr_direct_to_disabled.2245661994
Short name	T504
Test name
Test status
Simulation time	58250225 ps
CPU time	3.19 seconds
Started	Sep 11 05:57:34 AM UTC 24
Finished	Sep 11 05:57:38 AM UTC 24
Peak memory	217880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245661994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2245661994
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/17.keymgr_hwsw_invalid_input.778732117
Short name	T60
Test name
Test status
Simulation time	288274678 ps
CPU time	4.63 seconds
Started	Sep 11 05:57:44 AM UTC 24
Finished	Sep 11 05:57:50 AM UTC 24
Peak memory	217876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778732117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.778732117
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/17.keymgr_kmac_rsp_err.3165294701
Short name	T271
Test name
Test status
Simulation time	132132045 ps
CPU time	6.11 seconds
Started	Sep 11 05:57:44 AM UTC 24
Finished	Sep 11 05:57:51 AM UTC 24
Peak memory	226004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165294701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3165294701
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/17.keymgr_lc_disable.2358864879
Short name	T506
Test name
Test status
Simulation time	1102616311 ps
CPU time	5.08 seconds
Started	Sep 11 05:57:38 AM UTC 24
Finished	Sep 11 05:57:44 AM UTC 24
Peak memory	230212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358864879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2358864879
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/17.keymgr_random.1080737707
Short name	T505
Test name
Test status
Simulation time	396242255 ps
CPU time	8.27 seconds
Started	Sep 11 05:57:34 AM UTC 24
Finished	Sep 11 05:57:43 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080737707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1080737707
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/17.keymgr_sideload.3890596987
Short name	T503
Test name
Test status
Simulation time	117442215 ps
CPU time	4.85 seconds
Started	Sep 11 05:57:28 AM UTC 24
Finished	Sep 11 05:57:33 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890596987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3890596987
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_aes.2269012385
Short name	T262
Test name
Test status
Simulation time	214727302 ps
CPU time	2.29 seconds
Started	Sep 11 05:57:30 AM UTC 24
Finished	Sep 11 05:57:33 AM UTC 24
Peak memory	215900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269012385 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2269012385
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_kmac.613557172
Short name	T502
Test name
Test status
Simulation time	126852219 ps
CPU time	2.59 seconds
Started	Sep 11 05:57:29 AM UTC 24
Finished	Sep 11 05:57:32 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613557172 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.613557172
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_otbn.196314640
Short name	T509
Test name
Test status
Simulation time	872953555 ps
CPU time	24.38 seconds
Started	Sep 11 05:57:33 AM UTC 24
Finished	Sep 11 05:57:59 AM UTC 24
Peak memory	217948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196314640 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.196314640
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_protect.1880178044
Short name	T507
Test name
Test status
Simulation time	143629781 ps
CPU time	2.53 seconds
Started	Sep 11 05:57:45 AM UTC 24
Finished	Sep 11 05:57:49 AM UTC 24
Peak memory	218020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880178044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1880178044
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/17.keymgr_smoke.1612995145
Short name	T501
Test name
Test status
Simulation time	271041639 ps
CPU time	3.62 seconds
Started	Sep 11 05:57:28 AM UTC 24
Finished	Sep 11 05:57:32 AM UTC 24
Peak memory	215844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612995145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1612995145
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all.3531822536
Short name	T251
Test name
Test status
Simulation time	1699345335 ps
CPU time	24.88 seconds
Started	Sep 11 05:57:49 AM UTC 24
Finished	Sep 11 05:58:16 AM UTC 24
Peak memory	232576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531822536 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3531822536
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/17.keymgr_sw_invalid_input.2708901035
Short name	T431
Test name
Test status
Simulation time	84198954 ps
CPU time	4.64 seconds
Started	Sep 11 05:57:39 AM UTC 24
Finished	Sep 11 05:57:45 AM UTC 24
Peak memory	226236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708901035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2708901035
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/17.keymgr_sync_async_fault_cross.1139782122
Short name	T179
Test name
Test status
Simulation time	353998189 ps
CPU time	4.51 seconds
Started	Sep 11 05:57:46 AM UTC 24
Finished	Sep 11 05:57:52 AM UTC 24
Peak memory	219932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139782122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1139782122
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/17.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/18.keymgr_alert_test.1623839130
Short name	T518
Test name
Test status
Simulation time	41965223 ps
CPU time	0.92 seconds
Started	Sep 11 05:58:16 AM UTC 24
Finished	Sep 11 05:58:18 AM UTC 24
Peak memory	213592 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623839130 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1623839130
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/18.keymgr_cfg_regwen.2770730937
Short name	T297
Test name
Test status
Simulation time	34693185 ps
CPU time	3.06 seconds
Started	Sep 11 05:58:00 AM UTC 24
Finished	Sep 11 05:58:04 AM UTC 24
Peak memory	226436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770730937 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2770730937
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/18.keymgr_custom_cm.1868714896
Short name	T225
Test name
Test status
Simulation time	2031299809 ps
CPU time	35.33 seconds
Started	Sep 11 05:58:06 AM UTC 24
Finished	Sep 11 05:58:43 AM UTC 24
Peak memory	232580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868714896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1868714896
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/18.keymgr_direct_to_disabled.1242180093
Short name	T514
Test name
Test status
Simulation time	43003694 ps
CPU time	2.46 seconds
Started	Sep 11 05:58:02 AM UTC 24
Finished	Sep 11 05:58:05 AM UTC 24
Peak memory	217880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242180093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1242180093
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/18.keymgr_lc_disable.1751507035
Short name	T515
Test name
Test status
Simulation time	338837384 ps
CPU time	3.88 seconds
Started	Sep 11 05:58:03 AM UTC 24
Finished	Sep 11 05:58:08 AM UTC 24
Peak memory	224116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751507035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1751507035
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/18.keymgr_random.1093483665
Short name	T362
Test name
Test status
Simulation time	142053298 ps
CPU time	3.05 seconds
Started	Sep 11 05:58:00 AM UTC 24
Finished	Sep 11 05:58:04 AM UTC 24
Peak memory	224304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093483665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1093483665
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/18.keymgr_sideload.1746493632
Short name	T417
Test name
Test status
Simulation time	208738061 ps
CPU time	3.16 seconds
Started	Sep 11 05:57:54 AM UTC 24
Finished	Sep 11 05:57:58 AM UTC 24
Peak memory	218208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746493632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1746493632
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_aes.2835416500
Short name	T511
Test name
Test status
Simulation time	84703476 ps
CPU time	2.19 seconds
Started	Sep 11 05:57:58 AM UTC 24
Finished	Sep 11 05:58:01 AM UTC 24
Peak memory	215924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835416500 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2835416500
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_kmac.3503447264
Short name	T510
Test name
Test status
Simulation time	58107880 ps
CPU time	3.78 seconds
Started	Sep 11 05:57:54 AM UTC 24
Finished	Sep 11 05:57:59 AM UTC 24
Peak memory	217944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503447264 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3503447264
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_otbn.1514495694
Short name	T513
Test name
Test status
Simulation time	1364053472 ps
CPU time	4.35 seconds
Started	Sep 11 05:57:59 AM UTC 24
Finished	Sep 11 05:58:04 AM UTC 24
Peak memory	217948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514495694 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1514495694
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_protect.2835685290
Short name	T516
Test name
Test status
Simulation time	89812341 ps
CPU time	2.93 seconds
Started	Sep 11 05:58:09 AM UTC 24
Finished	Sep 11 05:58:13 AM UTC 24
Peak memory	218268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835685290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2835685290
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/18.keymgr_smoke.1045332645
Short name	T512
Test name
Test status
Simulation time	838611080 ps
CPU time	7.62 seconds
Started	Sep 11 05:57:53 AM UTC 24
Finished	Sep 11 05:58:02 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045332645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1045332645
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all.2910494661
Short name	T517
Test name
Test status
Simulation time	612990356 ps
CPU time	1.99 seconds
Started	Sep 11 05:58:14 AM UTC 24
Finished	Sep 11 05:58:17 AM UTC 24
Peak memory	214164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910494661 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2910494661
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all_with_rand_reset.329428030
Short name	T312
Test name
Test status
Simulation time	4020096986 ps
CPU time	22.35 seconds
Started	Sep 11 05:58:14 AM UTC 24
Finished	Sep 11 05:58:38 AM UTC 24
Peak memory	232768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=329428030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr _stress_all_with_rand_reset.329428030
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/18.keymgr_sw_invalid_input.727438922
Short name	T268
Test name
Test status
Simulation time	361503105 ps
CPU time	6.83 seconds
Started	Sep 11 05:58:05 AM UTC 24
Finished	Sep 11 05:58:13 AM UTC 24
Peak memory	215632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727438922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.727438922
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/18.keymgr_sync_async_fault_cross.492371049
Short name	T181
Test name
Test status
Simulation time	270234330 ps
CPU time	4.16 seconds
Started	Sep 11 05:58:10 AM UTC 24
Finished	Sep 11 05:58:16 AM UTC 24
Peak memory	219932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492371049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.492371049
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/18.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/19.keymgr_alert_test.3485134552
Short name	T527
Test name
Test status
Simulation time	37019847 ps
CPU time	1 seconds
Started	Sep 11 05:58:39 AM UTC 24
Finished	Sep 11 05:58:41 AM UTC 24
Peak memory	213532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485134552 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3485134552
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/19.keymgr_cfg_regwen.3108465583
Short name	T420
Test name
Test status
Simulation time	75721440 ps
CPU time	4.5 seconds
Started	Sep 11 05:58:23 AM UTC 24
Finished	Sep 11 05:58:29 AM UTC 24
Peak memory	226068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108465583 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3108465583
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/19.keymgr_custom_cm.1556754934
Short name	T525
Test name
Test status
Simulation time	346556055 ps
CPU time	4.32 seconds
Started	Sep 11 05:58:32 AM UTC 24
Finished	Sep 11 05:58:37 AM UTC 24
Peak memory	224436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556754934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1556754934
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/19.keymgr_direct_to_disabled.4155764106
Short name	T533
Test name
Test status
Simulation time	5547607608 ps
CPU time	24.31 seconds
Started	Sep 11 05:58:25 AM UTC 24
Finished	Sep 11 05:58:51 AM UTC 24
Peak memory	224412 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155764106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.4155764106
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/19.keymgr_kmac_rsp_err.876734708
Short name	T291
Test name
Test status
Simulation time	281264471 ps
CPU time	3.93 seconds
Started	Sep 11 05:58:32 AM UTC 24
Finished	Sep 11 05:58:37 AM UTC 24
Peak memory	226084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876734708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.876734708
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/19.keymgr_random.3072844570
Short name	T523
Test name
Test status
Simulation time	563967897 ps
CPU time	3.65 seconds
Started	Sep 11 05:58:22 AM UTC 24
Finished	Sep 11 05:58:26 AM UTC 24
Peak memory	217872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072844570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3072844570
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/19.keymgr_sideload.3218939333
Short name	T412
Test name
Test status
Simulation time	54544599 ps
CPU time	3.04 seconds
Started	Sep 11 05:58:17 AM UTC 24
Finished	Sep 11 05:58:21 AM UTC 24
Peak memory	217880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218939333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3218939333
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_aes.2576207260
Short name	T521
Test name
Test status
Simulation time	463543791 ps
CPU time	4.79 seconds
Started	Sep 11 05:58:19 AM UTC 24
Finished	Sep 11 05:58:24 AM UTC 24
Peak memory	218028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576207260 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2576207260
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_kmac.2068560805
Short name	T520
Test name
Test status
Simulation time	90734251 ps
CPU time	2.8 seconds
Started	Sep 11 05:58:19 AM UTC 24
Finished	Sep 11 05:58:22 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068560805 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2068560805
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_otbn.4220920935
Short name	T522
Test name
Test status
Simulation time	183473152 ps
CPU time	4.01 seconds
Started	Sep 11 05:58:21 AM UTC 24
Finished	Sep 11 05:58:26 AM UTC 24
Peak memory	217916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220920935 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.4220920935
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_protect.2245867093
Short name	T526
Test name
Test status
Simulation time	107858518 ps
CPU time	3.04 seconds
Started	Sep 11 05:58:34 AM UTC 24
Finished	Sep 11 05:58:38 AM UTC 24
Peak memory	228276 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245867093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2245867093
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/19.keymgr_smoke.1640712911
Short name	T519
Test name
Test status
Simulation time	56762891 ps
CPU time	2.81 seconds
Started	Sep 11 05:58:17 AM UTC 24
Finished	Sep 11 05:58:20 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640712911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1640712911
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/19.keymgr_sw_invalid_input.3230641233
Short name	T524
Test name
Test status
Simulation time	131295100 ps
CPU time	3.11 seconds
Started	Sep 11 05:58:27 AM UTC 24
Finished	Sep 11 05:58:31 AM UTC 24
Peak memory	217876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230641233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3230641233
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/19.keymgr_sync_async_fault_cross.790341475
Short name	T528
Test name
Test status
Simulation time	290543857 ps
CPU time	3.69 seconds
Started	Sep 11 05:58:38 AM UTC 24
Finished	Sep 11 05:58:43 AM UTC 24
Peak memory	219932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790341475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.790341475
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/19.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/2.keymgr_alert_test.2168371810
Short name	T65
Test name
Test status
Simulation time	42727112 ps
CPU time	1.09 seconds
Started	Sep 11 05:50:12 AM UTC 24
Finished	Sep 11 05:50:14 AM UTC 24
Peak memory	213600 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168371810 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2168371810
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/2.keymgr_direct_to_disabled.4089555601
Short name	T136
Test name
Test status
Simulation time	191651106 ps
CPU time	2.98 seconds
Started	Sep 11 05:49:48 AM UTC 24
Finished	Sep 11 05:49:52 AM UTC 24
Peak memory	228248 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089555601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.4089555601
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/2.keymgr_hwsw_invalid_input.4016321254
Short name	T52
Test name
Test status
Simulation time	35491146 ps
CPU time	3.09 seconds
Started	Sep 11 05:49:55 AM UTC 24
Finished	Sep 11 05:49:59 AM UTC 24
Peak memory	224020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016321254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.4016321254
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/2.keymgr_kmac_rsp_err.3190392130
Short name	T71
Test name
Test status
Simulation time	209905371 ps
CPU time	3.32 seconds
Started	Sep 11 05:49:57 AM UTC 24
Finished	Sep 11 05:50:02 AM UTC 24
Peak memory	226176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190392130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3190392130
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/2.keymgr_lc_disable.3546302932
Short name	T109
Test name
Test status
Simulation time	46642648 ps
CPU time	3.19 seconds
Started	Sep 11 05:49:52 AM UTC 24
Finished	Sep 11 05:49:56 AM UTC 24
Peak memory	215840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546302932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3546302932
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/2.keymgr_random.324554547
Short name	T204
Test name
Test status
Simulation time	239109470 ps
CPU time	8.58 seconds
Started	Sep 11 05:49:45 AM UTC 24
Finished	Sep 11 05:49:55 AM UTC 24
Peak memory	217876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324554547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.324554547
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/2.keymgr_sec_cm.2028439543
Short name	T12
Test name
Test status
Simulation time	2060364029 ps
CPU time	12.99 seconds
Started	Sep 11 05:50:09 AM UTC 24
Finished	Sep 11 05:50:23 AM UTC 24
Peak memory	259024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028439543 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2028439543
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/2.keymgr_sideload.2585316707
Short name	T104
Test name
Test status
Simulation time	395894546 ps
CPU time	3.23 seconds
Started	Sep 11 05:49:34 AM UTC 24
Finished	Sep 11 05:49:38 AM UTC 24
Peak memory	218200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585316707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2585316707
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_aes.768837963
Short name	T106
Test name
Test status
Simulation time	274490109 ps
CPU time	4.91 seconds
Started	Sep 11 05:49:39 AM UTC 24
Finished	Sep 11 05:49:45 AM UTC 24
Peak memory	216156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768837963 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.768837963
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_kmac.3724527848
Short name	T105
Test name
Test status
Simulation time	204815448 ps
CPU time	3.14 seconds
Started	Sep 11 05:49:35 AM UTC 24
Finished	Sep 11 05:49:39 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724527848 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3724527848
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_otbn.2850315997
Short name	T107
Test name
Test status
Simulation time	1085874187 ps
CPU time	6.02 seconds
Started	Sep 11 05:49:40 AM UTC 24
Finished	Sep 11 05:49:47 AM UTC 24
Peak memory	217872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850315997 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2850315997
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_protect.3975720610
Short name	T208
Test name
Test status
Simulation time	289177776 ps
CPU time	4.18 seconds
Started	Sep 11 05:50:00 AM UTC 24
Finished	Sep 11 05:50:06 AM UTC 24
Peak memory	224092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975720610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3975720610
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/2.keymgr_smoke.2188109009
Short name	T103
Test name
Test status
Simulation time	215155127 ps
CPU time	3.22 seconds
Started	Sep 11 05:49:28 AM UTC 24
Finished	Sep 11 05:49:33 AM UTC 24
Peak memory	216092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188109009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2188109009
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all.537638266
Short name	T67
Test name
Test status
Simulation time	274359606 ps
CPU time	13.4 seconds
Started	Sep 11 05:50:02 AM UTC 24
Finished	Sep 11 05:50:17 AM UTC 24
Peak memory	226068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537638266 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.537638266
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/2.keymgr_sw_invalid_input.3412319704
Short name	T248
Test name
Test status
Simulation time	114242136 ps
CPU time	2.66 seconds
Started	Sep 11 05:49:53 AM UTC 24
Finished	Sep 11 05:49:57 AM UTC 24
Peak memory	215900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412319704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3412319704
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/2.keymgr_sync_async_fault_cross.3088838206
Short name	T37
Test name
Test status
Simulation time	190554499 ps
CPU time	4.55 seconds
Started	Sep 11 05:50:02 AM UTC 24
Finished	Sep 11 05:50:08 AM UTC 24
Peak memory	220004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088838206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3088838206
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/20.keymgr_alert_test.2382969499
Short name	T541
Test name
Test status
Simulation time	24763588 ps
CPU time	1.07 seconds
Started	Sep 11 05:59:02 AM UTC 24
Finished	Sep 11 05:59:05 AM UTC 24
Peak memory	213532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382969499 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2382969499
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/20.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/20.keymgr_cfg_regwen.1224331855
Short name	T286
Test name
Test status
Simulation time	187201204 ps
CPU time	10.63 seconds
Started	Sep 11 05:58:50 AM UTC 24
Finished	Sep 11 05:59:02 AM UTC 24
Peak memory	224096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224331855 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1224331855
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/20.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/20.keymgr_custom_cm.2898683902
Short name	T228
Test name
Test status
Simulation time	238432664 ps
CPU time	5.87 seconds
Started	Sep 11 05:58:55 AM UTC 24
Finished	Sep 11 05:59:02 AM UTC 24
Peak memory	218212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898683902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2898683902
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/20.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/20.keymgr_direct_to_disabled.1766844050
Short name	T537
Test name
Test status
Simulation time	261246862 ps
CPU time	2.61 seconds
Started	Sep 11 05:58:51 AM UTC 24
Finished	Sep 11 05:58:55 AM UTC 24
Peak memory	215832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766844050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1766844050
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/20.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/20.keymgr_hwsw_invalid_input.1622114484
Short name	T538
Test name
Test status
Simulation time	51287157 ps
CPU time	3.51 seconds
Started	Sep 11 05:58:52 AM UTC 24
Finished	Sep 11 05:58:57 AM UTC 24
Peak memory	217880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622114484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1622114484
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/20.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/20.keymgr_lc_disable.3583495837
Short name	T539
Test name
Test status
Simulation time	132653655 ps
CPU time	5.49 seconds
Started	Sep 11 05:58:52 AM UTC 24
Finished	Sep 11 05:58:59 AM UTC 24
Peak memory	230504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583495837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3583495837
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/20.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/20.keymgr_random.3570338373
Short name	T536
Test name
Test status
Simulation time	96887896 ps
CPU time	4.08 seconds
Started	Sep 11 05:58:48 AM UTC 24
Finished	Sep 11 05:58:53 AM UTC 24
Peak memory	216156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570338373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3570338373
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/20.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/20.keymgr_sideload.1209312355
Short name	T531
Test name
Test status
Simulation time	35684951 ps
CPU time	2.6 seconds
Started	Sep 11 05:58:44 AM UTC 24
Finished	Sep 11 05:58:47 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209312355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1209312355
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/20.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_aes.17313163
Short name	T535
Test name
Test status
Simulation time	74944414 ps
CPU time	3.91 seconds
Started	Sep 11 05:58:47 AM UTC 24
Finished	Sep 11 05:58:52 AM UTC 24
Peak memory	217684 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17313163 -assert nopostproc +UVM_TESTNAME=keymgr_base_ test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.17313163
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/20.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_kmac.932190838
Short name	T532
Test name
Test status
Simulation time	296106392 ps
CPU time	4.08 seconds
Started	Sep 11 05:58:44 AM UTC 24
Finished	Sep 11 05:58:49 AM UTC 24
Peak memory	218020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932190838 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.932190838
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/20.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_otbn.4156479641
Short name	T534
Test name
Test status
Simulation time	315395170 ps
CPU time	3.42 seconds
Started	Sep 11 05:58:47 AM UTC 24
Finished	Sep 11 05:58:51 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156479641 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.4156479641
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/20.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_protect.1076822777
Short name	T552
Test name
Test status
Simulation time	2763242576 ps
CPU time	31.17 seconds
Started	Sep 11 05:58:56 AM UTC 24
Finished	Sep 11 05:59:29 AM UTC 24
Peak memory	226292 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076822777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1076822777
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/20.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/20.keymgr_smoke.2901532968
Short name	T530
Test name
Test status
Simulation time	94264159 ps
CPU time	2.75 seconds
Started	Sep 11 05:58:43 AM UTC 24
Finished	Sep 11 05:58:46 AM UTC 24
Peak memory	216100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901532968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2901532968
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/20.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all.172441800
Short name	T197
Test name
Test status
Simulation time	108473722 ps
CPU time	4.83 seconds
Started	Sep 11 05:58:59 AM UTC 24
Finished	Sep 11 05:59:05 AM UTC 24
Peak memory	218072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172441800 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.172441800
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/20.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all_with_rand_reset.1329284166
Short name	T156
Test name
Test status
Simulation time	805265757 ps
CPU time	10.95 seconds
Started	Sep 11 05:59:02 AM UTC 24
Finished	Sep 11 05:59:15 AM UTC 24
Peak memory	230364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1329284166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymg r_stress_all_with_rand_reset.1329284166
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/20.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/20.keymgr_sw_invalid_input.827391966
Short name	T266
Test name
Test status
Simulation time	910816457 ps
CPU time	11.74 seconds
Started	Sep 11 05:58:52 AM UTC 24
Finished	Sep 11 05:59:05 AM UTC 24
Peak memory	218228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827391966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.827391966
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/20.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/20.keymgr_sync_async_fault_cross.2427254530
Short name	T542
Test name
Test status
Simulation time	914566754 ps
CPU time	7.85 seconds
Started	Sep 11 05:58:57 AM UTC 24
Finished	Sep 11 05:59:06 AM UTC 24
Peak memory	219932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427254530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2427254530
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/20.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/21.keymgr_alert_test.3273980732
Short name	T551
Test name
Test status
Simulation time	21975652 ps
CPU time	1.08 seconds
Started	Sep 11 05:59:21 AM UTC 24
Finished	Sep 11 05:59:24 AM UTC 24
Peak memory	213532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273980732 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3273980732
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/21.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/21.keymgr_cfg_regwen.4269656468
Short name	T400
Test name
Test status
Simulation time	53131632 ps
CPU time	4.5 seconds
Started	Sep 11 05:59:11 AM UTC 24
Finished	Sep 11 05:59:16 AM UTC 24
Peak memory	226144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269656468 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.4269656468
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/21.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/21.keymgr_custom_cm.3875254741
Short name	T229
Test name
Test status
Simulation time	506989234 ps
CPU time	6.84 seconds
Started	Sep 11 05:59:16 AM UTC 24
Finished	Sep 11 05:59:24 AM UTC 24
Peak memory	232652 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875254741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3875254741
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/21.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/21.keymgr_direct_to_disabled.3713847606
Short name	T546
Test name
Test status
Simulation time	49685136 ps
CPU time	1.81 seconds
Started	Sep 11 05:59:12 AM UTC 24
Finished	Sep 11 05:59:15 AM UTC 24
Peak memory	217684 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713847606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3713847606
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/21.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/21.keymgr_hwsw_invalid_input.932447128
Short name	T58
Test name
Test status
Simulation time	829096253 ps
CPU time	7.9 seconds
Started	Sep 11 05:59:15 AM UTC 24
Finished	Sep 11 05:59:24 AM UTC 24
Peak memory	231720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932447128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.932447128
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/21.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/21.keymgr_kmac_rsp_err.727774276
Short name	T255
Test name
Test status
Simulation time	52519242 ps
CPU time	2.65 seconds
Started	Sep 11 05:59:15 AM UTC 24
Finished	Sep 11 05:59:19 AM UTC 24
Peak memory	230812 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727774276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.727774276
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/21.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/21.keymgr_lc_disable.2785878953
Short name	T547
Test name
Test status
Simulation time	159932987 ps
CPU time	2.78 seconds
Started	Sep 11 05:59:13 AM UTC 24
Finished	Sep 11 05:59:17 AM UTC 24
Peak memory	217888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785878953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2785878953
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/21.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/21.keymgr_random.886150481
Short name	T545
Test name
Test status
Simulation time	144250587 ps
CPU time	3.94 seconds
Started	Sep 11 05:59:08 AM UTC 24
Finished	Sep 11 05:59:13 AM UTC 24
Peak memory	224348 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886150481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.886150481
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/21.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/21.keymgr_sideload.1493248619
Short name	T388
Test name
Test status
Simulation time	407885862 ps
CPU time	5.5 seconds
Started	Sep 11 05:59:06 AM UTC 24
Finished	Sep 11 05:59:12 AM UTC 24
Peak memory	217824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493248619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1493248619
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/21.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_aes.2895353794
Short name	T543
Test name
Test status
Simulation time	67235715 ps
CPU time	3.77 seconds
Started	Sep 11 05:59:06 AM UTC 24
Finished	Sep 11 05:59:10 AM UTC 24
Peak memory	217944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895353794 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2895353794
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/21.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_kmac.3255530963
Short name	T544
Test name
Test status
Simulation time	534278701 ps
CPU time	3.99 seconds
Started	Sep 11 05:59:06 AM UTC 24
Finished	Sep 11 05:59:11 AM UTC 24
Peak memory	217984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255530963 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3255530963
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/21.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_protect.2540069035
Short name	T548
Test name
Test status
Simulation time	84821100 ps
CPU time	2.37 seconds
Started	Sep 11 05:59:17 AM UTC 24
Finished	Sep 11 05:59:21 AM UTC 24
Peak memory	218012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540069035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2540069035
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/21.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/21.keymgr_smoke.2947862122
Short name	T411
Test name
Test status
Simulation time	393672972 ps
CPU time	3.29 seconds
Started	Sep 11 05:59:03 AM UTC 24
Finished	Sep 11 05:59:07 AM UTC 24
Peak memory	216136 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947862122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2947862122
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/21.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/21.keymgr_stress_all.2895955623
Short name	T321
Test name
Test status
Simulation time	4725047526 ps
CPU time	54.42 seconds
Started	Sep 11 05:59:19 AM UTC 24
Finished	Sep 11 06:00:15 AM UTC 24
Peak memory	232372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895955623 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2895955623
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/21.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/21.keymgr_sw_invalid_input.4256712460
Short name	T550
Test name
Test status
Simulation time	482349220 ps
CPU time	8.08 seconds
Started	Sep 11 05:59:14 AM UTC 24
Finished	Sep 11 05:59:23 AM UTC 24
Peak memory	228192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256712460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.4256712460
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/21.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/21.keymgr_sync_async_fault_cross.2204886401
Short name	T549
Test name
Test status
Simulation time	54335229 ps
CPU time	2.72 seconds
Started	Sep 11 05:59:17 AM UTC 24
Finished	Sep 11 05:59:21 AM UTC 24
Peak memory	220260 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204886401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2204886401
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/21.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/22.keymgr_alert_test.2423138311
Short name	T560
Test name
Test status
Simulation time	13288987 ps
CPU time	1.02 seconds
Started	Sep 11 05:59:44 AM UTC 24
Finished	Sep 11 05:59:46 AM UTC 24
Peak memory	213532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423138311 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.2423138311
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/22.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/22.keymgr_cfg_regwen.3733435122
Short name	T280
Test name
Test status
Simulation time	235840193 ps
CPU time	7.58 seconds
Started	Sep 11 05:59:31 AM UTC 24
Finished	Sep 11 05:59:40 AM UTC 24
Peak memory	226400 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733435122 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3733435122
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/22.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/22.keymgr_custom_cm.1931430405
Short name	T559
Test name
Test status
Simulation time	184493971 ps
CPU time	4.4 seconds
Started	Sep 11 05:59:38 AM UTC 24
Finished	Sep 11 05:59:44 AM UTC 24
Peak memory	224356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931430405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1931430405
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/22.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/22.keymgr_direct_to_disabled.3833876111
Short name	T157
Test name
Test status
Simulation time	37911231 ps
CPU time	2.21 seconds
Started	Sep 11 05:59:32 AM UTC 24
Finished	Sep 11 05:59:35 AM UTC 24
Peak memory	215832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833876111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3833876111
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/22.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/22.keymgr_hwsw_invalid_input.2318331911
Short name	T62
Test name
Test status
Simulation time	2370169354 ps
CPU time	11.9 seconds
Started	Sep 11 05:59:35 AM UTC 24
Finished	Sep 11 05:59:48 AM UTC 24
Peak memory	232260 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318331911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2318331911
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/22.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/22.keymgr_lc_disable.1459469881
Short name	T230
Test name
Test status
Simulation time	136431070 ps
CPU time	3.93 seconds
Started	Sep 11 05:59:32 AM UTC 24
Finished	Sep 11 05:59:37 AM UTC 24
Peak memory	217880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459469881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1459469881
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/22.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/22.keymgr_random.1495113395
Short name	T282
Test name
Test status
Simulation time	190162364 ps
CPU time	6.31 seconds
Started	Sep 11 05:59:30 AM UTC 24
Finished	Sep 11 05:59:38 AM UTC 24
Peak memory	217872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495113395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1495113395
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/22.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/22.keymgr_sideload.2666769506
Short name	T553
Test name
Test status
Simulation time	65946802 ps
CPU time	3.56 seconds
Started	Sep 11 05:59:25 AM UTC 24
Finished	Sep 11 05:59:29 AM UTC 24
Peak memory	215832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666769506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2666769506
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/22.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_aes.3606390048
Short name	T555
Test name
Test status
Simulation time	341519309 ps
CPU time	5.41 seconds
Started	Sep 11 05:59:25 AM UTC 24
Finished	Sep 11 05:59:31 AM UTC 24
Peak memory	215900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606390048 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3606390048
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/22.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_kmac.2590139301
Short name	T554
Test name
Test status
Simulation time	502174340 ps
CPU time	5.46 seconds
Started	Sep 11 05:59:25 AM UTC 24
Finished	Sep 11 05:59:31 AM UTC 24
Peak memory	217944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590139301 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2590139301
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/22.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_otbn.2947685354
Short name	T557
Test name
Test status
Simulation time	563716888 ps
CPU time	6.85 seconds
Started	Sep 11 05:59:26 AM UTC 24
Finished	Sep 11 05:59:34 AM UTC 24
Peak memory	218204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947685354 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2947685354
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/22.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_protect.3367094138
Short name	T330
Test name
Test status
Simulation time	268224690 ps
CPU time	3.59 seconds
Started	Sep 11 05:59:38 AM UTC 24
Finished	Sep 11 05:59:43 AM UTC 24
Peak memory	226132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367094138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3367094138
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/22.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/22.keymgr_smoke.878381221
Short name	T556
Test name
Test status
Simulation time	596547914 ps
CPU time	6.78 seconds
Started	Sep 11 05:59:24 AM UTC 24
Finished	Sep 11 05:59:32 AM UTC 24
Peak memory	218076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878381221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.878381221
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/22.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/22.keymgr_sw_invalid_input.1452618686
Short name	T383
Test name
Test status
Simulation time	316272316 ps
CPU time	4.23 seconds
Started	Sep 11 05:59:33 AM UTC 24
Finished	Sep 11 05:59:39 AM UTC 24
Peak memory	218244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452618686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1452618686
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/22.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/22.keymgr_sync_async_fault_cross.1024393648
Short name	T558
Test name
Test status
Simulation time	221450747 ps
CPU time	2.29 seconds
Started	Sep 11 05:59:39 AM UTC 24
Finished	Sep 11 05:59:43 AM UTC 24
Peak memory	218388 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024393648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1024393648
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/22.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/23.keymgr_alert_test.2762633942
Short name	T567
Test name
Test status
Simulation time	13836533 ps
CPU time	1.13 seconds
Started	Sep 11 06:00:01 AM UTC 24
Finished	Sep 11 06:00:06 AM UTC 24
Peak memory	213532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762633942 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2762633942
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/23.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/23.keymgr_cfg_regwen.3083298231
Short name	T442
Test name
Test status
Simulation time	150702510 ps
CPU time	3.68 seconds
Started	Sep 11 05:59:49 AM UTC 24
Finished	Sep 11 05:59:54 AM UTC 24
Peak memory	226464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083298231 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3083298231
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/23.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/23.keymgr_custom_cm.1849710940
Short name	T32
Test name
Test status
Simulation time	269685025 ps
CPU time	2.78 seconds
Started	Sep 11 05:59:55 AM UTC 24
Finished	Sep 11 05:59:59 AM UTC 24
Peak memory	230868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849710940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1849710940
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/23.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/23.keymgr_direct_to_disabled.1033077628
Short name	T564
Test name
Test status
Simulation time	801756182 ps
CPU time	4.37 seconds
Started	Sep 11 05:59:50 AM UTC 24
Finished	Sep 11 05:59:55 AM UTC 24
Peak memory	215852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033077628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1033077628
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/23.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/23.keymgr_hwsw_invalid_input.3768797428
Short name	T238
Test name
Test status
Simulation time	295197067 ps
CPU time	6.77 seconds
Started	Sep 11 05:59:53 AM UTC 24
Finished	Sep 11 06:00:01 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768797428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3768797428
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/23.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/23.keymgr_kmac_rsp_err.101079733
Short name	T565
Test name
Test status
Simulation time	122363484 ps
CPU time	2.71 seconds
Started	Sep 11 05:59:54 AM UTC 24
Finished	Sep 11 05:59:58 AM UTC 24
Peak memory	230480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101079733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.101079733
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/23.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/23.keymgr_lc_disable.4188647312
Short name	T140
Test name
Test status
Simulation time	104658423 ps
CPU time	2.22 seconds
Started	Sep 11 05:59:51 AM UTC 24
Finished	Sep 11 05:59:54 AM UTC 24
Peak memory	224104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188647312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.4188647312
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/23.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/23.keymgr_random.2572205068
Short name	T348
Test name
Test status
Simulation time	827128259 ps
CPU time	7.51 seconds
Started	Sep 11 05:59:49 AM UTC 24
Finished	Sep 11 05:59:57 AM UTC 24
Peak memory	228188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572205068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2572205068
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/23.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/23.keymgr_sideload.2469893773
Short name	T320
Test name
Test status
Simulation time	29725302 ps
CPU time	2.64 seconds
Started	Sep 11 05:59:45 AM UTC 24
Finished	Sep 11 05:59:49 AM UTC 24
Peak memory	215832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469893773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2469893773
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/23.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_aes.1632419769
Short name	T563
Test name
Test status
Simulation time	244920622 ps
CPU time	3.93 seconds
Started	Sep 11 05:59:47 AM UTC 24
Finished	Sep 11 05:59:52 AM UTC 24
Peak memory	216152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632419769 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1632419769
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/23.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_kmac.744190502
Short name	T562
Test name
Test status
Simulation time	114192196 ps
CPU time	3.99 seconds
Started	Sep 11 05:59:45 AM UTC 24
Finished	Sep 11 05:59:50 AM UTC 24
Peak memory	215896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744190502 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.744190502
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/23.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_otbn.2928058721
Short name	T529
Test name
Test status
Simulation time	655198849 ps
CPU time	3.59 seconds
Started	Sep 11 05:59:47 AM UTC 24
Finished	Sep 11 05:59:52 AM UTC 24
Peak memory	215896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928058721 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2928058721
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/23.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_protect.1442748903
Short name	T566
Test name
Test status
Simulation time	120862553 ps
CPU time	2.44 seconds
Started	Sep 11 05:59:56 AM UTC 24
Finished	Sep 11 06:00:00 AM UTC 24
Peak memory	230548 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442748903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1442748903
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/23.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/23.keymgr_smoke.3800237368
Short name	T561
Test name
Test status
Simulation time	97225211 ps
CPU time	3.45 seconds
Started	Sep 11 05:59:44 AM UTC 24
Finished	Sep 11 05:59:48 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800237368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3800237368
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/23.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all_with_rand_reset.2008217817
Short name	T571
Test name
Test status
Simulation time	726261932 ps
CPU time	11.41 seconds
Started	Sep 11 06:00:00 AM UTC 24
Finished	Sep 11 06:00:12 AM UTC 24
Peak memory	232368 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2008217817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymg r_stress_all_with_rand_reset.2008217817
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/23.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/23.keymgr_sw_invalid_input.2311002151
Short name	T403
Test name
Test status
Simulation time	6038698011 ps
CPU time	29.7 seconds
Started	Sep 11 05:59:52 AM UTC 24
Finished	Sep 11 06:00:23 AM UTC 24
Peak memory	218272 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311002151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2311002151
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/23.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/23.keymgr_sync_async_fault_cross.4204512715
Short name	T395
Test name
Test status
Simulation time	371065402 ps
CPU time	2.57 seconds
Started	Sep 11 05:59:58 AM UTC 24
Finished	Sep 11 06:00:02 AM UTC 24
Peak memory	220260 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204512715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.4204512715
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/23.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/24.keymgr_alert_test.3782676208
Short name	T578
Test name
Test status
Simulation time	51122517 ps
CPU time	0.97 seconds
Started	Sep 11 06:00:23 AM UTC 24
Finished	Sep 11 06:00:25 AM UTC 24
Peak memory	213532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782676208 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3782676208
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/24.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/24.keymgr_cfg_regwen.42583647
Short name	T337
Test name
Test status
Simulation time	574677571 ps
CPU time	9.96 seconds
Started	Sep 11 06:00:12 AM UTC 24
Finished	Sep 11 06:00:23 AM UTC 24
Peak memory	232308 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42583647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keym gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.42583647
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/24.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/24.keymgr_custom_cm.2986633138
Short name	T20
Test name
Test status
Simulation time	86136973 ps
CPU time	2.02 seconds
Started	Sep 11 06:00:18 AM UTC 24
Finished	Sep 11 06:00:21 AM UTC 24
Peak memory	218580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986633138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2986633138
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/24.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/24.keymgr_direct_to_disabled.546703061
Short name	T574
Test name
Test status
Simulation time	163909058 ps
CPU time	3.46 seconds
Started	Sep 11 06:00:13 AM UTC 24
Finished	Sep 11 06:00:18 AM UTC 24
Peak memory	218268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546703061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.546703061
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/24.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/24.keymgr_hwsw_invalid_input.3563360396
Short name	T575
Test name
Test status
Simulation time	95192965 ps
CPU time	2.46 seconds
Started	Sep 11 06:00:16 AM UTC 24
Finished	Sep 11 06:00:20 AM UTC 24
Peak memory	226076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563360396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3563360396
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/24.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/24.keymgr_kmac_rsp_err.1103121771
Short name	T272
Test name
Test status
Simulation time	37996563 ps
CPU time	2.34 seconds
Started	Sep 11 06:00:17 AM UTC 24
Finished	Sep 11 06:00:21 AM UTC 24
Peak memory	226196 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103121771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1103121771
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/24.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/24.keymgr_random.650099903
Short name	T329
Test name
Test status
Simulation time	95633285 ps
CPU time	4.83 seconds
Started	Sep 11 06:00:11 AM UTC 24
Finished	Sep 11 06:00:17 AM UTC 24
Peak memory	215900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650099903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.650099903
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/24.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/24.keymgr_sideload.3497563477
Short name	T569
Test name
Test status
Simulation time	454215895 ps
CPU time	3.69 seconds
Started	Sep 11 06:00:06 AM UTC 24
Finished	Sep 11 06:00:10 AM UTC 24
Peak memory	217880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497563477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3497563477
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/24.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_aes.3371625450
Short name	T572
Test name
Test status
Simulation time	94591802 ps
CPU time	3.2 seconds
Started	Sep 11 06:00:10 AM UTC 24
Finished	Sep 11 06:00:14 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371625450 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3371625450
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/24.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_kmac.524385456
Short name	T570
Test name
Test status
Simulation time	55297579 ps
CPU time	3.41 seconds
Started	Sep 11 06:00:07 AM UTC 24
Finished	Sep 11 06:00:11 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524385456 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.524385456
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/24.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_otbn.2883047381
Short name	T573
Test name
Test status
Simulation time	127767227 ps
CPU time	3.74 seconds
Started	Sep 11 06:00:11 AM UTC 24
Finished	Sep 11 06:00:16 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883047381 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2883047381
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/24.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_protect.2473945106
Short name	T577
Test name
Test status
Simulation time	102589517 ps
CPU time	2.73 seconds
Started	Sep 11 06:00:20 AM UTC 24
Finished	Sep 11 06:00:24 AM UTC 24
Peak memory	224164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473945106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2473945106
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/24.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/24.keymgr_smoke.610245215
Short name	T568
Test name
Test status
Simulation time	216979957 ps
CPU time	3.31 seconds
Started	Sep 11 06:00:02 AM UTC 24
Finished	Sep 11 06:00:09 AM UTC 24
Peak memory	216092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610245215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.610245215
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/24.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all_with_rand_reset.1681248857
Short name	T584
Test name
Test status
Simulation time	142035124 ps
CPU time	9.47 seconds
Started	Sep 11 06:00:22 AM UTC 24
Finished	Sep 11 06:00:32 AM UTC 24
Peak memory	232640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1681248857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymg r_stress_all_with_rand_reset.1681248857
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/24.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/24.keymgr_sw_invalid_input.569903179
Short name	T576
Test name
Test status
Simulation time	145883086 ps
CPU time	3.39 seconds
Started	Sep 11 06:00:16 AM UTC 24
Finished	Sep 11 06:00:21 AM UTC 24
Peak memory	218208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569903179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.569903179
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/24.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/24.keymgr_sync_async_fault_cross.1570576706
Short name	T579
Test name
Test status
Simulation time	217967799 ps
CPU time	2.75 seconds
Started	Sep 11 06:00:22 AM UTC 24
Finished	Sep 11 06:00:25 AM UTC 24
Peak memory	218100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570576706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1570576706
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/24.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/25.keymgr_alert_test.74792173
Short name	T588
Test name
Test status
Simulation time	37470804 ps
CPU time	1.27 seconds
Started	Sep 11 06:00:45 AM UTC 24
Finished	Sep 11 06:00:47 AM UTC 24
Peak memory	214160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74792173 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.74792173
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/25.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/25.keymgr_custom_cm.2291932929
Short name	T21
Test name
Test status
Simulation time	95192055 ps
CPU time	4.15 seconds
Started	Sep 11 06:00:37 AM UTC 24
Finished	Sep 11 06:00:43 AM UTC 24
Peak memory	218296 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291932929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2291932929
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/25.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/25.keymgr_direct_to_disabled.942720511
Short name	T586
Test name
Test status
Simulation time	637028396 ps
CPU time	6.58 seconds
Started	Sep 11 06:00:30 AM UTC 24
Finished	Sep 11 06:00:38 AM UTC 24
Peak memory	217876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942720511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.942720511
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/25.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/25.keymgr_hwsw_invalid_input.3186936463
Short name	T240
Test name
Test status
Simulation time	442704560 ps
CPU time	4.98 seconds
Started	Sep 11 06:00:37 AM UTC 24
Finished	Sep 11 06:00:43 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186936463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3186936463
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/25.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/25.keymgr_kmac_rsp_err.647321823
Short name	T256
Test name
Test status
Simulation time	229114516 ps
CPU time	3.47 seconds
Started	Sep 11 06:00:37 AM UTC 24
Finished	Sep 11 06:00:42 AM UTC 24
Peak memory	224104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647321823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.647321823
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/25.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/25.keymgr_lc_disable.2793107337
Short name	T585
Test name
Test status
Simulation time	263347446 ps
CPU time	3.89 seconds
Started	Sep 11 06:00:31 AM UTC 24
Finished	Sep 11 06:00:36 AM UTC 24
Peak memory	217972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793107337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2793107337
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/25.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/25.keymgr_random.4291323128
Short name	T267
Test name
Test status
Simulation time	1156855356 ps
CPU time	6.6 seconds
Started	Sep 11 06:00:29 AM UTC 24
Finished	Sep 11 06:00:37 AM UTC 24
Peak memory	218212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291323128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.4291323128
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/25.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/25.keymgr_sideload.3994987538
Short name	T580
Test name
Test status
Simulation time	58665607 ps
CPU time	3.37 seconds
Started	Sep 11 06:00:24 AM UTC 24
Finished	Sep 11 06:00:28 AM UTC 24
Peak memory	215840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994987538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3994987538
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/25.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_aes.3845566589
Short name	T582
Test name
Test status
Simulation time	33847446 ps
CPU time	2.76 seconds
Started	Sep 11 06:00:26 AM UTC 24
Finished	Sep 11 06:00:30 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845566589 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3845566589
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/25.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_kmac.4154415802
Short name	T607
Test name
Test status
Simulation time	5435402403 ps
CPU time	55.22 seconds
Started	Sep 11 06:00:25 AM UTC 24
Finished	Sep 11 06:01:22 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154415802 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.4154415802
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/25.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_otbn.2371341486
Short name	T583
Test name
Test status
Simulation time	237084675 ps
CPU time	3.62 seconds
Started	Sep 11 06:00:26 AM UTC 24
Finished	Sep 11 06:00:31 AM UTC 24
Peak memory	217944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371341486 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2371341486
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/25.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/25.keymgr_smoke.3074670592
Short name	T581
Test name
Test status
Simulation time	1361501559 ps
CPU time	4.01 seconds
Started	Sep 11 06:00:24 AM UTC 24
Finished	Sep 11 06:00:29 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074670592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3074670592
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/25.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/25.keymgr_stress_all.4292192661
Short name	T199
Test name
Test status
Simulation time	6699646820 ps
CPU time	48.66 seconds
Started	Sep 11 06:00:43 AM UTC 24
Finished	Sep 11 06:01:33 AM UTC 24
Peak memory	232236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292192661 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.4292192661
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/25.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/25.keymgr_stress_all_with_rand_reset.1468321564
Short name	T596
Test name
Test status
Simulation time	475586160 ps
CPU time	19.62 seconds
Started	Sep 11 06:00:44 AM UTC 24
Finished	Sep 11 06:01:04 AM UTC 24
Peak memory	232332 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1468321564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymg r_stress_all_with_rand_reset.1468321564
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/25.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/25.keymgr_sw_invalid_input.2011447920
Short name	T587
Test name
Test status
Simulation time	352318605 ps
CPU time	7.33 seconds
Started	Sep 11 06:00:33 AM UTC 24
Finished	Sep 11 06:00:42 AM UTC 24
Peak memory	224096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011447920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2011447920
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/25.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/25.keymgr_sync_async_fault_cross.1180106631
Short name	T589
Test name
Test status
Simulation time	279522840 ps
CPU time	3.57 seconds
Started	Sep 11 06:00:43 AM UTC 24
Finished	Sep 11 06:00:47 AM UTC 24
Peak memory	217992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180106631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1180106631
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/25.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/26.keymgr_alert_test.4189253940
Short name	T603
Test name
Test status
Simulation time	43293343 ps
CPU time	1.19 seconds
Started	Sep 11 06:01:13 AM UTC 24
Finished	Sep 11 06:01:15 AM UTC 24
Peak memory	213528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189253940 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.4189253940
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/26.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/26.keymgr_cfg_regwen.3284644228
Short name	T325
Test name
Test status
Simulation time	5150434544 ps
CPU time	71.72 seconds
Started	Sep 11 06:00:57 AM UTC 24
Finished	Sep 11 06:02:11 AM UTC 24
Peak memory	226284 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284644228 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3284644228
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/26.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/26.keymgr_custom_cm.3333702237
Short name	T39
Test name
Test status
Simulation time	120844486 ps
CPU time	5.06 seconds
Started	Sep 11 06:01:08 AM UTC 24
Finished	Sep 11 06:01:15 AM UTC 24
Peak memory	218312 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333702237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3333702237
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/26.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/26.keymgr_direct_to_disabled.3359800560
Short name	T595
Test name
Test status
Simulation time	158312558 ps
CPU time	4.15 seconds
Started	Sep 11 06:00:58 AM UTC 24
Finished	Sep 11 06:01:03 AM UTC 24
Peak memory	226072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359800560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3359800560
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/26.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/26.keymgr_hwsw_invalid_input.3220992469
Short name	T597
Test name
Test status
Simulation time	34301712 ps
CPU time	1.82 seconds
Started	Sep 11 06:01:04 AM UTC 24
Finished	Sep 11 06:01:07 AM UTC 24
Peak memory	224408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220992469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3220992469
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/26.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/26.keymgr_kmac_rsp_err.2651131663
Short name	T335
Test name
Test status
Simulation time	115450728 ps
CPU time	3.43 seconds
Started	Sep 11 06:01:05 AM UTC 24
Finished	Sep 11 06:01:10 AM UTC 24
Peak memory	232180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651131663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2651131663
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/26.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/26.keymgr_lc_disable.3314506767
Short name	T598
Test name
Test status
Simulation time	48685593 ps
CPU time	2.94 seconds
Started	Sep 11 06:01:03 AM UTC 24
Finished	Sep 11 06:01:08 AM UTC 24
Peak memory	228156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314506767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3314506767
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/26.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/26.keymgr_random.58506699
Short name	T599
Test name
Test status
Simulation time	1281125678 ps
CPU time	9.61 seconds
Started	Sep 11 06:00:57 AM UTC 24
Finished	Sep 11 06:01:08 AM UTC 24
Peak memory	216160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58506699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.58506699
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/26.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/26.keymgr_sideload.1184987567
Short name	T591
Test name
Test status
Simulation time	96750079 ps
CPU time	2.94 seconds
Started	Sep 11 06:00:48 AM UTC 24
Finished	Sep 11 06:00:52 AM UTC 24
Peak memory	215832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184987567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1184987567
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/26.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_aes.531547831
Short name	T593
Test name
Test status
Simulation time	239806330 ps
CPU time	4.08 seconds
Started	Sep 11 06:00:52 AM UTC 24
Finished	Sep 11 06:00:57 AM UTC 24
Peak memory	217984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531547831 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.531547831
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/26.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_kmac.2945674979
Short name	T590
Test name
Test status
Simulation time	20449881 ps
CPU time	2.13 seconds
Started	Sep 11 06:00:48 AM UTC 24
Finished	Sep 11 06:00:51 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945674979 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2945674979
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/26.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_otbn.1978775501
Short name	T592
Test name
Test status
Simulation time	33240114 ps
CPU time	2.68 seconds
Started	Sep 11 06:00:53 AM UTC 24
Finished	Sep 11 06:00:57 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978775501 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1978775501
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/26.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_protect.3311384726
Short name	T601
Test name
Test status
Simulation time	27423442 ps
CPU time	2.36 seconds
Started	Sep 11 06:01:09 AM UTC 24
Finished	Sep 11 06:01:12 AM UTC 24
Peak memory	226212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311384726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3311384726
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/26.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/26.keymgr_smoke.3597561062
Short name	T594
Test name
Test status
Simulation time	2213769553 ps
CPU time	14.23 seconds
Started	Sep 11 06:00:48 AM UTC 24
Finished	Sep 11 06:01:03 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597561062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3597561062
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/26.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/26.keymgr_stress_all.1284626490
Short name	T237
Test name
Test status
Simulation time	2571564097 ps
CPU time	41.58 seconds
Started	Sep 11 06:01:11 AM UTC 24
Finished	Sep 11 06:01:54 AM UTC 24
Peak memory	231400 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284626490 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1284626490
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/26.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/26.keymgr_sw_invalid_input.4044077994
Short name	T600
Test name
Test status
Simulation time	179700272 ps
CPU time	5.18 seconds
Started	Sep 11 06:01:04 AM UTC 24
Finished	Sep 11 06:01:11 AM UTC 24
Peak memory	216160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044077994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.4044077994
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/26.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/26.keymgr_sync_async_fault_cross.2219234244
Short name	T602
Test name
Test status
Simulation time	388781944 ps
CPU time	3.32 seconds
Started	Sep 11 06:01:10 AM UTC 24
Finished	Sep 11 06:01:14 AM UTC 24
Peak memory	220004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219234244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2219234244
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/26.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/27.keymgr_alert_test.3523449884
Short name	T613
Test name
Test status
Simulation time	54807505 ps
CPU time	0.93 seconds
Started	Sep 11 06:01:36 AM UTC 24
Finished	Sep 11 06:01:38 AM UTC 24
Peak memory	214164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523449884 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3523449884
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/27.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/27.keymgr_cfg_regwen.2866943389
Short name	T242
Test name
Test status
Simulation time	189095904 ps
CPU time	10.33 seconds
Started	Sep 11 06:01:22 AM UTC 24
Finished	Sep 11 06:01:34 AM UTC 24
Peak memory	226144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866943389 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2866943389
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/27.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/27.keymgr_direct_to_disabled.2424341866
Short name	T610
Test name
Test status
Simulation time	414578029 ps
CPU time	6.05 seconds
Started	Sep 11 06:01:22 AM UTC 24
Finished	Sep 11 06:01:29 AM UTC 24
Peak memory	220252 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424341866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2424341866
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/27.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/27.keymgr_hwsw_invalid_input.3299178042
Short name	T305
Test name
Test status
Simulation time	484800638 ps
CPU time	5.02 seconds
Started	Sep 11 06:01:29 AM UTC 24
Finished	Sep 11 06:01:35 AM UTC 24
Peak memory	226076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299178042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3299178042
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/27.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/27.keymgr_random.1130272000
Short name	T608
Test name
Test status
Simulation time	206566426 ps
CPU time	3.45 seconds
Started	Sep 11 06:01:20 AM UTC 24
Finished	Sep 11 06:01:25 AM UTC 24
Peak memory	216228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130272000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1130272000
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/27.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/27.keymgr_sideload.3156715606
Short name	T605
Test name
Test status
Simulation time	196076032 ps
CPU time	2.05 seconds
Started	Sep 11 06:01:16 AM UTC 24
Finished	Sep 11 06:01:19 AM UTC 24
Peak memory	215940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156715606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3156715606
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/27.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_aes.4104469028
Short name	T614
Test name
Test status
Simulation time	635063188 ps
CPU time	17.37 seconds
Started	Sep 11 06:01:20 AM UTC 24
Finished	Sep 11 06:01:39 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104469028 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.4104469028
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/27.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_kmac.2390202332
Short name	T606
Test name
Test status
Simulation time	99699046 ps
CPU time	4.17 seconds
Started	Sep 11 06:01:16 AM UTC 24
Finished	Sep 11 06:01:21 AM UTC 24
Peak memory	218076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390202332 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2390202332
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/27.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_otbn.885599980
Short name	T609
Test name
Test status
Simulation time	387035106 ps
CPU time	5.27 seconds
Started	Sep 11 06:01:20 AM UTC 24
Finished	Sep 11 06:01:26 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885599980 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.885599980
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/27.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_protect.2173704584
Short name	T612
Test name
Test status
Simulation time	40387536 ps
CPU time	2.07 seconds
Started	Sep 11 06:01:34 AM UTC 24
Finished	Sep 11 06:01:37 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173704584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2173704584
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/27.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/27.keymgr_smoke.2220652074
Short name	T604
Test name
Test status
Simulation time	62693830 ps
CPU time	2.85 seconds
Started	Sep 11 06:01:15 AM UTC 24
Finished	Sep 11 06:01:19 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220652074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2220652074
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/27.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/27.keymgr_stress_all_with_rand_reset.3886976496
Short name	T184
Test name
Test status
Simulation time	231797103 ps
CPU time	9.16 seconds
Started	Sep 11 06:01:36 AM UTC 24
Finished	Sep 11 06:01:46 AM UTC 24
Peak memory	232380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3886976496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymg r_stress_all_with_rand_reset.3886976496
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/27.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/27.keymgr_sw_invalid_input.1534514836
Short name	T611
Test name
Test status
Simulation time	80971804 ps
CPU time	4.2 seconds
Started	Sep 11 06:01:27 AM UTC 24
Finished	Sep 11 06:01:33 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534514836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1534514836
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/27.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/27.keymgr_sync_async_fault_cross.2235939692
Short name	T396
Test name
Test status
Simulation time	106297499 ps
CPU time	1.41 seconds
Started	Sep 11 06:01:35 AM UTC 24
Finished	Sep 11 06:01:37 AM UTC 24
Peak memory	217564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235939692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2235939692
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/27.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/28.keymgr_alert_test.3454067770
Short name	T623
Test name
Test status
Simulation time	89332530 ps
CPU time	1.03 seconds
Started	Sep 11 06:02:01 AM UTC 24
Finished	Sep 11 06:02:03 AM UTC 24
Peak memory	213532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454067770 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3454067770
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/28.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/28.keymgr_custom_cm.1462019810
Short name	T622
Test name
Test status
Simulation time	244002131 ps
CPU time	7.6 seconds
Started	Sep 11 06:01:52 AM UTC 24
Finished	Sep 11 06:02:00 AM UTC 24
Peak memory	231356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462019810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1462019810
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/28.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/28.keymgr_direct_to_disabled.47391165
Short name	T619
Test name
Test status
Simulation time	121698361 ps
CPU time	4.47 seconds
Started	Sep 11 06:01:44 AM UTC 24
Finished	Sep 11 06:01:50 AM UTC 24
Peak memory	224068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47391165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.47391165
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/28.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/28.keymgr_hwsw_invalid_input.1093307527
Short name	T55
Test name
Test status
Simulation time	4048348066 ps
CPU time	26.49 seconds
Started	Sep 11 06:01:48 AM UTC 24
Finished	Sep 11 06:02:16 AM UTC 24
Peak memory	226132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093307527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1093307527
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/28.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/28.keymgr_kmac_rsp_err.1866384472
Short name	T620
Test name
Test status
Simulation time	539756057 ps
CPU time	4.57 seconds
Started	Sep 11 06:01:50 AM UTC 24
Finished	Sep 11 06:01:56 AM UTC 24
Peak memory	223968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866384472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1866384472
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/28.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/28.keymgr_random.4260520604
Short name	T386
Test name
Test status
Simulation time	7780983016 ps
CPU time	66.95 seconds
Started	Sep 11 06:01:42 AM UTC 24
Finished	Sep 11 06:02:51 AM UTC 24
Peak memory	218020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260520604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.4260520604
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/28.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/28.keymgr_sideload.3168974925
Short name	T349
Test name
Test status
Simulation time	106798655 ps
CPU time	3.69 seconds
Started	Sep 11 06:01:38 AM UTC 24
Finished	Sep 11 06:01:43 AM UTC 24
Peak memory	218184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168974925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3168974925
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/28.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_aes.2884167595
Short name	T618
Test name
Test status
Simulation time	567185187 ps
CPU time	7.33 seconds
Started	Sep 11 06:01:39 AM UTC 24
Finished	Sep 11 06:01:47 AM UTC 24
Peak memory	217968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884167595 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2884167595
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/28.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_kmac.1637470805
Short name	T615
Test name
Test status
Simulation time	76243121 ps
CPU time	2.13 seconds
Started	Sep 11 06:01:38 AM UTC 24
Finished	Sep 11 06:01:41 AM UTC 24
Peak memory	215816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637470805 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1637470805
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/28.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_otbn.3462007754
Short name	T617
Test name
Test status
Simulation time	171072035 ps
CPU time	3.77 seconds
Started	Sep 11 06:01:39 AM UTC 24
Finished	Sep 11 06:01:44 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462007754 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3462007754
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/28.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_protect.1851745558
Short name	T621
Test name
Test status
Simulation time	281298048 ps
CPU time	3.73 seconds
Started	Sep 11 06:01:55 AM UTC 24
Finished	Sep 11 06:01:59 AM UTC 24
Peak memory	218020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851745558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1851745558
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/28.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/28.keymgr_smoke.1070784834
Short name	T616
Test name
Test status
Simulation time	175385757 ps
CPU time	4.1 seconds
Started	Sep 11 06:01:38 AM UTC 24
Finished	Sep 11 06:01:43 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070784834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1070784834
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/28.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all_with_rand_reset.3487194873
Short name	T626
Test name
Test status
Simulation time	521080199 ps
CPU time	12.93 seconds
Started	Sep 11 06:02:00 AM UTC 24
Finished	Sep 11 06:02:14 AM UTC 24
Peak memory	232468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3487194873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymg r_stress_all_with_rand_reset.3487194873
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/28.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/28.keymgr_sw_invalid_input.4020605807
Short name	T359
Test name
Test status
Simulation time	1024379587 ps
CPU time	7.98 seconds
Started	Sep 11 06:01:47 AM UTC 24
Finished	Sep 11 06:01:56 AM UTC 24
Peak memory	218280 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020605807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.4020605807
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/28.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/28.keymgr_sync_async_fault_cross.4193551022
Short name	T638
Test name
Test status
Simulation time	4665065875 ps
CPU time	31.41 seconds
Started	Sep 11 06:01:57 AM UTC 24
Finished	Sep 11 06:02:30 AM UTC 24
Peak memory	219996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193551022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.4193551022
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/28.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/29.keymgr_alert_test.802735666
Short name	T637
Test name
Test status
Simulation time	69036002 ps
CPU time	0.93 seconds
Started	Sep 11 06:02:27 AM UTC 24
Finished	Sep 11 06:02:29 AM UTC 24
Peak memory	214228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802735666 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.802735666
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/29.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/29.keymgr_cfg_regwen.2835806554
Short name	T441
Test name
Test status
Simulation time	70479283 ps
CPU time	2.98 seconds
Started	Sep 11 06:02:15 AM UTC 24
Finished	Sep 11 06:02:19 AM UTC 24
Peak memory	224096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835806554 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2835806554
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/29.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/29.keymgr_custom_cm.1523102104
Short name	T636
Test name
Test status
Simulation time	498921968 ps
CPU time	4.26 seconds
Started	Sep 11 06:02:22 AM UTC 24
Finished	Sep 11 06:02:27 AM UTC 24
Peak memory	218484 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523102104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1523102104
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/29.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/29.keymgr_direct_to_disabled.2904362546
Short name	T630
Test name
Test status
Simulation time	317865348 ps
CPU time	2.57 seconds
Started	Sep 11 06:02:17 AM UTC 24
Finished	Sep 11 06:02:21 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904362546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2904362546
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/29.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/29.keymgr_hwsw_invalid_input.3849665464
Short name	T633
Test name
Test status
Simulation time	194327255 ps
CPU time	2.88 seconds
Started	Sep 11 06:02:20 AM UTC 24
Finished	Sep 11 06:02:23 AM UTC 24
Peak memory	224136 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849665464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3849665464
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/29.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/29.keymgr_kmac_rsp_err.4127678781
Short name	T373
Test name
Test status
Simulation time	75254164 ps
CPU time	2.1 seconds
Started	Sep 11 06:02:20 AM UTC 24
Finished	Sep 11 06:02:23 AM UTC 24
Peak memory	224032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127678781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.4127678781
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/29.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/29.keymgr_lc_disable.531077871
Short name	T634
Test name
Test status
Simulation time	233972898 ps
CPU time	8.03 seconds
Started	Sep 11 06:02:17 AM UTC 24
Finished	Sep 11 06:02:27 AM UTC 24
Peak memory	232260 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531077871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.531077871
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/29.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/29.keymgr_random.2322093207
Short name	T631
Test name
Test status
Simulation time	514292991 ps
CPU time	5.92 seconds
Started	Sep 11 06:02:15 AM UTC 24
Finished	Sep 11 06:02:22 AM UTC 24
Peak memory	217884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322093207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2322093207
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/29.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/29.keymgr_sideload.1883657511
Short name	T625
Test name
Test status
Simulation time	103353762 ps
CPU time	3.72 seconds
Started	Sep 11 06:02:09 AM UTC 24
Finished	Sep 11 06:02:14 AM UTC 24
Peak memory	216160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883657511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1883657511
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/29.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_aes.1000410577
Short name	T627
Test name
Test status
Simulation time	237429705 ps
CPU time	3.33 seconds
Started	Sep 11 06:02:12 AM UTC 24
Finished	Sep 11 06:02:16 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000410577 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1000410577
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/29.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_kmac.1488665039
Short name	T629
Test name
Test status
Simulation time	886680523 ps
CPU time	7.58 seconds
Started	Sep 11 06:02:10 AM UTC 24
Finished	Sep 11 06:02:19 AM UTC 24
Peak memory	217988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488665039 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1488665039
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/29.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_otbn.1140658973
Short name	T628
Test name
Test status
Simulation time	47920859 ps
CPU time	2.27 seconds
Started	Sep 11 06:02:14 AM UTC 24
Finished	Sep 11 06:02:17 AM UTC 24
Peak memory	218048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140658973 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1140658973
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/29.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_protect.4278015398
Short name	T635
Test name
Test status
Simulation time	39544043 ps
CPU time	3.18 seconds
Started	Sep 11 06:02:23 AM UTC 24
Finished	Sep 11 06:02:27 AM UTC 24
Peak memory	226316 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278015398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.4278015398
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/29.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/29.keymgr_smoke.3501933742
Short name	T624
Test name
Test status
Simulation time	294285419 ps
CPU time	3.78 seconds
Started	Sep 11 06:02:04 AM UTC 24
Finished	Sep 11 06:02:09 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501933742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3501933742
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/29.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all_with_rand_reset.3939957359
Short name	T287
Test name
Test status
Simulation time	258633850 ps
CPU time	18.09 seconds
Started	Sep 11 06:02:24 AM UTC 24
Finished	Sep 11 06:02:43 AM UTC 24
Peak memory	232628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3939957359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymg r_stress_all_with_rand_reset.3939957359
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/29.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/29.keymgr_sw_invalid_input.2318766914
Short name	T632
Test name
Test status
Simulation time	140409970 ps
CPU time	3.63 seconds
Started	Sep 11 06:02:19 AM UTC 24
Finished	Sep 11 06:02:23 AM UTC 24
Peak memory	215896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318766914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2318766914
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/29.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/29.keymgr_sync_async_fault_cross.2255215485
Short name	T180
Test name
Test status
Simulation time	98173517 ps
CPU time	1.88 seconds
Started	Sep 11 06:02:24 AM UTC 24
Finished	Sep 11 06:02:27 AM UTC 24
Peak memory	217532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255215485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2255215485
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/29.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/3.keymgr_alert_test.3776629191
Short name	T443
Test name
Test status
Simulation time	25216941 ps
CPU time	1.12 seconds
Started	Sep 11 05:50:43 AM UTC 24
Finished	Sep 11 05:50:45 AM UTC 24
Peak memory	213600 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776629191 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3776629191
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/3.keymgr_cfg_regwen.3367259296
Short name	T126
Test name
Test status
Simulation time	83710196 ps
CPU time	3.66 seconds
Started	Sep 11 05:50:26 AM UTC 24
Finished	Sep 11 05:50:31 AM UTC 24
Peak memory	226068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367259296 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3367259296
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/3.keymgr_direct_to_disabled.3376748554
Short name	T137
Test name
Test status
Simulation time	306613817 ps
CPU time	4.76 seconds
Started	Sep 11 05:50:27 AM UTC 24
Finished	Sep 11 05:50:33 AM UTC 24
Peak memory	230244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376748554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3376748554
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/3.keymgr_hwsw_invalid_input.1945246558
Short name	T53
Test name
Test status
Simulation time	43173800 ps
CPU time	2.84 seconds
Started	Sep 11 05:50:32 AM UTC 24
Finished	Sep 11 05:50:35 AM UTC 24
Peak memory	226144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945246558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1945246558
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/3.keymgr_kmac_rsp_err.1123371701
Short name	T70
Test name
Test status
Simulation time	52732265 ps
CPU time	3.23 seconds
Started	Sep 11 05:50:34 AM UTC 24
Finished	Sep 11 05:50:38 AM UTC 24
Peak memory	224080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123371701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1123371701
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/3.keymgr_lc_disable.2471442954
Short name	T149
Test name
Test status
Simulation time	40462689 ps
CPU time	3.53 seconds
Started	Sep 11 05:50:29 AM UTC 24
Finished	Sep 11 05:50:33 AM UTC 24
Peak memory	217880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471442954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2471442954
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/3.keymgr_random.2664663084
Short name	T254
Test name
Test status
Simulation time	341990201 ps
CPU time	4.55 seconds
Started	Sep 11 05:50:25 AM UTC 24
Finished	Sep 11 05:50:31 AM UTC 24
Peak memory	226148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664663084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2664663084
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/3.keymgr_sideload.1579127949
Short name	T211
Test name
Test status
Simulation time	422892562 ps
CPU time	5.85 seconds
Started	Sep 11 05:50:18 AM UTC 24
Finished	Sep 11 05:50:25 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579127949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1579127949
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_aes.3429836590
Short name	T213
Test name
Test status
Simulation time	151401715 ps
CPU time	3.51 seconds
Started	Sep 11 05:50:23 AM UTC 24
Finished	Sep 11 05:50:28 AM UTC 24
Peak memory	218036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429836590 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3429836590
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_kmac.3363088979
Short name	T214
Test name
Test status
Simulation time	157910456 ps
CPU time	4.22 seconds
Started	Sep 11 05:50:20 AM UTC 24
Finished	Sep 11 05:50:25 AM UTC 24
Peak memory	218268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363088979 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3363088979
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_otbn.4175794571
Short name	T323
Test name
Test status
Simulation time	19860830 ps
CPU time	2.22 seconds
Started	Sep 11 05:50:23 AM UTC 24
Finished	Sep 11 05:50:26 AM UTC 24
Peak memory	215900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175794571 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.4175794571
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_protect.1675038986
Short name	T205
Test name
Test status
Simulation time	138823222 ps
CPU time	5.03 seconds
Started	Sep 11 05:50:36 AM UTC 24
Finished	Sep 11 05:50:42 AM UTC 24
Peak memory	218212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675038986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1675038986
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/3.keymgr_smoke.3461671677
Short name	T203
Test name
Test status
Simulation time	1357577450 ps
CPU time	6.43 seconds
Started	Sep 11 05:50:15 AM UTC 24
Finished	Sep 11 05:50:22 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461671677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3461671677
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/3.keymgr_sw_invalid_input.3529985425
Short name	T207
Test name
Test status
Simulation time	131949464 ps
CPU time	3.89 seconds
Started	Sep 11 05:50:32 AM UTC 24
Finished	Sep 11 05:50:36 AM UTC 24
Peak memory	218208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529985425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3529985425
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/3.keymgr_sync_async_fault_cross.2087896967
Short name	T41
Test name
Test status
Simulation time	137919215 ps
CPU time	2.71 seconds
Started	Sep 11 05:50:37 AM UTC 24
Finished	Sep 11 05:50:41 AM UTC 24
Peak memory	218068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087896967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2087896967
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/30.keymgr_alert_test.1356562134
Short name	T646
Test name
Test status
Simulation time	23736092 ps
CPU time	0.92 seconds
Started	Sep 11 06:02:47 AM UTC 24
Finished	Sep 11 06:02:49 AM UTC 24
Peak memory	214164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356562134 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1356562134
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/30.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/30.keymgr_cfg_regwen.4116128616
Short name	T434
Test name
Test status
Simulation time	131738356 ps
CPU time	3.67 seconds
Started	Sep 11 06:02:33 AM UTC 24
Finished	Sep 11 06:02:38 AM UTC 24
Peak memory	226144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116128616 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.4116128616
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/30.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/30.keymgr_custom_cm.3840658523
Short name	T649
Test name
Test status
Simulation time	650646954 ps
CPU time	13.04 seconds
Started	Sep 11 06:02:41 AM UTC 24
Finished	Sep 11 06:02:55 AM UTC 24
Peak memory	218372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840658523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3840658523
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/30.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/30.keymgr_direct_to_disabled.2514317100
Short name	T354
Test name
Test status
Simulation time	182189190 ps
CPU time	2.17 seconds
Started	Sep 11 06:02:34 AM UTC 24
Finished	Sep 11 06:02:38 AM UTC 24
Peak memory	215832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514317100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2514317100
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/30.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/30.keymgr_kmac_rsp_err.132115849
Short name	T376
Test name
Test status
Simulation time	528286645 ps
CPU time	4.58 seconds
Started	Sep 11 06:02:39 AM UTC 24
Finished	Sep 11 06:02:45 AM UTC 24
Peak memory	224040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132115849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.132115849
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/30.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/30.keymgr_random.670629763
Short name	T644
Test name
Test status
Simulation time	492474684 ps
CPU time	5.67 seconds
Started	Sep 11 06:02:33 AM UTC 24
Finished	Sep 11 06:02:40 AM UTC 24
Peak memory	224092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670629763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.670629763
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/30.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/30.keymgr_sideload.344647369
Short name	T639
Test name
Test status
Simulation time	70324445 ps
CPU time	3.37 seconds
Started	Sep 11 06:02:28 AM UTC 24
Finished	Sep 11 06:02:32 AM UTC 24
Peak memory	217872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344647369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.344647369
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/30.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_aes.197279257
Short name	T643
Test name
Test status
Simulation time	161657596 ps
CPU time	6.54 seconds
Started	Sep 11 06:02:29 AM UTC 24
Finished	Sep 11 06:02:37 AM UTC 24
Peak memory	217876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197279257 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.197279257
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/30.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_kmac.1124627955
Short name	T641
Test name
Test status
Simulation time	102768530 ps
CPU time	3.87 seconds
Started	Sep 11 06:02:28 AM UTC 24
Finished	Sep 11 06:02:33 AM UTC 24
Peak memory	217980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124627955 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1124627955
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/30.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_otbn.4059008718
Short name	T642
Test name
Test status
Simulation time	472601412 ps
CPU time	3.49 seconds
Started	Sep 11 06:02:30 AM UTC 24
Finished	Sep 11 06:02:35 AM UTC 24
Peak memory	216152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059008718 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.4059008718
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/30.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_protect.3653332802
Short name	T322
Test name
Test status
Simulation time	2114716828 ps
CPU time	24.44 seconds
Started	Sep 11 06:02:41 AM UTC 24
Finished	Sep 11 06:03:06 AM UTC 24
Peak memory	218368 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653332802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3653332802
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/30.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/30.keymgr_smoke.3371277681
Short name	T640
Test name
Test status
Simulation time	351931186 ps
CPU time	3.8 seconds
Started	Sep 11 06:02:28 AM UTC 24
Finished	Sep 11 06:02:33 AM UTC 24
Peak memory	217904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371277681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3371277681
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/30.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all_with_rand_reset.1286281093
Short name	T185
Test name
Test status
Simulation time	972151577 ps
CPU time	21.22 seconds
Started	Sep 11 06:02:46 AM UTC 24
Finished	Sep 11 06:03:09 AM UTC 24
Peak memory	232624 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1286281093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymg r_stress_all_with_rand_reset.1286281093
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/30.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/30.keymgr_sw_invalid_input.2997516898
Short name	T645
Test name
Test status
Simulation time	199529533 ps
CPU time	5.55 seconds
Started	Sep 11 06:02:37 AM UTC 24
Finished	Sep 11 06:02:44 AM UTC 24
Peak memory	230608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997516898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2997516898
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/30.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/30.keymgr_sync_async_fault_cross.2072646961
Short name	T647
Test name
Test status
Simulation time	1247497802 ps
CPU time	6.04 seconds
Started	Sep 11 06:02:44 AM UTC 24
Finished	Sep 11 06:02:51 AM UTC 24
Peak memory	219928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072646961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2072646961
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/30.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/31.keymgr_alert_test.2266907156
Short name	T657
Test name
Test status
Simulation time	9565930 ps
CPU time	0.98 seconds
Started	Sep 11 06:03:10 AM UTC 24
Finished	Sep 11 06:03:12 AM UTC 24
Peak memory	213532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266907156 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2266907156
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/31.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/31.keymgr_cfg_regwen.3174197819
Short name	T433
Test name
Test status
Simulation time	338156600 ps
CPU time	2.64 seconds
Started	Sep 11 06:02:57 AM UTC 24
Finished	Sep 11 06:03:01 AM UTC 24
Peak memory	224132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174197819 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3174197819
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/31.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/31.keymgr_custom_cm.2459671569
Short name	T656
Test name
Test status
Simulation time	92050063 ps
CPU time	3.88 seconds
Started	Sep 11 06:03:05 AM UTC 24
Finished	Sep 11 06:03:10 AM UTC 24
Peak memory	231184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459671569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2459671569
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/31.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/31.keymgr_direct_to_disabled.2030217506
Short name	T654
Test name
Test status
Simulation time	122297809 ps
CPU time	2.66 seconds
Started	Sep 11 06:02:59 AM UTC 24
Finished	Sep 11 06:03:03 AM UTC 24
Peak memory	216160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030217506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2030217506
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/31.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/31.keymgr_hwsw_invalid_input.3702377192
Short name	T392
Test name
Test status
Simulation time	53747502 ps
CPU time	2.13 seconds
Started	Sep 11 06:03:03 AM UTC 24
Finished	Sep 11 06:03:06 AM UTC 24
Peak memory	226468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702377192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3702377192
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/31.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/31.keymgr_kmac_rsp_err.279372320
Short name	T356
Test name
Test status
Simulation time	38230625 ps
CPU time	2.37 seconds
Started	Sep 11 06:03:04 AM UTC 24
Finished	Sep 11 06:03:07 AM UTC 24
Peak memory	232448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279372320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.279372320
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/31.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/31.keymgr_lc_disable.1484127995
Short name	T655
Test name
Test status
Simulation time	62022850 ps
CPU time	2.81 seconds
Started	Sep 11 06:03:00 AM UTC 24
Finished	Sep 11 06:03:04 AM UTC 24
Peak memory	230500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484127995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1484127995
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/31.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/31.keymgr_random.2617828117
Short name	T653
Test name
Test status
Simulation time	79115801 ps
CPU time	4.52 seconds
Started	Sep 11 06:02:56 AM UTC 24
Finished	Sep 11 06:03:02 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617828117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2617828117
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/31.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/31.keymgr_sideload.3937188544
Short name	T650
Test name
Test status
Simulation time	232597605 ps
CPU time	3.23 seconds
Started	Sep 11 06:02:52 AM UTC 24
Finished	Sep 11 06:02:56 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937188544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3937188544
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/31.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_aes.1316154374
Short name	T675
Test name
Test status
Simulation time	4281607987 ps
CPU time	46.23 seconds
Started	Sep 11 06:02:54 AM UTC 24
Finished	Sep 11 06:03:42 AM UTC 24
Peak memory	218272 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316154374 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1316154374
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/31.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_kmac.2357618689
Short name	T652
Test name
Test status
Simulation time	192730973 ps
CPU time	6.14 seconds
Started	Sep 11 06:02:52 AM UTC 24
Finished	Sep 11 06:02:59 AM UTC 24
Peak memory	215900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357618689 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2357618689
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/31.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_otbn.4219043616
Short name	T651
Test name
Test status
Simulation time	97232666 ps
CPU time	2.28 seconds
Started	Sep 11 06:02:55 AM UTC 24
Finished	Sep 11 06:02:59 AM UTC 24
Peak memory	218216 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219043616 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.4219043616
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/31.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_protect.620684636
Short name	T658
Test name
Test status
Simulation time	290224885 ps
CPU time	4.6 seconds
Started	Sep 11 06:03:07 AM UTC 24
Finished	Sep 11 06:03:12 AM UTC 24
Peak memory	218080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620684636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.620684636
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/31.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/31.keymgr_smoke.2120866573
Short name	T648
Test name
Test status
Simulation time	58708200 ps
CPU time	3.06 seconds
Started	Sep 11 06:02:50 AM UTC 24
Finished	Sep 11 06:02:54 AM UTC 24
Peak memory	215864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120866573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2120866573
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/31.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/31.keymgr_stress_all.1647144609
Short name	T402
Test name
Test status
Simulation time	944645318 ps
CPU time	41.83 seconds
Started	Sep 11 06:03:08 AM UTC 24
Finished	Sep 11 06:03:51 AM UTC 24
Peak memory	226072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647144609 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1647144609
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/31.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/31.keymgr_sw_invalid_input.3790055517
Short name	T664
Test name
Test status
Simulation time	921043955 ps
CPU time	23.34 seconds
Started	Sep 11 06:03:02 AM UTC 24
Finished	Sep 11 06:03:26 AM UTC 24
Peak memory	218208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790055517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3790055517
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/31.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/31.keymgr_sync_async_fault_cross.1915361750
Short name	T165
Test name
Test status
Simulation time	86923652 ps
CPU time	3.45 seconds
Started	Sep 11 06:03:08 AM UTC 24
Finished	Sep 11 06:03:12 AM UTC 24
Peak memory	218212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915361750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1915361750
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/31.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/32.keymgr_alert_test.598593493
Short name	T672
Test name
Test status
Simulation time	16799276 ps
CPU time	0.92 seconds
Started	Sep 11 06:03:37 AM UTC 24
Finished	Sep 11 06:03:39 AM UTC 24
Peak memory	213596 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598593493 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.598593493
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/32.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/32.keymgr_custom_cm.3136787368
Short name	T673
Test name
Test status
Simulation time	73725737 ps
CPU time	4.3 seconds
Started	Sep 11 06:03:34 AM UTC 24
Finished	Sep 11 06:03:39 AM UTC 24
Peak memory	219892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136787368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3136787368
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/32.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/32.keymgr_direct_to_disabled.1613778403
Short name	T666
Test name
Test status
Simulation time	98570419 ps
CPU time	4.11 seconds
Started	Sep 11 06:03:25 AM UTC 24
Finished	Sep 11 06:03:31 AM UTC 24
Peak memory	217936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613778403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1613778403
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/32.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/32.keymgr_hwsw_invalid_input.3582200140
Short name	T669
Test name
Test status
Simulation time	225225524 ps
CPU time	3.47 seconds
Started	Sep 11 06:03:31 AM UTC 24
Finished	Sep 11 06:03:35 AM UTC 24
Peak memory	224356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582200140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3582200140
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/32.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/32.keymgr_kmac_rsp_err.886535694
Short name	T379
Test name
Test status
Simulation time	363883217 ps
CPU time	4.18 seconds
Started	Sep 11 06:03:32 AM UTC 24
Finished	Sep 11 06:03:37 AM UTC 24
Peak memory	232184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886535694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.886535694
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/32.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/32.keymgr_lc_disable.1573952697
Short name	T665
Test name
Test status
Simulation time	64043075 ps
CPU time	2.93 seconds
Started	Sep 11 06:03:25 AM UTC 24
Finished	Sep 11 06:03:29 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573952697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1573952697
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/32.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/32.keymgr_random.2959674607
Short name	T662
Test name
Test status
Simulation time	114537423 ps
CPU time	5.34 seconds
Started	Sep 11 06:03:18 AM UTC 24
Finished	Sep 11 06:03:25 AM UTC 24
Peak memory	219932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959674607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2959674607
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/32.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/32.keymgr_sideload.1053048656
Short name	T660
Test name
Test status
Simulation time	70705953 ps
CPU time	3.59 seconds
Started	Sep 11 06:03:13 AM UTC 24
Finished	Sep 11 06:03:18 AM UTC 24
Peak memory	217880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053048656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1053048656
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/32.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_aes.3340383210
Short name	T661
Test name
Test status
Simulation time	229223678 ps
CPU time	4.43 seconds
Started	Sep 11 06:03:16 AM UTC 24
Finished	Sep 11 06:03:22 AM UTC 24
Peak memory	217948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340383210 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3340383210
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/32.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_kmac.681604363
Short name	T667
Test name
Test status
Simulation time	638707278 ps
CPU time	18.06 seconds
Started	Sep 11 06:03:13 AM UTC 24
Finished	Sep 11 06:03:32 AM UTC 24
Peak memory	217864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681604363 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.681604363
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/32.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_otbn.877214308
Short name	T663
Test name
Test status
Simulation time	824097642 ps
CPU time	6.5 seconds
Started	Sep 11 06:03:17 AM UTC 24
Finished	Sep 11 06:03:25 AM UTC 24
Peak memory	217876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877214308 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.877214308
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/32.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_protect.1141374816
Short name	T671
Test name
Test status
Simulation time	259555922 ps
CPU time	4.1 seconds
Started	Sep 11 06:03:34 AM UTC 24
Finished	Sep 11 06:03:39 AM UTC 24
Peak memory	225944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141374816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1141374816
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/32.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/32.keymgr_smoke.4234620552
Short name	T659
Test name
Test status
Simulation time	36256077 ps
CPU time	2.74 seconds
Started	Sep 11 06:03:13 AM UTC 24
Finished	Sep 11 06:03:17 AM UTC 24
Peak memory	217816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234620552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.4234620552
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/32.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/32.keymgr_stress_all.4017004769
Short name	T701
Test name
Test status
Simulation time	3155775475 ps
CPU time	34.72 seconds
Started	Sep 11 06:03:35 AM UTC 24
Finished	Sep 11 06:04:11 AM UTC 24
Peak memory	226204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017004769 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.4017004769
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/32.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/32.keymgr_stress_all_with_rand_reset.3685727765
Short name	T682
Test name
Test status
Simulation time	908126595 ps
CPU time	14.7 seconds
Started	Sep 11 06:03:36 AM UTC 24
Finished	Sep 11 06:03:52 AM UTC 24
Peak memory	232340 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3685727765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymg r_stress_all_with_rand_reset.3685727765
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/32.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/32.keymgr_sw_invalid_input.910697480
Short name	T668
Test name
Test status
Simulation time	97666193 ps
CPU time	4.97 seconds
Started	Sep 11 06:03:27 AM UTC 24
Finished	Sep 11 06:03:32 AM UTC 24
Peak memory	218208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910697480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.910697480
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/32.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/32.keymgr_sync_async_fault_cross.2386803583
Short name	T670
Test name
Test status
Simulation time	524070842 ps
CPU time	3.14 seconds
Started	Sep 11 06:03:34 AM UTC 24
Finished	Sep 11 06:03:38 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386803583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2386803583
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/32.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/33.keymgr_alert_test.973594000
Short name	T689
Test name
Test status
Simulation time	56815688 ps
CPU time	1.12 seconds
Started	Sep 11 06:03:57 AM UTC 24
Finished	Sep 11 06:03:59 AM UTC 24
Peak memory	213716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973594000 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.973594000
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/33.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/33.keymgr_custom_cm.1264333068
Short name	T687
Test name
Test status
Simulation time	509828373 ps
CPU time	6.1 seconds
Started	Sep 11 06:03:51 AM UTC 24
Finished	Sep 11 06:03:58 AM UTC 24
Peak memory	231456 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264333068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1264333068
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/33.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/33.keymgr_direct_to_disabled.3119689346
Short name	T680
Test name
Test status
Simulation time	66728670 ps
CPU time	1.71 seconds
Started	Sep 11 06:03:45 AM UTC 24
Finished	Sep 11 06:03:48 AM UTC 24
Peak memory	216208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119689346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3119689346
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/33.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/33.keymgr_hwsw_invalid_input.2858964931
Short name	T688
Test name
Test status
Simulation time	371040149 ps
CPU time	11.07 seconds
Started	Sep 11 06:03:47 AM UTC 24
Finished	Sep 11 06:03:59 AM UTC 24
Peak memory	218140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858964931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2858964931
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/33.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/33.keymgr_kmac_rsp_err.70545902
Short name	T683
Test name
Test status
Simulation time	93228152 ps
CPU time	4.2 seconds
Started	Sep 11 06:03:49 AM UTC 24
Finished	Sep 11 06:03:54 AM UTC 24
Peak memory	224028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70545902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.70545902
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/33.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/33.keymgr_lc_disable.2954365368
Short name	T681
Test name
Test status
Simulation time	419154276 ps
CPU time	2.8 seconds
Started	Sep 11 06:03:46 AM UTC 24
Finished	Sep 11 06:03:49 AM UTC 24
Peak memory	232588 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954365368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2954365368
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/33.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/33.keymgr_random.3183415884
Short name	T381
Test name
Test status
Simulation time	1772012623 ps
CPU time	43.88 seconds
Started	Sep 11 06:03:43 AM UTC 24
Finished	Sep 11 06:04:29 AM UTC 24
Peak memory	218028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183415884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3183415884
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/33.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/33.keymgr_sideload.3703250104
Short name	T678
Test name
Test status
Simulation time	136691803 ps
CPU time	5.1 seconds
Started	Sep 11 06:03:39 AM UTC 24
Finished	Sep 11 06:03:45 AM UTC 24
Peak memory	217880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703250104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3703250104
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/33.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_aes.689494744
Short name	T679
Test name
Test status
Simulation time	329200284 ps
CPU time	4.67 seconds
Started	Sep 11 06:03:40 AM UTC 24
Finished	Sep 11 06:03:46 AM UTC 24
Peak memory	217884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689494744 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.689494744
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/33.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_kmac.2122422967
Short name	T677
Test name
Test status
Simulation time	56160535 ps
CPU time	3.76 seconds
Started	Sep 11 06:03:40 AM UTC 24
Finished	Sep 11 06:03:45 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122422967 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2122422967
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/33.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_otbn.2914035273
Short name	T676
Test name
Test status
Simulation time	240619065 ps
CPU time	3.23 seconds
Started	Sep 11 06:03:40 AM UTC 24
Finished	Sep 11 06:03:45 AM UTC 24
Peak memory	216152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914035273 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2914035273
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/33.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_protect.2357452575
Short name	T684
Test name
Test status
Simulation time	27855433 ps
CPU time	2.09 seconds
Started	Sep 11 06:03:52 AM UTC 24
Finished	Sep 11 06:03:55 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357452575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2357452575
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/33.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/33.keymgr_smoke.1492844879
Short name	T674
Test name
Test status
Simulation time	62268876 ps
CPU time	3.12 seconds
Started	Sep 11 06:03:38 AM UTC 24
Finished	Sep 11 06:03:42 AM UTC 24
Peak memory	215856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492844879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1492844879
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/33.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all.1808725566
Short name	T706
Test name
Test status
Simulation time	1106330741 ps
CPU time	18.09 seconds
Started	Sep 11 06:03:55 AM UTC 24
Finished	Sep 11 06:04:14 AM UTC 24
Peak memory	230152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808725566 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1808725566
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/33.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all_with_rand_reset.3792674628
Short name	T694
Test name
Test status
Simulation time	201340977 ps
CPU time	9.09 seconds
Started	Sep 11 06:03:56 AM UTC 24
Finished	Sep 11 06:04:06 AM UTC 24
Peak memory	230364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3792674628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymg r_stress_all_with_rand_reset.3792674628
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/33.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/33.keymgr_sw_invalid_input.174419374
Short name	T685
Test name
Test status
Simulation time	1124587516 ps
CPU time	8.77 seconds
Started	Sep 11 06:03:47 AM UTC 24
Finished	Sep 11 06:03:56 AM UTC 24
Peak memory	228160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174419374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.174419374
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/33.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/33.keymgr_sync_async_fault_cross.3069471785
Short name	T686
Test name
Test status
Simulation time	133976030 ps
CPU time	3.19 seconds
Started	Sep 11 06:03:53 AM UTC 24
Finished	Sep 11 06:03:57 AM UTC 24
Peak memory	220100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069471785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3069471785
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/33.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/34.keymgr_alert_test.1812063169
Short name	T705
Test name
Test status
Simulation time	13628633 ps
CPU time	1.08 seconds
Started	Sep 11 06:04:12 AM UTC 24
Finished	Sep 11 06:04:14 AM UTC 24
Peak memory	213528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812063169 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1812063169
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/34.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/34.keymgr_cfg_regwen.2791523153
Short name	T432
Test name
Test status
Simulation time	49835987 ps
CPU time	3.86 seconds
Started	Sep 11 06:04:03 AM UTC 24
Finished	Sep 11 06:04:07 AM UTC 24
Peak memory	225796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791523153 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2791523153
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/34.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/34.keymgr_custom_cm.1517376596
Short name	T702
Test name
Test status
Simulation time	213605577 ps
CPU time	2.82 seconds
Started	Sep 11 06:04:08 AM UTC 24
Finished	Sep 11 06:04:12 AM UTC 24
Peak memory	230248 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517376596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1517376596
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/34.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/34.keymgr_direct_to_disabled.2843606175
Short name	T698
Test name
Test status
Simulation time	220176169 ps
CPU time	5.28 seconds
Started	Sep 11 06:04:04 AM UTC 24
Finished	Sep 11 06:04:10 AM UTC 24
Peak memory	217948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843606175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2843606175
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/34.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/34.keymgr_kmac_rsp_err.2698636706
Short name	T700
Test name
Test status
Simulation time	78628151 ps
CPU time	3.03 seconds
Started	Sep 11 06:04:07 AM UTC 24
Finished	Sep 11 06:04:11 AM UTC 24
Peak memory	224028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698636706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2698636706
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/34.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/34.keymgr_lc_disable.2910059414
Short name	T699
Test name
Test status
Simulation time	1104546435 ps
CPU time	4.83 seconds
Started	Sep 11 06:04:05 AM UTC 24
Finished	Sep 11 06:04:11 AM UTC 24
Peak memory	217976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910059414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2910059414
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/34.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/34.keymgr_random.1031805150
Short name	T695
Test name
Test status
Simulation time	31973860 ps
CPU time	2.75 seconds
Started	Sep 11 06:04:02 AM UTC 24
Finished	Sep 11 06:04:06 AM UTC 24
Peak memory	217696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031805150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1031805150
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/34.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/34.keymgr_sideload.2511743856
Short name	T696
Test name
Test status
Simulation time	728086178 ps
CPU time	7.96 seconds
Started	Sep 11 06:03:59 AM UTC 24
Finished	Sep 11 06:04:08 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511743856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2511743856
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/34.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_aes.2166493497
Short name	T691
Test name
Test status
Simulation time	141151477 ps
CPU time	2.79 seconds
Started	Sep 11 06:03:59 AM UTC 24
Finished	Sep 11 06:04:03 AM UTC 24
Peak memory	216152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166493497 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2166493497
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/34.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_kmac.1644509328
Short name	T693
Test name
Test status
Simulation time	270463674 ps
CPU time	3.76 seconds
Started	Sep 11 06:03:59 AM UTC 24
Finished	Sep 11 06:04:04 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644509328 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1644509328
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/34.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_otbn.3874065676
Short name	T692
Test name
Test status
Simulation time	78301986 ps
CPU time	2.09 seconds
Started	Sep 11 06:04:00 AM UTC 24
Finished	Sep 11 06:04:03 AM UTC 24
Peak memory	215900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874065676 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3874065676
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/34.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_protect.4138563173
Short name	T703
Test name
Test status
Simulation time	72839421 ps
CPU time	1.95 seconds
Started	Sep 11 06:04:09 AM UTC 24
Finished	Sep 11 06:04:12 AM UTC 24
Peak memory	225684 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138563173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.4138563173
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/34.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/34.keymgr_smoke.520485715
Short name	T690
Test name
Test status
Simulation time	47608901 ps
CPU time	2.27 seconds
Started	Sep 11 06:03:58 AM UTC 24
Finished	Sep 11 06:04:02 AM UTC 24
Peak memory	215840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520485715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.520485715
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/34.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all.1249762074
Short name	T355
Test name
Test status
Simulation time	345839367 ps
CPU time	16.53 seconds
Started	Sep 11 06:04:11 AM UTC 24
Finished	Sep 11 06:04:29 AM UTC 24
Peak memory	230492 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249762074 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1249762074
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/34.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all_with_rand_reset.301202928
Short name	T709
Test name
Test status
Simulation time	70703129 ps
CPU time	5.23 seconds
Started	Sep 11 06:04:11 AM UTC 24
Finished	Sep 11 06:04:17 AM UTC 24
Peak memory	231464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=301202928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr _stress_all_with_rand_reset.301202928
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/34.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/34.keymgr_sw_invalid_input.9705648
Short name	T697
Test name
Test status
Simulation time	81051138 ps
CPU time	4.29 seconds
Started	Sep 11 06:04:05 AM UTC 24
Finished	Sep 11 06:04:10 AM UTC 24
Peak memory	215896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9705648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=k eymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.9705648
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/34.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/34.keymgr_sync_async_fault_cross.1698025678
Short name	T704
Test name
Test status
Simulation time	74215492 ps
CPU time	1.47 seconds
Started	Sep 11 06:04:11 AM UTC 24
Finished	Sep 11 06:04:13 AM UTC 24
Peak memory	217544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698025678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1698025678
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/34.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/35.keymgr_alert_test.2818849164
Short name	T717
Test name
Test status
Simulation time	10250983 ps
CPU time	1.05 seconds
Started	Sep 11 06:04:26 AM UTC 24
Finished	Sep 11 06:04:29 AM UTC 24
Peak memory	213532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818849164 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2818849164
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/35.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/35.keymgr_custom_cm.3903537621
Short name	T715
Test name
Test status
Simulation time	209560979 ps
CPU time	2.27 seconds
Started	Sep 11 06:04:22 AM UTC 24
Finished	Sep 11 06:04:25 AM UTC 24
Peak memory	232576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903537621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3903537621
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/35.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/35.keymgr_direct_to_disabled.143529028
Short name	T713
Test name
Test status
Simulation time	1026739630 ps
CPU time	3.68 seconds
Started	Sep 11 06:04:17 AM UTC 24
Finished	Sep 11 06:04:21 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143529028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.143529028
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/35.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/35.keymgr_hwsw_invalid_input.2044333826
Short name	T716
Test name
Test status
Simulation time	91830325 ps
CPU time	5.22 seconds
Started	Sep 11 06:04:20 AM UTC 24
Finished	Sep 11 06:04:26 AM UTC 24
Peak memory	231204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044333826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.2044333826
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/35.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/35.keymgr_kmac_rsp_err.3729008033
Short name	T393
Test name
Test status
Simulation time	64718284 ps
CPU time	3.39 seconds
Started	Sep 11 06:04:21 AM UTC 24
Finished	Sep 11 06:04:25 AM UTC 24
Peak memory	223968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729008033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3729008033
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/35.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/35.keymgr_lc_disable.4220454350
Short name	T714
Test name
Test status
Simulation time	168928267 ps
CPU time	4.37 seconds
Started	Sep 11 06:04:18 AM UTC 24
Finished	Sep 11 06:04:23 AM UTC 24
Peak memory	226244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220454350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.4220454350
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/35.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/35.keymgr_random.2576812646
Short name	T283
Test name
Test status
Simulation time	115626928 ps
CPU time	5.42 seconds
Started	Sep 11 06:04:15 AM UTC 24
Finished	Sep 11 06:04:22 AM UTC 24
Peak memory	217880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576812646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2576812646
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/35.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/35.keymgr_sideload.2022636104
Short name	T708
Test name
Test status
Simulation time	413635399 ps
CPU time	3.4 seconds
Started	Sep 11 06:04:12 AM UTC 24
Finished	Sep 11 06:04:17 AM UTC 24
Peak memory	215752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022636104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2022636104
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/35.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_aes.1181037235
Short name	T710
Test name
Test status
Simulation time	54289056 ps
CPU time	3.31 seconds
Started	Sep 11 06:04:14 AM UTC 24
Finished	Sep 11 06:04:19 AM UTC 24
Peak memory	217872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181037235 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1181037235
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/35.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_kmac.3340404110
Short name	T712
Test name
Test status
Simulation time	234513595 ps
CPU time	7.38 seconds
Started	Sep 11 06:04:12 AM UTC 24
Finished	Sep 11 06:04:21 AM UTC 24
Peak memory	217876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340404110 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3340404110
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/35.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_otbn.2982635330
Short name	T711
Test name
Test status
Simulation time	177846270 ps
CPU time	4.95 seconds
Started	Sep 11 06:04:14 AM UTC 24
Finished	Sep 11 06:04:20 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982635330 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2982635330
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/35.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_protect.1465252944
Short name	T263
Test name
Test status
Simulation time	528854360 ps
CPU time	4.1 seconds
Started	Sep 11 06:04:22 AM UTC 24
Finished	Sep 11 06:04:27 AM UTC 24
Peak memory	228244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465252944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1465252944
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/35.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/35.keymgr_smoke.2521714686
Short name	T707
Test name
Test status
Simulation time	36913020 ps
CPU time	2.46 seconds
Started	Sep 11 06:04:12 AM UTC 24
Finished	Sep 11 06:04:16 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521714686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2521714686
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/35.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/35.keymgr_stress_all.2455029285
Short name	T723
Test name
Test status
Simulation time	925150122 ps
CPU time	10.44 seconds
Started	Sep 11 06:04:24 AM UTC 24
Finished	Sep 11 06:04:36 AM UTC 24
Peak memory	226140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455029285 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2455029285
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/35.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/35.keymgr_stress_all_with_rand_reset.3092667677
Short name	T729
Test name
Test status
Simulation time	395759517 ps
CPU time	16.04 seconds
Started	Sep 11 06:04:26 AM UTC 24
Finished	Sep 11 06:04:44 AM UTC 24
Peak memory	232368 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3092667677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymg r_stress_all_with_rand_reset.3092667677
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/35.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/35.keymgr_sw_invalid_input.3979308248
Short name	T743
Test name
Test status
Simulation time	2179628260 ps
CPU time	43.08 seconds
Started	Sep 11 06:04:19 AM UTC 24
Finished	Sep 11 06:05:04 AM UTC 24
Peak memory	228248 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979308248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3979308248
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/35.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/35.keymgr_sync_async_fault_cross.312016046
Short name	T728
Test name
Test status
Simulation time	789504702 ps
CPU time	18.82 seconds
Started	Sep 11 06:04:23 AM UTC 24
Finished	Sep 11 06:04:43 AM UTC 24
Peak memory	220004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312016046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.312016046
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/35.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/36.keymgr_alert_test.1410501579
Short name	T732
Test name
Test status
Simulation time	12693779 ps
CPU time	0.94 seconds
Started	Sep 11 06:04:44 AM UTC 24
Finished	Sep 11 06:04:46 AM UTC 24
Peak memory	213532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410501579 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1410501579
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/36.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/36.keymgr_cfg_regwen.3921176951
Short name	T439
Test name
Test status
Simulation time	527144157 ps
CPU time	8.3 seconds
Started	Sep 11 06:04:34 AM UTC 24
Finished	Sep 11 06:04:43 AM UTC 24
Peak memory	226092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921176951 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3921176951
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/36.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/36.keymgr_custom_cm.3091082602
Short name	T731
Test name
Test status
Simulation time	1612161955 ps
CPU time	5.55 seconds
Started	Sep 11 06:04:39 AM UTC 24
Finished	Sep 11 06:04:46 AM UTC 24
Peak memory	224068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091082602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3091082602
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/36.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/36.keymgr_direct_to_disabled.2024700308
Short name	T725
Test name
Test status
Simulation time	134331987 ps
CPU time	3.88 seconds
Started	Sep 11 06:04:34 AM UTC 24
Finished	Sep 11 06:04:39 AM UTC 24
Peak memory	217868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024700308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2024700308
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/36.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/36.keymgr_hwsw_invalid_input.2302492266
Short name	T56
Test name
Test status
Simulation time	5432019644 ps
CPU time	25.8 seconds
Started	Sep 11 06:04:37 AM UTC 24
Finished	Sep 11 06:05:04 AM UTC 24
Peak memory	224160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302492266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2302492266
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/36.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/36.keymgr_kmac_rsp_err.4160533565
Short name	T726
Test name
Test status
Simulation time	96331581 ps
CPU time	3.24 seconds
Started	Sep 11 06:04:37 AM UTC 24
Finished	Sep 11 06:04:41 AM UTC 24
Peak memory	226404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160533565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.4160533565
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/36.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/36.keymgr_lc_disable.1111010707
Short name	T724
Test name
Test status
Simulation time	71042209 ps
CPU time	2.95 seconds
Started	Sep 11 06:04:34 AM UTC 24
Finished	Sep 11 06:04:38 AM UTC 24
Peak memory	232340 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111010707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1111010707
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/36.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/36.keymgr_random.23378808
Short name	T747
Test name
Test status
Simulation time	905988018 ps
CPU time	32.99 seconds
Started	Sep 11 06:04:33 AM UTC 24
Finished	Sep 11 06:05:07 AM UTC 24
Peak memory	218208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23378808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.23378808
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/36.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/36.keymgr_sideload.1111932787
Short name	T720
Test name
Test status
Simulation time	151029084 ps
CPU time	3.38 seconds
Started	Sep 11 06:04:28 AM UTC 24
Finished	Sep 11 06:04:33 AM UTC 24
Peak memory	215820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111932787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1111932787
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/36.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_aes.2573160756
Short name	T721
Test name
Test status
Simulation time	34290897 ps
CPU time	2.74 seconds
Started	Sep 11 06:04:29 AM UTC 24
Finished	Sep 11 06:04:33 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573160756 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2573160756
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/36.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_kmac.1577244611
Short name	T722
Test name
Test status
Simulation time	169041635 ps
CPU time	4.36 seconds
Started	Sep 11 06:04:29 AM UTC 24
Finished	Sep 11 06:04:35 AM UTC 24
Peak memory	217908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577244611 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1577244611
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/36.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_otbn.2954765553
Short name	T719
Test name
Test status
Simulation time	80292211 ps
CPU time	2.15 seconds
Started	Sep 11 06:04:29 AM UTC 24
Finished	Sep 11 06:04:33 AM UTC 24
Peak memory	215936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954765553 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2954765553
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/36.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_protect.2262976151
Short name	T730
Test name
Test status
Simulation time	419205624 ps
CPU time	3.76 seconds
Started	Sep 11 06:04:39 AM UTC 24
Finished	Sep 11 06:04:44 AM UTC 24
Peak memory	224188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262976151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2262976151
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/36.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/36.keymgr_smoke.107609655
Short name	T718
Test name
Test status
Simulation time	461877436 ps
CPU time	3 seconds
Started	Sep 11 06:04:27 AM UTC 24
Finished	Sep 11 06:04:31 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107609655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.107609655
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/36.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/36.keymgr_stress_all.2188379430
Short name	T264
Test name
Test status
Simulation time	1138200058 ps
CPU time	40.6 seconds
Started	Sep 11 06:04:43 AM UTC 24
Finished	Sep 11 06:05:25 AM UTC 24
Peak memory	232616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188379430 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2188379430
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/36.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/36.keymgr_sw_invalid_input.456039251
Short name	T727
Test name
Test status
Simulation time	116084116 ps
CPU time	5.14 seconds
Started	Sep 11 06:04:36 AM UTC 24
Finished	Sep 11 06:04:42 AM UTC 24
Peak memory	219936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456039251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.456039251
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/36.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/36.keymgr_sync_async_fault_cross.3094334970
Short name	T736
Test name
Test status
Simulation time	775188851 ps
CPU time	8.31 seconds
Started	Sep 11 06:04:42 AM UTC 24
Finished	Sep 11 06:04:52 AM UTC 24
Peak memory	219932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094334970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3094334970
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/36.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/37.keymgr_alert_test.2363585900
Short name	T746
Test name
Test status
Simulation time	44240179 ps
CPU time	1.03 seconds
Started	Sep 11 06:05:04 AM UTC 24
Finished	Sep 11 06:05:06 AM UTC 24
Peak memory	213532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363585900 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2363585900
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/37.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/37.keymgr_cfg_regwen.3666295039
Short name	T243
Test name
Test status
Simulation time	63188304 ps
CPU time	4.67 seconds
Started	Sep 11 06:04:52 AM UTC 24
Finished	Sep 11 06:04:57 AM UTC 24
Peak memory	226168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666295039 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3666295039
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/37.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/37.keymgr_custom_cm.733073138
Short name	T745
Test name
Test status
Simulation time	536954449 ps
CPU time	6.89 seconds
Started	Sep 11 06:04:58 AM UTC 24
Finished	Sep 11 06:05:06 AM UTC 24
Peak memory	231892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733073138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.733073138
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/37.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/37.keymgr_direct_to_disabled.2592792292
Short name	T332
Test name
Test status
Simulation time	1482339810 ps
CPU time	15.69 seconds
Started	Sep 11 06:04:53 AM UTC 24
Finished	Sep 11 06:05:10 AM UTC 24
Peak memory	217860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592792292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2592792292
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/37.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/37.keymgr_hwsw_invalid_input.3898535420
Short name	T740
Test name
Test status
Simulation time	89997520 ps
CPU time	2.13 seconds
Started	Sep 11 06:04:55 AM UTC 24
Finished	Sep 11 06:04:58 AM UTC 24
Peak memory	224028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898535420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3898535420
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/37.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/37.keymgr_kmac_rsp_err.2362605960
Short name	T357
Test name
Test status
Simulation time	520477707 ps
CPU time	4.49 seconds
Started	Sep 11 06:04:58 AM UTC 24
Finished	Sep 11 06:05:03 AM UTC 24
Peak memory	224388 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362605960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2362605960
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/37.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/37.keymgr_lc_disable.426126200
Short name	T739
Test name
Test status
Simulation time	228209682 ps
CPU time	3.85 seconds
Started	Sep 11 06:04:53 AM UTC 24
Finished	Sep 11 06:04:58 AM UTC 24
Peak memory	230168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426126200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.426126200
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/37.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/37.keymgr_random.1565637122
Short name	T738
Test name
Test status
Simulation time	185979235 ps
CPU time	3.55 seconds
Started	Sep 11 06:04:50 AM UTC 24
Finished	Sep 11 06:04:54 AM UTC 24
Peak memory	218212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565637122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1565637122
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/37.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/37.keymgr_sideload.3020328630
Short name	T733
Test name
Test status
Simulation time	72664449 ps
CPU time	2.06 seconds
Started	Sep 11 06:04:44 AM UTC 24
Finished	Sep 11 06:04:47 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020328630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.3020328630
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/37.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_aes.3332119542
Short name	T735
Test name
Test status
Simulation time	38852715 ps
CPU time	2.54 seconds
Started	Sep 11 06:04:47 AM UTC 24
Finished	Sep 11 06:04:51 AM UTC 24
Peak memory	216152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332119542 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3332119542
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/37.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_kmac.441319299
Short name	T744
Test name
Test status
Simulation time	907459625 ps
CPU time	18.16 seconds
Started	Sep 11 06:04:46 AM UTC 24
Finished	Sep 11 06:05:06 AM UTC 24
Peak memory	218204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441319299 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.441319299
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/37.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_otbn.572600185
Short name	T737
Test name
Test status
Simulation time	68447308 ps
CPU time	3.89 seconds
Started	Sep 11 06:04:48 AM UTC 24
Finished	Sep 11 06:04:53 AM UTC 24
Peak memory	217944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572600185 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.572600185
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/37.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_protect.2585112847
Short name	T742
Test name
Test status
Simulation time	36233905 ps
CPU time	2.98 seconds
Started	Sep 11 06:04:59 AM UTC 24
Finished	Sep 11 06:05:03 AM UTC 24
Peak memory	224104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585112847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2585112847
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/37.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/37.keymgr_smoke.2568429869
Short name	T734
Test name
Test status
Simulation time	80409092 ps
CPU time	3.64 seconds
Started	Sep 11 06:04:44 AM UTC 24
Finished	Sep 11 06:04:49 AM UTC 24
Peak memory	217816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568429869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2568429869
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/37.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all.816025672
Short name	T783
Test name
Test status
Simulation time	25763348572 ps
CPU time	58.22 seconds
Started	Sep 11 06:05:04 AM UTC 24
Finished	Sep 11 06:06:04 AM UTC 24
Peak memory	232660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816025672 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.816025672
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/37.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all_with_rand_reset.682946310
Short name	T758
Test name
Test status
Simulation time	238783950 ps
CPU time	16.95 seconds
Started	Sep 11 06:05:04 AM UTC 24
Finished	Sep 11 06:05:22 AM UTC 24
Peak memory	232748 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=682946310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr _stress_all_with_rand_reset.682946310
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/37.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/37.keymgr_sw_invalid_input.1280563607
Short name	T741
Test name
Test status
Simulation time	206875194 ps
CPU time	7.39 seconds
Started	Sep 11 06:04:54 AM UTC 24
Finished	Sep 11 06:05:02 AM UTC 24
Peak memory	217972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280563607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1280563607
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/37.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/37.keymgr_sync_async_fault_cross.2025046691
Short name	T397
Test name
Test status
Simulation time	106518218 ps
CPU time	1.67 seconds
Started	Sep 11 06:05:03 AM UTC 24
Finished	Sep 11 06:05:06 AM UTC 24
Peak memory	216156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025046691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2025046691
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/37.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/38.keymgr_alert_test.2077132597
Short name	T757
Test name
Test status
Simulation time	23433992 ps
CPU time	0.89 seconds
Started	Sep 11 06:05:18 AM UTC 24
Finished	Sep 11 06:05:20 AM UTC 24
Peak memory	213532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077132597 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2077132597
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/38.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/38.keymgr_cfg_regwen.4193228447
Short name	T437
Test name
Test status
Simulation time	215981321 ps
CPU time	13 seconds
Started	Sep 11 06:05:11 AM UTC 24
Finished	Sep 11 06:05:25 AM UTC 24
Peak memory	226144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193228447 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.4193228447
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/38.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/38.keymgr_direct_to_disabled.4077420024
Short name	T391
Test name
Test status
Simulation time	71160611 ps
CPU time	2.77 seconds
Started	Sep 11 06:05:11 AM UTC 24
Finished	Sep 11 06:05:14 AM UTC 24
Peak memory	218080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077420024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.4077420024
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/38.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/38.keymgr_hwsw_invalid_input.3129627189
Short name	T375
Test name
Test status
Simulation time	327492512 ps
CPU time	3.44 seconds
Started	Sep 11 06:05:12 AM UTC 24
Finished	Sep 11 06:05:16 AM UTC 24
Peak memory	224352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129627189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3129627189
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/38.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/38.keymgr_kmac_rsp_err.533154580
Short name	T755
Test name
Test status
Simulation time	234899898 ps
CPU time	2.98 seconds
Started	Sep 11 06:05:12 AM UTC 24
Finished	Sep 11 06:05:16 AM UTC 24
Peak memory	230220 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533154580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.533154580
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/38.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/38.keymgr_lc_disable.1727602648
Short name	T313
Test name
Test status
Simulation time	221932036 ps
CPU time	4.4 seconds
Started	Sep 11 06:05:12 AM UTC 24
Finished	Sep 11 06:05:17 AM UTC 24
Peak memory	230504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727602648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1727602648
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/38.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/38.keymgr_random.3828468897
Short name	T754
Test name
Test status
Simulation time	257033718 ps
CPU time	3.72 seconds
Started	Sep 11 06:05:08 AM UTC 24
Finished	Sep 11 06:05:12 AM UTC 24
Peak memory	218212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828468897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3828468897
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/38.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/38.keymgr_sideload.124448376
Short name	T748
Test name
Test status
Simulation time	191978751 ps
CPU time	2.86 seconds
Started	Sep 11 06:05:06 AM UTC 24
Finished	Sep 11 06:05:10 AM UTC 24
Peak memory	217876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124448376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.124448376
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/38.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_aes.1105580788
Short name	T751
Test name
Test status
Simulation time	325199204 ps
CPU time	3.34 seconds
Started	Sep 11 06:05:06 AM UTC 24
Finished	Sep 11 06:05:11 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105580788 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1105580788
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/38.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_kmac.3231919816
Short name	T750
Test name
Test status
Simulation time	87343235 ps
CPU time	3.16 seconds
Started	Sep 11 06:05:06 AM UTC 24
Finished	Sep 11 06:05:11 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231919816 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3231919816
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/38.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_otbn.347314309
Short name	T752
Test name
Test status
Simulation time	21974802 ps
CPU time	2.27 seconds
Started	Sep 11 06:05:07 AM UTC 24
Finished	Sep 11 06:05:11 AM UTC 24
Peak memory	215900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347314309 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.347314309
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/38.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_protect.735014144
Short name	T769
Test name
Test status
Simulation time	1256663642 ps
CPU time	29.37 seconds
Started	Sep 11 06:05:15 AM UTC 24
Finished	Sep 11 06:05:46 AM UTC 24
Peak memory	218020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735014144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.735014144
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/38.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/38.keymgr_smoke.2983340837
Short name	T749
Test name
Test status
Simulation time	535396378 ps
CPU time	4.23 seconds
Started	Sep 11 06:05:05 AM UTC 24
Finished	Sep 11 06:05:11 AM UTC 24
Peak memory	216096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983340837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2983340837
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/38.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all.905416279
Short name	T319
Test name
Test status
Simulation time	462609952 ps
CPU time	16.87 seconds
Started	Sep 11 06:05:17 AM UTC 24
Finished	Sep 11 06:05:35 AM UTC 24
Peak memory	228192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905416279 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.905416279
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/38.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all_with_rand_reset.4052175433
Short name	T142
Test name
Test status
Simulation time	1013471160 ps
CPU time	10.61 seconds
Started	Sep 11 06:05:18 AM UTC 24
Finished	Sep 11 06:05:30 AM UTC 24
Peak memory	232336 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4052175433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymg r_stress_all_with_rand_reset.4052175433
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/38.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/38.keymgr_sw_invalid_input.2457877629
Short name	T756
Test name
Test status
Simulation time	906676224 ps
CPU time	6.88 seconds
Started	Sep 11 06:05:12 AM UTC 24
Finished	Sep 11 06:05:20 AM UTC 24
Peak memory	217872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457877629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2457877629
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/38.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/38.keymgr_sync_async_fault_cross.907449691
Short name	T169
Test name
Test status
Simulation time	66702254 ps
CPU time	2.4 seconds
Started	Sep 11 06:05:17 AM UTC 24
Finished	Sep 11 06:05:20 AM UTC 24
Peak memory	217856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907449691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.907449691
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/38.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/39.keymgr_alert_test.1612938193
Short name	T766
Test name
Test status
Simulation time	40718206 ps
CPU time	1.25 seconds
Started	Sep 11 06:05:41 AM UTC 24
Finished	Sep 11 06:05:44 AM UTC 24
Peak memory	214052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612938193 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1612938193
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/39.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/39.keymgr_cfg_regwen.112785143
Short name	T440
Test name
Test status
Simulation time	115798935 ps
CPU time	2.8 seconds
Started	Sep 11 06:05:28 AM UTC 24
Finished	Sep 11 06:05:31 AM UTC 24
Peak memory	224080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112785143 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.112785143
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/39.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/39.keymgr_direct_to_disabled.1927556896
Short name	T333
Test name
Test status
Simulation time	1560846387 ps
CPU time	16.93 seconds
Started	Sep 11 06:05:30 AM UTC 24
Finished	Sep 11 06:05:48 AM UTC 24
Peak memory	220032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927556896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1927556896
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/39.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/39.keymgr_hwsw_invalid_input.2958741975
Short name	T764
Test name
Test status
Simulation time	64621235 ps
CPU time	2.87 seconds
Started	Sep 11 06:05:34 AM UTC 24
Finished	Sep 11 06:05:38 AM UTC 24
Peak memory	224120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958741975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2958741975
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/39.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/39.keymgr_lc_disable.3839084868
Short name	T762
Test name
Test status
Simulation time	105683895 ps
CPU time	2.44 seconds
Started	Sep 11 06:05:31 AM UTC 24
Finished	Sep 11 06:05:34 AM UTC 24
Peak memory	226404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839084868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3839084868
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/39.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/39.keymgr_random.110307419
Short name	T761
Test name
Test status
Simulation time	405925298 ps
CPU time	5.61 seconds
Started	Sep 11 06:05:27 AM UTC 24
Finished	Sep 11 06:05:33 AM UTC 24
Peak memory	218024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110307419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.110307419
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/39.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/39.keymgr_sideload.3729354950
Short name	T774
Test name
Test status
Simulation time	12730998008 ps
CPU time	27.2 seconds
Started	Sep 11 06:05:21 AM UTC 24
Finished	Sep 11 06:05:50 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729354950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3729354950
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/39.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_aes.351074289
Short name	T765
Test name
Test status
Simulation time	1037253875 ps
CPU time	16.3 seconds
Started	Sep 11 06:05:23 AM UTC 24
Finished	Sep 11 06:05:41 AM UTC 24
Peak memory	217880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351074289 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.351074289
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/39.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_kmac.3170052727
Short name	T759
Test name
Test status
Simulation time	118844821 ps
CPU time	4.42 seconds
Started	Sep 11 06:05:21 AM UTC 24
Finished	Sep 11 06:05:27 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170052727 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3170052727
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/39.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_otbn.1791476393
Short name	T760
Test name
Test status
Simulation time	90132923 ps
CPU time	2.9 seconds
Started	Sep 11 06:05:25 AM UTC 24
Finished	Sep 11 06:05:29 AM UTC 24
Peak memory	216152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791476393 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1791476393
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/39.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_protect.3132479849
Short name	T768
Test name
Test status
Simulation time	245003170 ps
CPU time	5.76 seconds
Started	Sep 11 06:05:37 AM UTC 24
Finished	Sep 11 06:05:44 AM UTC 24
Peak memory	217984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132479849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.3132479849
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/39.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/39.keymgr_smoke.989167306
Short name	T770
Test name
Test status
Simulation time	1279659094 ps
CPU time	25.5 seconds
Started	Sep 11 06:05:20 AM UTC 24
Finished	Sep 11 06:05:47 AM UTC 24
Peak memory	217816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989167306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.989167306
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/39.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all_with_rand_reset.3179967059
Short name	T186
Test name
Test status
Simulation time	334900694 ps
CPU time	13.38 seconds
Started	Sep 11 06:05:41 AM UTC 24
Finished	Sep 11 06:05:56 AM UTC 24
Peak memory	232500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3179967059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymg r_stress_all_with_rand_reset.3179967059
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/39.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/39.keymgr_sw_invalid_input.197543173
Short name	T763
Test name
Test status
Simulation time	75619902 ps
CPU time	3.85 seconds
Started	Sep 11 06:05:32 AM UTC 24
Finished	Sep 11 06:05:37 AM UTC 24
Peak memory	218272 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197543173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.197543173
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/39.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/39.keymgr_sync_async_fault_cross.4016095283
Short name	T767
Test name
Test status
Simulation time	349033440 ps
CPU time	4.7 seconds
Started	Sep 11 06:05:38 AM UTC 24
Finished	Sep 11 06:05:44 AM UTC 24
Peak memory	220260 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016095283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.4016095283
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/39.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/4.keymgr_alert_test.1188212813
Short name	T190
Test name
Test status
Simulation time	68022687 ps
CPU time	1.01 seconds
Started	Sep 11 05:51:58 AM UTC 24
Finished	Sep 11 05:52:00 AM UTC 24
Peak memory	213600 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188212813 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1188212813
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/4.keymgr_direct_to_disabled.891896170
Short name	T210
Test name
Test status
Simulation time	26963978 ps
CPU time	1.86 seconds
Started	Sep 11 05:51:21 AM UTC 24
Finished	Sep 11 05:51:24 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891896170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.891896170
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/4.keymgr_hwsw_invalid_input.220742506
Short name	T49
Test name
Test status
Simulation time	2199002592 ps
CPU time	27.57 seconds
Started	Sep 11 05:51:31 AM UTC 24
Finished	Sep 11 05:52:00 AM UTC 24
Peak memory	218012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220742506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.220742506
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/4.keymgr_lc_disable.2947327596
Short name	T206
Test name
Test status
Simulation time	309645744 ps
CPU time	4.5 seconds
Started	Sep 11 05:51:25 AM UTC 24
Finished	Sep 11 05:51:31 AM UTC 24
Peak memory	230276 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947327596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2947327596
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/4.keymgr_random.2096320450
Short name	T215
Test name
Test status
Simulation time	102814901 ps
CPU time	5.63 seconds
Started	Sep 11 05:51:01 AM UTC 24
Finished	Sep 11 05:51:07 AM UTC 24
Peak memory	217880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096320450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2096320450
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/4.keymgr_sec_cm.901349247
Short name	T45
Test name
Test status
Simulation time	443938763 ps
CPU time	15.06 seconds
Started	Sep 11 05:51:44 AM UTC 24
Finished	Sep 11 05:52:01 AM UTC 24
Peak memory	252304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901349247 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.901349247
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/4.keymgr_sideload.1896683012
Short name	T258
Test name
Test status
Simulation time	2137877013 ps
CPU time	39.87 seconds
Started	Sep 11 05:50:52 AM UTC 24
Finished	Sep 11 05:51:34 AM UTC 24
Peak memory	217876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896683012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1896683012
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_aes.1139469657
Short name	T191
Test name
Test status
Simulation time	4183440933 ps
CPU time	67.3 seconds
Started	Sep 11 05:50:54 AM UTC 24
Finished	Sep 11 05:52:04 AM UTC 24
Peak memory	218016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139469657 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1139469657
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_kmac.3583279336
Short name	T188
Test name
Test status
Simulation time	3341942214 ps
CPU time	61.05 seconds
Started	Sep 11 05:50:54 AM UTC 24
Finished	Sep 11 05:51:57 AM UTC 24
Peak memory	218020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583279336 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3583279336
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_otbn.3349643490
Short name	T284
Test name
Test status
Simulation time	39609392 ps
CPU time	2.47 seconds
Started	Sep 11 05:50:57 AM UTC 24
Finished	Sep 11 05:51:00 AM UTC 24
Peak memory	218280 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349643490 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3349643490
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_protect.3268216494
Short name	T200
Test name
Test status
Simulation time	235546270 ps
CPU time	2.28 seconds
Started	Sep 11 05:51:39 AM UTC 24
Finished	Sep 11 05:51:42 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268216494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3268216494
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/4.keymgr_smoke.2815912000
Short name	T444
Test name
Test status
Simulation time	468960626 ps
CPU time	4.31 seconds
Started	Sep 11 05:50:46 AM UTC 24
Finished	Sep 11 05:50:52 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815912000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2815912000
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/4.keymgr_stress_all_with_rand_reset.2258758381
Short name	T80
Test name
Test status
Simulation time	297970100 ps
CPU time	12.12 seconds
Started	Sep 11 05:51:43 AM UTC 24
Finished	Sep 11 05:51:57 AM UTC 24
Peak memory	232372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2258758381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr _stress_all_with_rand_reset.2258758381
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/4.keymgr_sw_invalid_input.2222945873
Short name	T209
Test name
Test status
Simulation time	398456339 ps
CPU time	3.81 seconds
Started	Sep 11 05:51:25 AM UTC 24
Finished	Sep 11 05:51:30 AM UTC 24
Peak memory	215896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222945873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2222945873
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/4.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/40.keymgr_alert_test.2711710336
Short name	T782
Test name
Test status
Simulation time	15556142 ps
CPU time	1.17 seconds
Started	Sep 11 06:05:59 AM UTC 24
Finished	Sep 11 06:06:01 AM UTC 24
Peak memory	213712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711710336 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2711710336
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/40.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/40.keymgr_custom_cm.896726934
Short name	T40
Test name
Test status
Simulation time	151256965 ps
CPU time	3.53 seconds
Started	Sep 11 06:05:56 AM UTC 24
Finished	Sep 11 06:06:01 AM UTC 24
Peak memory	218360 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896726934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.896726934
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/40.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/40.keymgr_direct_to_disabled.1949961238
Short name	T777
Test name
Test status
Simulation time	238017543 ps
CPU time	5.87 seconds
Started	Sep 11 06:05:50 AM UTC 24
Finished	Sep 11 06:05:57 AM UTC 24
Peak memory	218272 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949961238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1949961238
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/40.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/40.keymgr_kmac_rsp_err.4115965854
Short name	T781
Test name
Test status
Simulation time	155742429 ps
CPU time	5.27 seconds
Started	Sep 11 06:05:55 AM UTC 24
Finished	Sep 11 06:06:01 AM UTC 24
Peak memory	224072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115965854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.4115965854
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/40.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/40.keymgr_lc_disable.679240444
Short name	T222
Test name
Test status
Simulation time	33600837 ps
CPU time	2.37 seconds
Started	Sep 11 06:05:51 AM UTC 24
Finished	Sep 11 06:05:54 AM UTC 24
Peak memory	228452 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679240444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.679240444
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/40.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/40.keymgr_random.1426689890
Short name	T778
Test name
Test status
Simulation time	209299549 ps
CPU time	9.06 seconds
Started	Sep 11 06:05:49 AM UTC 24
Finished	Sep 11 06:05:59 AM UTC 24
Peak memory	224028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426689890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1426689890
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/40.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/40.keymgr_sideload.918634730
Short name	T771
Test name
Test status
Simulation time	22056530 ps
CPU time	2.08 seconds
Started	Sep 11 06:05:44 AM UTC 24
Finished	Sep 11 06:05:47 AM UTC 24
Peak memory	215900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918634730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.918634730
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/40.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_aes.2687539429
Short name	T776
Test name
Test status
Simulation time	654688140 ps
CPU time	7.19 seconds
Started	Sep 11 06:05:47 AM UTC 24
Finished	Sep 11 06:05:55 AM UTC 24
Peak memory	217944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687539429 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2687539429
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/40.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_kmac.689145585
Short name	T773
Test name
Test status
Simulation time	96255668 ps
CPU time	4.27 seconds
Started	Sep 11 06:05:44 AM UTC 24
Finished	Sep 11 06:05:50 AM UTC 24
Peak memory	217940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689145585 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.689145585
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/40.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_otbn.1958910566
Short name	T775
Test name
Test status
Simulation time	25514446 ps
CPU time	2.35 seconds
Started	Sep 11 06:05:48 AM UTC 24
Finished	Sep 11 06:05:51 AM UTC 24
Peak memory	217948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958910566 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1958910566
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/40.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_protect.474057566
Short name	T780
Test name
Test status
Simulation time	64699269 ps
CPU time	2.92 seconds
Started	Sep 11 06:05:57 AM UTC 24
Finished	Sep 11 06:06:01 AM UTC 24
Peak memory	230308 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474057566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.474057566
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/40.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/40.keymgr_smoke.741986756
Short name	T772
Test name
Test status
Simulation time	52833844 ps
CPU time	3.23 seconds
Started	Sep 11 06:05:44 AM UTC 24
Finished	Sep 11 06:05:49 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741986756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.741986756
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/40.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all.2427458965
Short name	T790
Test name
Test status
Simulation time	1747133449 ps
CPU time	13.09 seconds
Started	Sep 11 06:05:57 AM UTC 24
Finished	Sep 11 06:06:11 AM UTC 24
Peak memory	226140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427458965 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2427458965
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/40.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all_with_rand_reset.2677769601
Short name	T787
Test name
Test status
Simulation time	233993468 ps
CPU time	10.41 seconds
Started	Sep 11 06:05:58 AM UTC 24
Finished	Sep 11 06:06:10 AM UTC 24
Peak memory	230492 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2677769601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymg r_stress_all_with_rand_reset.2677769601
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/40.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/40.keymgr_sw_invalid_input.2395470947
Short name	T793
Test name
Test status
Simulation time	939040382 ps
CPU time	20.53 seconds
Started	Sep 11 06:05:51 AM UTC 24
Finished	Sep 11 06:06:13 AM UTC 24
Peak memory	217944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395470947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2395470947
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/40.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/40.keymgr_sync_async_fault_cross.2837915168
Short name	T779
Test name
Test status
Simulation time	62589647 ps
CPU time	1.54 seconds
Started	Sep 11 06:05:57 AM UTC 24
Finished	Sep 11 06:06:00 AM UTC 24
Peak memory	217564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837915168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2837915168
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/40.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/41.keymgr_alert_test.1469954820
Short name	T802
Test name
Test status
Simulation time	218563139 ps
CPU time	1.18 seconds
Started	Sep 11 06:06:16 AM UTC 24
Finished	Sep 11 06:06:19 AM UTC 24
Peak memory	214164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469954820 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1469954820
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/41.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/41.keymgr_cfg_regwen.922842050
Short name	T419
Test name
Test status
Simulation time	589047541 ps
CPU time	6.9 seconds
Started	Sep 11 06:06:05 AM UTC 24
Finished	Sep 11 06:06:13 AM UTC 24
Peak memory	226396 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922842050 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.922842050
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/41.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/41.keymgr_custom_cm.3795099167
Short name	T801
Test name
Test status
Simulation time	158406579 ps
CPU time	4.74 seconds
Started	Sep 11 06:06:12 AM UTC 24
Finished	Sep 11 06:06:18 AM UTC 24
Peak memory	228224 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795099167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3795099167
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/41.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/41.keymgr_direct_to_disabled.2144598624
Short name	T794
Test name
Test status
Simulation time	338623753 ps
CPU time	6.81 seconds
Started	Sep 11 06:06:07 AM UTC 24
Finished	Sep 11 06:06:15 AM UTC 24
Peak memory	224060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144598624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2144598624
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/41.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/41.keymgr_kmac_rsp_err.2279575193
Short name	T795
Test name
Test status
Simulation time	66618680 ps
CPU time	2.73 seconds
Started	Sep 11 06:06:12 AM UTC 24
Finished	Sep 11 06:06:16 AM UTC 24
Peak memory	226004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279575193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2279575193
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/41.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/41.keymgr_lc_disable.1510078041
Short name	T789
Test name
Test status
Simulation time	43445699 ps
CPU time	2.48 seconds
Started	Sep 11 06:06:08 AM UTC 24
Finished	Sep 11 06:06:11 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510078041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1510078041
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/41.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/41.keymgr_random.1279737444
Short name	T796
Test name
Test status
Simulation time	1870109571 ps
CPU time	10.12 seconds
Started	Sep 11 06:06:05 AM UTC 24
Finished	Sep 11 06:06:16 AM UTC 24
Peak memory	217884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279737444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1279737444
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/41.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/41.keymgr_sideload.1150604181
Short name	T784
Test name
Test status
Simulation time	22191610 ps
CPU time	1.95 seconds
Started	Sep 11 06:06:01 AM UTC 24
Finished	Sep 11 06:06:04 AM UTC 24
Peak memory	215704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150604181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1150604181
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/41.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_aes.1164304786
Short name	T785
Test name
Test status
Simulation time	45219041 ps
CPU time	2.86 seconds
Started	Sep 11 06:06:03 AM UTC 24
Finished	Sep 11 06:06:06 AM UTC 24
Peak memory	217988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164304786 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1164304786
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/41.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_kmac.1381114949
Short name	T786
Test name
Test status
Simulation time	136579200 ps
CPU time	4.76 seconds
Started	Sep 11 06:06:01 AM UTC 24
Finished	Sep 11 06:06:07 AM UTC 24
Peak memory	216216 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381114949 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1381114949
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/41.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_otbn.2492984148
Short name	T788
Test name
Test status
Simulation time	1411916795 ps
CPU time	6.64 seconds
Started	Sep 11 06:06:03 AM UTC 24
Finished	Sep 11 06:06:10 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492984148 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2492984148
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/41.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_protect.831901980
Short name	T799
Test name
Test status
Simulation time	470581600 ps
CPU time	2.76 seconds
Started	Sep 11 06:06:13 AM UTC 24
Finished	Sep 11 06:06:17 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831901980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.831901980
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/41.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/41.keymgr_smoke.3670432565
Short name	T811
Test name
Test status
Simulation time	4843921790 ps
CPU time	29.55 seconds
Started	Sep 11 06:06:00 AM UTC 24
Finished	Sep 11 06:06:31 AM UTC 24
Peak memory	215900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670432565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3670432565
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/41.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all.2849996575
Short name	T805
Test name
Test status
Simulation time	354466583 ps
CPU time	8.55 seconds
Started	Sep 11 06:06:14 AM UTC 24
Finished	Sep 11 06:06:24 AM UTC 24
Peak memory	232532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849996575 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2849996575
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/41.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all_with_rand_reset.899141594
Short name	T187
Test name
Test status
Simulation time	306442641 ps
CPU time	12.45 seconds
Started	Sep 11 06:06:15 AM UTC 24
Finished	Sep 11 06:06:29 AM UTC 24
Peak memory	232308 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=899141594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr _stress_all_with_rand_reset.899141594
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/41.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/41.keymgr_sw_invalid_input.2281340348
Short name	T798
Test name
Test status
Simulation time	368577665 ps
CPU time	5.06 seconds
Started	Sep 11 06:06:11 AM UTC 24
Finished	Sep 11 06:06:17 AM UTC 24
Peak memory	224208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281340348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2281340348
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/41.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/41.keymgr_sync_async_fault_cross.1834832326
Short name	T800
Test name
Test status
Simulation time	54997386 ps
CPU time	2.84 seconds
Started	Sep 11 06:06:13 AM UTC 24
Finished	Sep 11 06:06:17 AM UTC 24
Peak memory	219800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834832326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1834832326
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/41.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/42.keymgr_alert_test.3978846374
Short name	T814
Test name
Test status
Simulation time	11361900 ps
CPU time	1.08 seconds
Started	Sep 11 06:06:31 AM UTC 24
Finished	Sep 11 06:06:34 AM UTC 24
Peak memory	214164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978846374 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3978846374
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/42.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/42.keymgr_cfg_regwen.1257624357
Short name	T438
Test name
Test status
Simulation time	15559207259 ps
CPU time	73.82 seconds
Started	Sep 11 06:06:20 AM UTC 24
Finished	Sep 11 06:07:36 AM UTC 24
Peak memory	226176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257624357 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1257624357
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/42.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/42.keymgr_custom_cm.673642824
Short name	T812
Test name
Test status
Simulation time	226849304 ps
CPU time	3.45 seconds
Started	Sep 11 06:06:27 AM UTC 24
Finished	Sep 11 06:06:32 AM UTC 24
Peak memory	218552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673642824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.673642824
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/42.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/42.keymgr_direct_to_disabled.3672291772
Short name	T806
Test name
Test status
Simulation time	208934874 ps
CPU time	2.09 seconds
Started	Sep 11 06:06:22 AM UTC 24
Finished	Sep 11 06:06:25 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672291772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3672291772
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/42.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/42.keymgr_hwsw_invalid_input.1028894883
Short name	T816
Test name
Test status
Simulation time	1054527209 ps
CPU time	9.95 seconds
Started	Sep 11 06:06:26 AM UTC 24
Finished	Sep 11 06:06:37 AM UTC 24
Peak memory	224436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028894883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1028894883
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/42.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/42.keymgr_kmac_rsp_err.432288707
Short name	T290
Test name
Test status
Simulation time	306417594 ps
CPU time	3.3 seconds
Started	Sep 11 06:06:26 AM UTC 24
Finished	Sep 11 06:06:30 AM UTC 24
Peak memory	219944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432288707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.432288707
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/42.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/42.keymgr_random.2370386257
Short name	T843
Test name
Test status
Simulation time	5530747930 ps
CPU time	53.29 seconds
Started	Sep 11 06:06:19 AM UTC 24
Finished	Sep 11 06:07:14 AM UTC 24
Peak memory	228552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370386257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2370386257
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/42.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/42.keymgr_sideload.3704331018
Short name	T809
Test name
Test status
Simulation time	724090853 ps
CPU time	9.47 seconds
Started	Sep 11 06:06:16 AM UTC 24
Finished	Sep 11 06:06:27 AM UTC 24
Peak memory	217880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704331018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3704331018
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/42.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_aes.1216161566
Short name	T804
Test name
Test status
Simulation time	39126752 ps
CPU time	3.07 seconds
Started	Sep 11 06:06:18 AM UTC 24
Finished	Sep 11 06:06:22 AM UTC 24
Peak memory	218308 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216161566 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1216161566
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/42.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_kmac.1765998214
Short name	T807
Test name
Test status
Simulation time	196202507 ps
CPU time	6.76 seconds
Started	Sep 11 06:06:18 AM UTC 24
Finished	Sep 11 06:06:25 AM UTC 24
Peak memory	217944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765998214 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1765998214
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/42.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_otbn.3744733615
Short name	T808
Test name
Test status
Simulation time	773235602 ps
CPU time	7 seconds
Started	Sep 11 06:06:18 AM UTC 24
Finished	Sep 11 06:06:26 AM UTC 24
Peak memory	217944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744733615 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3744733615
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/42.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_protect.2113463378
Short name	T813
Test name
Test status
Simulation time	160537215 ps
CPU time	4.18 seconds
Started	Sep 11 06:06:28 AM UTC 24
Finished	Sep 11 06:06:33 AM UTC 24
Peak memory	228284 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113463378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2113463378
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/42.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/42.keymgr_smoke.1654051323
Short name	T803
Test name
Test status
Simulation time	262091009 ps
CPU time	3.37 seconds
Started	Sep 11 06:06:16 AM UTC 24
Finished	Sep 11 06:06:21 AM UTC 24
Peak memory	218208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654051323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1654051323
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/42.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all_with_rand_reset.3585211406
Short name	T826
Test name
Test status
Simulation time	2111476176 ps
CPU time	20.67 seconds
Started	Sep 11 06:06:31 AM UTC 24
Finished	Sep 11 06:06:53 AM UTC 24
Peak memory	232664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3585211406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymg r_stress_all_with_rand_reset.3585211406
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/42.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/42.keymgr_sw_invalid_input.2163885553
Short name	T810
Test name
Test status
Simulation time	151455669 ps
CPU time	4.45 seconds
Started	Sep 11 06:06:25 AM UTC 24
Finished	Sep 11 06:06:31 AM UTC 24
Peak memory	217948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163885553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2163885553
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/42.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/42.keymgr_sync_async_fault_cross.1844044533
Short name	T815
Test name
Test status
Simulation time	226529097 ps
CPU time	6.1 seconds
Started	Sep 11 06:06:29 AM UTC 24
Finished	Sep 11 06:06:36 AM UTC 24
Peak memory	217884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844044533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1844044533
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/42.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/43.keymgr_alert_test.4106802176
Short name	T830
Test name
Test status
Simulation time	20329527 ps
CPU time	1.29 seconds
Started	Sep 11 06:06:56 AM UTC 24
Finished	Sep 11 06:06:59 AM UTC 24
Peak memory	213660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106802176 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.4106802176
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/43.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/43.keymgr_cfg_regwen.1326260596
Short name	T824
Test name
Test status
Simulation time	687368204 ps
CPU time	10.24 seconds
Started	Sep 11 06:06:39 AM UTC 24
Finished	Sep 11 06:06:50 AM UTC 24
Peak memory	224096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326260596 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1326260596
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/43.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/43.keymgr_custom_cm.2661116861
Short name	T829
Test name
Test status
Simulation time	602531429 ps
CPU time	5.06 seconds
Started	Sep 11 06:06:51 AM UTC 24
Finished	Sep 11 06:06:57 AM UTC 24
Peak memory	218016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661116861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2661116861
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/43.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/43.keymgr_direct_to_disabled.1293898078
Short name	T821
Test name
Test status
Simulation time	153690313 ps
CPU time	3.85 seconds
Started	Sep 11 06:06:41 AM UTC 24
Finished	Sep 11 06:06:46 AM UTC 24
Peak memory	217900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293898078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1293898078
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/43.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/43.keymgr_hwsw_invalid_input.4217935152
Short name	T823
Test name
Test status
Simulation time	92987717 ps
CPU time	1.98 seconds
Started	Sep 11 06:06:47 AM UTC 24
Finished	Sep 11 06:06:50 AM UTC 24
Peak memory	223544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217935152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.4217935152
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/43.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/43.keymgr_kmac_rsp_err.3909531812
Short name	T825
Test name
Test status
Simulation time	64884453 ps
CPU time	1.87 seconds
Started	Sep 11 06:06:48 AM UTC 24
Finished	Sep 11 06:06:51 AM UTC 24
Peak memory	223520 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909531812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3909531812
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/43.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/43.keymgr_lc_disable.1511324631
Short name	T822
Test name
Test status
Simulation time	138181437 ps
CPU time	2.41 seconds
Started	Sep 11 06:06:44 AM UTC 24
Finished	Sep 11 06:06:47 AM UTC 24
Peak memory	230176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511324631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1511324631
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/43.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/43.keymgr_random.2463219021
Short name	T841
Test name
Test status
Simulation time	4361156651 ps
CPU time	34.24 seconds
Started	Sep 11 06:06:38 AM UTC 24
Finished	Sep 11 06:07:14 AM UTC 24
Peak memory	217940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463219021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2463219021
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/43.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/43.keymgr_sideload.122390410
Short name	T817
Test name
Test status
Simulation time	374093232 ps
CPU time	4.08 seconds
Started	Sep 11 06:06:32 AM UTC 24
Finished	Sep 11 06:06:38 AM UTC 24
Peak memory	216220 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122390410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.122390410
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/43.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_aes.2097698238
Short name	T820
Test name
Test status
Simulation time	338778168 ps
CPU time	7.46 seconds
Started	Sep 11 06:06:35 AM UTC 24
Finished	Sep 11 06:06:43 AM UTC 24
Peak memory	217860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097698238 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2097698238
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/43.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_kmac.4106685307
Short name	T831
Test name
Test status
Simulation time	4881572910 ps
CPU time	25.26 seconds
Started	Sep 11 06:06:35 AM UTC 24
Finished	Sep 11 06:07:02 AM UTC 24
Peak memory	217992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106685307 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.4106685307
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/43.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_otbn.2686082388
Short name	T819
Test name
Test status
Simulation time	305967306 ps
CPU time	4.46 seconds
Started	Sep 11 06:06:38 AM UTC 24
Finished	Sep 11 06:06:43 AM UTC 24
Peak memory	217872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686082388 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2686082388
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/43.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_protect.334553760
Short name	T346
Test name
Test status
Simulation time	107105283 ps
CPU time	3.49 seconds
Started	Sep 11 06:06:51 AM UTC 24
Finished	Sep 11 06:06:56 AM UTC 24
Peak memory	226468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334553760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.334553760
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/43.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/43.keymgr_smoke.1436404459
Short name	T818
Test name
Test status
Simulation time	189703245 ps
CPU time	6.81 seconds
Started	Sep 11 06:06:32 AM UTC 24
Finished	Sep 11 06:06:40 AM UTC 24
Peak memory	218144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436404459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1436404459
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/43.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/43.keymgr_stress_all.20584352
Short name	T834
Test name
Test status
Simulation time	684658072 ps
CPU time	9.65 seconds
Started	Sep 11 06:06:54 AM UTC 24
Finished	Sep 11 06:07:05 AM UTC 24
Peak memory	228184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20584352 -assert nopostproc +UVM_TESTNAME=ke ymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.20584352
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/43.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/43.keymgr_sw_invalid_input.50158141
Short name	T827
Test name
Test status
Simulation time	1230599963 ps
CPU time	9.79 seconds
Started	Sep 11 06:06:44 AM UTC 24
Finished	Sep 11 06:06:55 AM UTC 24
Peak memory	224344 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50158141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.50158141
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/43.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/43.keymgr_sync_async_fault_cross.624211454
Short name	T828
Test name
Test status
Simulation time	243954208 ps
CPU time	3.73 seconds
Started	Sep 11 06:06:52 AM UTC 24
Finished	Sep 11 06:06:57 AM UTC 24
Peak memory	220000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624211454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.624211454
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/43.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/44.keymgr_alert_test.2116169897
Short name	T845
Test name
Test status
Simulation time	68175875 ps
CPU time	0.99 seconds
Started	Sep 11 06:07:15 AM UTC 24
Finished	Sep 11 06:07:17 AM UTC 24
Peak memory	213532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116169897 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2116169897
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/44.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/44.keymgr_cfg_regwen.1683635646
Short name	T435
Test name
Test status
Simulation time	3804453622 ps
CPU time	38.61 seconds
Started	Sep 11 06:07:05 AM UTC 24
Finished	Sep 11 06:07:45 AM UTC 24
Peak memory	224088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683635646 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1683635646
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/44.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/44.keymgr_direct_to_disabled.2310254216
Short name	T837
Test name
Test status
Simulation time	55619739 ps
CPU time	2.23 seconds
Started	Sep 11 06:07:06 AM UTC 24
Finished	Sep 11 06:07:09 AM UTC 24
Peak memory	224208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310254216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2310254216
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/44.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/44.keymgr_hwsw_invalid_input.133082154
Short name	T842
Test name
Test status
Simulation time	188595138 ps
CPU time	2.65 seconds
Started	Sep 11 06:07:10 AM UTC 24
Finished	Sep 11 06:07:14 AM UTC 24
Peak memory	226144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133082154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.133082154
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/44.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/44.keymgr_kmac_rsp_err.3283578712
Short name	T844
Test name
Test status
Simulation time	68287944 ps
CPU time	2.68 seconds
Started	Sep 11 06:07:11 AM UTC 24
Finished	Sep 11 06:07:15 AM UTC 24
Peak memory	230336 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283578712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3283578712
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/44.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/44.keymgr_lc_disable.3541518191
Short name	T846
Test name
Test status
Simulation time	203142143 ps
CPU time	10.89 seconds
Started	Sep 11 06:07:07 AM UTC 24
Finished	Sep 11 06:07:19 AM UTC 24
Peak memory	230624 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541518191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3541518191
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/44.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/44.keymgr_random.4081270351
Short name	T838
Test name
Test status
Simulation time	491546143 ps
CPU time	4.86 seconds
Started	Sep 11 06:07:05 AM UTC 24
Finished	Sep 11 06:07:11 AM UTC 24
Peak memory	215816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081270351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.4081270351
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/44.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/44.keymgr_sideload.3104246270
Short name	T832
Test name
Test status
Simulation time	112034865 ps
CPU time	4.12 seconds
Started	Sep 11 06:06:59 AM UTC 24
Finished	Sep 11 06:07:04 AM UTC 24
Peak memory	217908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104246270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3104246270
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/44.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_aes.487263355
Short name	T835
Test name
Test status
Simulation time	742252945 ps
CPU time	4.46 seconds
Started	Sep 11 06:07:01 AM UTC 24
Finished	Sep 11 06:07:06 AM UTC 24
Peak memory	217972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487263355 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.487263355
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/44.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_kmac.1932113166
Short name	T833
Test name
Test status
Simulation time	63633416 ps
CPU time	3.47 seconds
Started	Sep 11 06:07:00 AM UTC 24
Finished	Sep 11 06:07:04 AM UTC 24
Peak memory	216156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932113166 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1932113166
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/44.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_otbn.2161576701
Short name	T836
Test name
Test status
Simulation time	183702920 ps
CPU time	2.61 seconds
Started	Sep 11 06:07:03 AM UTC 24
Finished	Sep 11 06:07:06 AM UTC 24
Peak memory	216156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161576701 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2161576701
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/44.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_protect.264699720
Short name	T849
Test name
Test status
Simulation time	230225966 ps
CPU time	8.25 seconds
Started	Sep 11 06:07:14 AM UTC 24
Finished	Sep 11 06:07:24 AM UTC 24
Peak memory	230324 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264699720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.264699720
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/44.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/44.keymgr_smoke.3801509611
Short name	T840
Test name
Test status
Simulation time	2481155360 ps
CPU time	14.25 seconds
Started	Sep 11 06:06:57 AM UTC 24
Finished	Sep 11 06:07:13 AM UTC 24
Peak memory	217876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801509611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3801509611
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/44.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/44.keymgr_sw_invalid_input.2525884284
Short name	T839
Test name
Test status
Simulation time	215289452 ps
CPU time	4.35 seconds
Started	Sep 11 06:07:07 AM UTC 24
Finished	Sep 11 06:07:12 AM UTC 24
Peak memory	226068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525884284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2525884284
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/44.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/44.keymgr_sync_async_fault_cross.3159693019
Short name	T166
Test name
Test status
Simulation time	46432700 ps
CPU time	2.13 seconds
Started	Sep 11 06:07:14 AM UTC 24
Finished	Sep 11 06:07:17 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159693019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3159693019
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/44.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/45.keymgr_alert_test.746549590
Short name	T847
Test name
Test status
Simulation time	42103621 ps
CPU time	1.09 seconds
Started	Sep 11 06:07:36 AM UTC 24
Finished	Sep 11 06:07:39 AM UTC 24
Peak memory	213588 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746549590 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.746549590
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/45.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/45.keymgr_cfg_regwen.1836392229
Short name	T856
Test name
Test status
Simulation time	191760006 ps
CPU time	4.25 seconds
Started	Sep 11 06:07:25 AM UTC 24
Finished	Sep 11 06:07:30 AM UTC 24
Peak memory	226084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836392229 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1836392229
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/45.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/45.keymgr_custom_cm.801563982
Short name	T753
Test name
Test status
Simulation time	413207243 ps
CPU time	12.71 seconds
Started	Sep 11 06:07:30 AM UTC 24
Finished	Sep 11 06:07:44 AM UTC 24
Peak memory	231652 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801563982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.801563982
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/45.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/45.keymgr_direct_to_disabled.1667547369
Short name	T859
Test name
Test status
Simulation time	1327842435 ps
CPU time	8.88 seconds
Started	Sep 11 06:07:26 AM UTC 24
Finished	Sep 11 06:07:36 AM UTC 24
Peak memory	224096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667547369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1667547369
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/45.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/45.keymgr_hwsw_invalid_input.1412417714
Short name	T857
Test name
Test status
Simulation time	26716485 ps
CPU time	2.48 seconds
Started	Sep 11 06:07:29 AM UTC 24
Finished	Sep 11 06:07:33 AM UTC 24
Peak memory	226504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412417714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1412417714
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/45.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/45.keymgr_kmac_rsp_err.1301559102
Short name	T862
Test name
Test status
Simulation time	189088700 ps
CPU time	7.44 seconds
Started	Sep 11 06:07:29 AM UTC 24
Finished	Sep 11 06:07:38 AM UTC 24
Peak memory	224292 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301559102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1301559102
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/45.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/45.keymgr_lc_disable.2833909594
Short name	T855
Test name
Test status
Simulation time	31507988 ps
CPU time	2.46 seconds
Started	Sep 11 06:07:26 AM UTC 24
Finished	Sep 11 06:07:29 AM UTC 24
Peak memory	230248 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833909594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2833909594
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/45.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/45.keymgr_random.1206466754
Short name	T853
Test name
Test status
Simulation time	59707844 ps
CPU time	2.93 seconds
Started	Sep 11 06:07:24 AM UTC 24
Finished	Sep 11 06:07:28 AM UTC 24
Peak memory	215864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206466754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1206466754
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/45.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/45.keymgr_sideload.2415023966
Short name	T854
Test name
Test status
Simulation time	3108872917 ps
CPU time	8.22 seconds
Started	Sep 11 06:07:19 AM UTC 24
Finished	Sep 11 06:07:28 AM UTC 24
Peak memory	217916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415023966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2415023966
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/45.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_aes.4011203473
Short name	T851
Test name
Test status
Simulation time	110068895 ps
CPU time	4.26 seconds
Started	Sep 11 06:07:20 AM UTC 24
Finished	Sep 11 06:07:25 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011203473 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.4011203473
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/45.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_kmac.735798817
Short name	T848
Test name
Test status
Simulation time	179656742 ps
CPU time	2.79 seconds
Started	Sep 11 06:07:20 AM UTC 24
Finished	Sep 11 06:07:23 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735798817 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.735798817
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/45.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_otbn.2917265436
Short name	T852
Test name
Test status
Simulation time	96255669 ps
CPU time	2.72 seconds
Started	Sep 11 06:07:24 AM UTC 24
Finished	Sep 11 06:07:28 AM UTC 24
Peak memory	216152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917265436 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2917265436
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/45.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_protect.1732993785
Short name	T860
Test name
Test status
Simulation time	153043541 ps
CPU time	4.09 seconds
Started	Sep 11 06:07:31 AM UTC 24
Finished	Sep 11 06:07:36 AM UTC 24
Peak memory	228288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732993785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1732993785
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/45.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/45.keymgr_smoke.1986826009
Short name	T850
Test name
Test status
Simulation time	213690374 ps
CPU time	5.12 seconds
Started	Sep 11 06:07:18 AM UTC 24
Finished	Sep 11 06:07:25 AM UTC 24
Peak memory	215708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986826009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1986826009
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/45.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/45.keymgr_stress_all.3391673051
Short name	T232
Test name
Test status
Simulation time	5815534670 ps
CPU time	17.42 seconds
Started	Sep 11 06:07:34 AM UTC 24
Finished	Sep 11 06:07:53 AM UTC 24
Peak memory	232200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391673051 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3391673051
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/45.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/45.keymgr_sw_invalid_input.3180197942
Short name	T858
Test name
Test status
Simulation time	308525488 ps
CPU time	4.62 seconds
Started	Sep 11 06:07:28 AM UTC 24
Finished	Sep 11 06:07:34 AM UTC 24
Peak memory	215936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180197942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3180197942
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/45.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/45.keymgr_sync_async_fault_cross.2713451563
Short name	T861
Test name
Test status
Simulation time	104195176 ps
CPU time	2.54 seconds
Started	Sep 11 06:07:33 AM UTC 24
Finished	Sep 11 06:07:37 AM UTC 24
Peak memory	219932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713451563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2713451563
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/45.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/46.keymgr_alert_test.1335869819
Short name	T873
Test name
Test status
Simulation time	44363224 ps
CPU time	1.08 seconds
Started	Sep 11 06:07:54 AM UTC 24
Finished	Sep 11 06:07:56 AM UTC 24
Peak memory	214160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335869819 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1335869819
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/46.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/46.keymgr_custom_cm.1964489281
Short name	T874
Test name
Test status
Simulation time	522635947 ps
CPU time	5.74 seconds
Started	Sep 11 06:07:50 AM UTC 24
Finished	Sep 11 06:07:57 AM UTC 24
Peak memory	224404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964489281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1964489281
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/46.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/46.keymgr_direct_to_disabled.1403740144
Short name	T867
Test name
Test status
Simulation time	278823166 ps
CPU time	3.97 seconds
Started	Sep 11 06:07:45 AM UTC 24
Finished	Sep 11 06:07:50 AM UTC 24
Peak memory	224416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403740144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1403740144
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/46.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/46.keymgr_hwsw_invalid_input.894785795
Short name	T866
Test name
Test status
Simulation time	30170569 ps
CPU time	2.43 seconds
Started	Sep 11 06:07:46 AM UTC 24
Finished	Sep 11 06:07:50 AM UTC 24
Peak memory	226400 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894785795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.894785795
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/46.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/46.keymgr_kmac_rsp_err.3475576379
Short name	T868
Test name
Test status
Simulation time	316449443 ps
CPU time	3.82 seconds
Started	Sep 11 06:07:46 AM UTC 24
Finished	Sep 11 06:07:51 AM UTC 24
Peak memory	223968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475576379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3475576379
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/46.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/46.keymgr_lc_disable.3786117316
Short name	T227
Test name
Test status
Simulation time	714929038 ps
CPU time	10 seconds
Started	Sep 11 06:07:45 AM UTC 24
Finished	Sep 11 06:07:56 AM UTC 24
Peak memory	218216 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786117316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3786117316
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/46.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/46.keymgr_random.4193431082
Short name	T865
Test name
Test status
Simulation time	116283089 ps
CPU time	5.64 seconds
Started	Sep 11 06:07:43 AM UTC 24
Finished	Sep 11 06:07:49 AM UTC 24
Peak memory	218300 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193431082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.4193431082
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/46.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/46.keymgr_sideload.3145704548
Short name	T792
Test name
Test status
Simulation time	336575053 ps
CPU time	3.2 seconds
Started	Sep 11 06:07:38 AM UTC 24
Finished	Sep 11 06:07:42 AM UTC 24
Peak memory	216156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145704548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3145704548
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/46.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_aes.2723207395
Short name	T864
Test name
Test status
Simulation time	557977468 ps
CPU time	4.97 seconds
Started	Sep 11 06:07:40 AM UTC 24
Finished	Sep 11 06:07:46 AM UTC 24
Peak memory	216152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723207395 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2723207395
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/46.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_kmac.459671499
Short name	T791
Test name
Test status
Simulation time	174028654 ps
CPU time	5.7 seconds
Started	Sep 11 06:07:39 AM UTC 24
Finished	Sep 11 06:07:45 AM UTC 24
Peak memory	217884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459671499 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.459671499
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/46.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_otbn.2988995570
Short name	T880
Test name
Test status
Simulation time	707709127 ps
CPU time	19.39 seconds
Started	Sep 11 06:07:42 AM UTC 24
Finished	Sep 11 06:08:02 AM UTC 24
Peak memory	217948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988995570 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2988995570
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/46.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_protect.32649926
Short name	T871
Test name
Test status
Simulation time	104544250 ps
CPU time	2.94 seconds
Started	Sep 11 06:07:50 AM UTC 24
Finished	Sep 11 06:07:54 AM UTC 24
Peak memory	228256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32649926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.32649926
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/46.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/46.keymgr_smoke.2753948458
Short name	T870
Test name
Test status
Simulation time	1287108930 ps
CPU time	15.33 seconds
Started	Sep 11 06:07:38 AM UTC 24
Finished	Sep 11 06:07:54 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753948458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2753948458
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/46.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/46.keymgr_stress_all.3978653108
Short name	T881
Test name
Test status
Simulation time	817387726 ps
CPU time	9.15 seconds
Started	Sep 11 06:07:52 AM UTC 24
Finished	Sep 11 06:08:03 AM UTC 24
Peak memory	230492 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978653108 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3978653108
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/46.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/46.keymgr_sw_invalid_input.1063767233
Short name	T869
Test name
Test status
Simulation time	136568363 ps
CPU time	5.41 seconds
Started	Sep 11 06:07:46 AM UTC 24
Finished	Sep 11 06:07:53 AM UTC 24
Peak memory	224024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063767233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1063767233
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/46.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/46.keymgr_sync_async_fault_cross.4189347335
Short name	T872
Test name
Test status
Simulation time	41143984 ps
CPU time	2.42 seconds
Started	Sep 11 06:07:51 AM UTC 24
Finished	Sep 11 06:07:55 AM UTC 24
Peak memory	217884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189347335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.4189347335
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/46.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/47.keymgr_alert_test.149363949
Short name	T888
Test name
Test status
Simulation time	77211561 ps
CPU time	0.91 seconds
Started	Sep 11 06:08:06 AM UTC 24
Finished	Sep 11 06:08:08 AM UTC 24
Peak memory	214156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149363949 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.149363949
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/47.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/47.keymgr_cfg_regwen.583578625
Short name	T436
Test name
Test status
Simulation time	94744552 ps
CPU time	4.15 seconds
Started	Sep 11 06:07:59 AM UTC 24
Finished	Sep 11 06:08:05 AM UTC 24
Peak memory	226068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583578625 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.583578625
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/47.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/47.keymgr_custom_cm.3710197340
Short name	T277
Test name
Test status
Simulation time	305750555 ps
CPU time	5.36 seconds
Started	Sep 11 06:08:03 AM UTC 24
Finished	Sep 11 06:08:10 AM UTC 24
Peak memory	230664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710197340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3710197340
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/47.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/47.keymgr_direct_to_disabled.3781662184
Short name	T879
Test name
Test status
Simulation time	85960014 ps
CPU time	1.44 seconds
Started	Sep 11 06:07:59 AM UTC 24
Finished	Sep 11 06:08:02 AM UTC 24
Peak memory	215700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781662184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3781662184
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/47.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/47.keymgr_kmac_rsp_err.4067102694
Short name	T889
Test name
Test status
Simulation time	869916595 ps
CPU time	6.65 seconds
Started	Sep 11 06:08:01 AM UTC 24
Finished	Sep 11 06:08:09 AM UTC 24
Peak memory	232264 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067102694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.4067102694
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/47.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/47.keymgr_lc_disable.3116851584
Short name	T884
Test name
Test status
Simulation time	339976498 ps
CPU time	4.47 seconds
Started	Sep 11 06:08:00 AM UTC 24
Finished	Sep 11 06:08:06 AM UTC 24
Peak memory	217884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116851584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3116851584
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/47.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/47.keymgr_random.2624595314
Short name	T882
Test name
Test status
Simulation time	272425429 ps
CPU time	4.08 seconds
Started	Sep 11 06:07:58 AM UTC 24
Finished	Sep 11 06:08:04 AM UTC 24
Peak memory	226396 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624595314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2624595314
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/47.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/47.keymgr_sideload.1357119195
Short name	T875
Test name
Test status
Simulation time	26201287 ps
CPU time	2.38 seconds
Started	Sep 11 06:07:55 AM UTC 24
Finished	Sep 11 06:07:59 AM UTC 24
Peak memory	217880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357119195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1357119195
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/47.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_aes.1483331172
Short name	T878
Test name
Test status
Simulation time	133816150 ps
CPU time	2.86 seconds
Started	Sep 11 06:07:57 AM UTC 24
Finished	Sep 11 06:08:01 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483331172 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1483331172
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/47.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_kmac.962867836
Short name	T883
Test name
Test status
Simulation time	735100332 ps
CPU time	7.15 seconds
Started	Sep 11 06:07:56 AM UTC 24
Finished	Sep 11 06:08:04 AM UTC 24
Peak memory	217980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962867836 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.962867836
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/47.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_otbn.1318244822
Short name	T877
Test name
Test status
Simulation time	122699579 ps
CPU time	2.64 seconds
Started	Sep 11 06:07:57 AM UTC 24
Finished	Sep 11 06:08:01 AM UTC 24
Peak memory	216152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318244822 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1318244822
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/47.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_protect.3337930582
Short name	T887
Test name
Test status
Simulation time	108381514 ps
CPU time	2.78 seconds
Started	Sep 11 06:08:03 AM UTC 24
Finished	Sep 11 06:08:07 AM UTC 24
Peak memory	226204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337930582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3337930582
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/47.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/47.keymgr_smoke.214054317
Short name	T876
Test name
Test status
Simulation time	214528215 ps
CPU time	3.46 seconds
Started	Sep 11 06:07:55 AM UTC 24
Finished	Sep 11 06:08:00 AM UTC 24
Peak memory	218096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214054317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.214054317
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/47.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all_with_rand_reset.1791095028
Short name	T898
Test name
Test status
Simulation time	749731643 ps
CPU time	14.26 seconds
Started	Sep 11 06:08:04 AM UTC 24
Finished	Sep 11 06:08:20 AM UTC 24
Peak memory	232392 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1791095028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymg r_stress_all_with_rand_reset.1791095028
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/47.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/47.keymgr_sw_invalid_input.2926998813
Short name	T885
Test name
Test status
Simulation time	527052269 ps
CPU time	4.86 seconds
Started	Sep 11 06:08:00 AM UTC 24
Finished	Sep 11 06:08:06 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926998813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2926998813
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/47.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/47.keymgr_sync_async_fault_cross.2870094479
Short name	T886
Test name
Test status
Simulation time	186556093 ps
CPU time	2.57 seconds
Started	Sep 11 06:08:03 AM UTC 24
Finished	Sep 11 06:08:07 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870094479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2870094479
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/47.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/48.keymgr_alert_test.3657505103
Short name	T901
Test name
Test status
Simulation time	28378347 ps
CPU time	0.97 seconds
Started	Sep 11 06:08:23 AM UTC 24
Finished	Sep 11 06:08:25 AM UTC 24
Peak memory	213532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657505103 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3657505103
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/48.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/48.keymgr_cfg_regwen.3910462575
Short name	T426
Test name
Test status
Simulation time	222733482 ps
CPU time	13.5 seconds
Started	Sep 11 06:08:10 AM UTC 24
Finished	Sep 11 06:08:25 AM UTC 24
Peak memory	226400 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910462575 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3910462575
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/48.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/48.keymgr_custom_cm.3499260170
Short name	T900
Test name
Test status
Simulation time	126978486 ps
CPU time	3.67 seconds
Started	Sep 11 06:08:19 AM UTC 24
Finished	Sep 11 06:08:24 AM UTC 24
Peak memory	228456 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499260170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3499260170
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/48.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/48.keymgr_direct_to_disabled.1689399503
Short name	T893
Test name
Test status
Simulation time	59749495 ps
CPU time	3.1 seconds
Started	Sep 11 06:08:11 AM UTC 24
Finished	Sep 11 06:08:15 AM UTC 24
Peak memory	224104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689399503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1689399503
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/48.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/48.keymgr_hwsw_invalid_input.279556584
Short name	T895
Test name
Test status
Simulation time	64252444 ps
CPU time	3.13 seconds
Started	Sep 11 06:08:14 AM UTC 24
Finished	Sep 11 06:08:18 AM UTC 24
Peak memory	226140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279556584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.279556584
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/48.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/48.keymgr_kmac_rsp_err.1643176596
Short name	T334
Test name
Test status
Simulation time	315890038 ps
CPU time	4.35 seconds
Started	Sep 11 06:08:16 AM UTC 24
Finished	Sep 11 06:08:22 AM UTC 24
Peak memory	215944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643176596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1643176596
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/48.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/48.keymgr_lc_disable.2623256276
Short name	T897
Test name
Test status
Simulation time	117236675 ps
CPU time	5.88 seconds
Started	Sep 11 06:08:12 AM UTC 24
Finished	Sep 11 06:08:19 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623256276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2623256276
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/48.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/48.keymgr_random.2335725262
Short name	T363
Test name
Test status
Simulation time	501691831 ps
CPU time	11.69 seconds
Started	Sep 11 06:08:09 AM UTC 24
Finished	Sep 11 06:08:22 AM UTC 24
Peak memory	230320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335725262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2335725262
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/48.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/48.keymgr_sideload.1275162878
Short name	T894
Test name
Test status
Simulation time	1773323791 ps
CPU time	10.15 seconds
Started	Sep 11 06:08:07 AM UTC 24
Finished	Sep 11 06:08:18 AM UTC 24
Peak memory	217880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275162878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1275162878
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/48.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_aes.1051839696
Short name	T917
Test name
Test status
Simulation time	5246865793 ps
CPU time	46 seconds
Started	Sep 11 06:08:08 AM UTC 24
Finished	Sep 11 06:08:56 AM UTC 24
Peak memory	218264 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051839696 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1051839696
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/48.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_kmac.3490191749
Short name	T892
Test name
Test status
Simulation time	1323377128 ps
CPU time	4.53 seconds
Started	Sep 11 06:08:08 AM UTC 24
Finished	Sep 11 06:08:13 AM UTC 24
Peak memory	217948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490191749 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3490191749
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/48.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_otbn.3914535374
Short name	T891
Test name
Test status
Simulation time	255769201 ps
CPU time	3.75 seconds
Started	Sep 11 06:08:08 AM UTC 24
Finished	Sep 11 06:08:13 AM UTC 24
Peak memory	217972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914535374 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3914535374
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/48.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_protect.1125327598
Short name	T384
Test name
Test status
Simulation time	89578512 ps
CPU time	4.25 seconds
Started	Sep 11 06:08:19 AM UTC 24
Finished	Sep 11 06:08:25 AM UTC 24
Peak memory	226212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125327598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1125327598
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/48.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/48.keymgr_smoke.180107840
Short name	T890
Test name
Test status
Simulation time	91588797 ps
CPU time	3.16 seconds
Started	Sep 11 06:08:07 AM UTC 24
Finished	Sep 11 06:08:11 AM UTC 24
Peak memory	217812 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180107840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.180107840
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/48.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all_with_rand_reset.2610496053
Short name	T903
Test name
Test status
Simulation time	295791665 ps
CPU time	5.29 seconds
Started	Sep 11 06:08:20 AM UTC 24
Finished	Sep 11 06:08:27 AM UTC 24
Peak memory	232340 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2610496053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymg r_stress_all_with_rand_reset.2610496053
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/48.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/48.keymgr_sw_invalid_input.4154809954
Short name	T896
Test name
Test status
Simulation time	150617731 ps
CPU time	4.4 seconds
Started	Sep 11 06:08:13 AM UTC 24
Finished	Sep 11 06:08:19 AM UTC 24
Peak memory	217900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154809954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.4154809954
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/48.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/48.keymgr_sync_async_fault_cross.3822358670
Short name	T899
Test name
Test status
Simulation time	140331569 ps
CPU time	1.57 seconds
Started	Sep 11 06:08:19 AM UTC 24
Finished	Sep 11 06:08:22 AM UTC 24
Peak memory	217564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822358670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3822358670
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/48.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/49.keymgr_alert_test.3764316135
Short name	T916
Test name
Test status
Simulation time	27884142 ps
CPU time	1.08 seconds
Started	Sep 11 06:08:41 AM UTC 24
Finished	Sep 11 06:08:43 AM UTC 24
Peak memory	213532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764316135 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3764316135
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/49.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/49.keymgr_cfg_regwen.3649674579
Short name	T427
Test name
Test status
Simulation time	1622005588 ps
CPU time	45.15 seconds
Started	Sep 11 06:08:27 AM UTC 24
Finished	Sep 11 06:09:14 AM UTC 24
Peak memory	226400 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649674579 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3649674579
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/49.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/49.keymgr_custom_cm.3893040893
Short name	T914
Test name
Test status
Simulation time	397112717 ps
CPU time	3.91 seconds
Started	Sep 11 06:08:35 AM UTC 24
Finished	Sep 11 06:08:40 AM UTC 24
Peak memory	232664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893040893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3893040893
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/49.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/49.keymgr_direct_to_disabled.3368315874
Short name	T907
Test name
Test status
Simulation time	97392647 ps
CPU time	3.82 seconds
Started	Sep 11 06:08:28 AM UTC 24
Finished	Sep 11 06:08:33 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368315874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3368315874
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/49.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/49.keymgr_hwsw_invalid_input.3670197681
Short name	T909
Test name
Test status
Simulation time	79034319 ps
CPU time	2.32 seconds
Started	Sep 11 06:08:32 AM UTC 24
Finished	Sep 11 06:08:36 AM UTC 24
Peak memory	224024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670197681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3670197681
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/49.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/49.keymgr_kmac_rsp_err.3611535656
Short name	T911
Test name
Test status
Simulation time	43336355 ps
CPU time	2.59 seconds
Started	Sep 11 06:08:33 AM UTC 24
Finished	Sep 11 06:08:37 AM UTC 24
Peak memory	226084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611535656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3611535656
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/49.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/49.keymgr_lc_disable.1348765826
Short name	T908
Test name
Test status
Simulation time	157780964 ps
CPU time	4.76 seconds
Started	Sep 11 06:08:29 AM UTC 24
Finished	Sep 11 06:08:35 AM UTC 24
Peak memory	230348 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348765826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1348765826
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/49.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/49.keymgr_random.2212538638
Short name	T906
Test name
Test status
Simulation time	191194569 ps
CPU time	4.95 seconds
Started	Sep 11 06:08:26 AM UTC 24
Finished	Sep 11 06:08:32 AM UTC 24
Peak memory	224020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212538638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2212538638
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/49.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/49.keymgr_sideload.1850742630
Short name	T904
Test name
Test status
Simulation time	287880582 ps
CPU time	4.77 seconds
Started	Sep 11 06:08:23 AM UTC 24
Finished	Sep 11 06:08:28 AM UTC 24
Peak memory	216160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850742630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1850742630
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/49.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_aes.2426434944
Short name	T918
Test name
Test status
Simulation time	4945105319 ps
CPU time	52.67 seconds
Started	Sep 11 06:08:26 AM UTC 24
Finished	Sep 11 06:09:20 AM UTC 24
Peak memory	217936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426434944 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2426434944
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/49.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_kmac.2992115223
Short name	T905
Test name
Test status
Simulation time	343608027 ps
CPU time	3.57 seconds
Started	Sep 11 06:08:25 AM UTC 24
Finished	Sep 11 06:08:29 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992115223 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2992115223
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/49.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_otbn.3459244170
Short name	T912
Test name
Test status
Simulation time	903138700 ps
CPU time	12.2 seconds
Started	Sep 11 06:08:26 AM UTC 24
Finished	Sep 11 06:08:39 AM UTC 24
Peak memory	215900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459244170 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3459244170
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/49.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_protect.538667743
Short name	T913
Test name
Test status
Simulation time	119604157 ps
CPU time	2.44 seconds
Started	Sep 11 06:08:36 AM UTC 24
Finished	Sep 11 06:08:40 AM UTC 24
Peak memory	217948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538667743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.538667743
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/49.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/49.keymgr_smoke.40436832
Short name	T902
Test name
Test status
Simulation time	28003217 ps
CPU time	1.98 seconds
Started	Sep 11 06:08:23 AM UTC 24
Finished	Sep 11 06:08:26 AM UTC 24
Peak memory	217744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40436832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.40436832
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/49.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all.3892044768
Short name	T347
Test name
Test status
Simulation time	1281629259 ps
CPU time	27.14 seconds
Started	Sep 11 06:08:37 AM UTC 24
Finished	Sep 11 06:09:06 AM UTC 24
Peak memory	231320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892044768 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3892044768
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/49.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/49.keymgr_sw_invalid_input.3063998719
Short name	T910
Test name
Test status
Simulation time	100441455 ps
CPU time	5.57 seconds
Started	Sep 11 06:08:30 AM UTC 24
Finished	Sep 11 06:08:37 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063998719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3063998719
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/49.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/49.keymgr_sync_async_fault_cross.4252435906
Short name	T915
Test name
Test status
Simulation time	44481523 ps
CPU time	2.62 seconds
Started	Sep 11 06:08:37 AM UTC 24
Finished	Sep 11 06:08:41 AM UTC 24
Peak memory	217884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252435906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.4252435906
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/49.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/5.keymgr_alert_test.993601127
Short name	T446
Test name
Test status
Simulation time	10543982 ps
CPU time	0.9 seconds
Started	Sep 11 05:52:26 AM UTC 24
Finished	Sep 11 05:52:28 AM UTC 24
Peak memory	213588 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993601127 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.993601127
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/5.keymgr_custom_cm.1090095083
Short name	T26
Test name
Test status
Simulation time	112374014 ps
CPU time	5.36 seconds
Started	Sep 11 05:52:17 AM UTC 24
Finished	Sep 11 05:52:24 AM UTC 24
Peak memory	218212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090095083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1090095083
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_custom_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/5.keymgr_direct_to_disabled.50980666
Short name	T153
Test name
Test status
Simulation time	276109564 ps
CPU time	3.39 seconds
Started	Sep 11 05:52:07 AM UTC 24
Finished	Sep 11 05:52:11 AM UTC 24
Peak memory	218272 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50980666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.50980666
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/5.keymgr_hwsw_invalid_input.2494013065
Short name	T50
Test name
Test status
Simulation time	84857511 ps
CPU time	2 seconds
Started	Sep 11 05:52:12 AM UTC 24
Finished	Sep 11 05:52:15 AM UTC 24
Peak memory	224344 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494013065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2494013065
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/5.keymgr_kmac_rsp_err.3319588872
Short name	T358
Test name
Test status
Simulation time	525313801 ps
CPU time	4.61 seconds
Started	Sep 11 05:52:16 AM UTC 24
Finished	Sep 11 05:52:22 AM UTC 24
Peak memory	224004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319588872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3319588872
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/5.keymgr_lc_disable.2832593440
Short name	T139
Test name
Test status
Simulation time	111934676 ps
CPU time	2.65 seconds
Started	Sep 11 05:52:08 AM UTC 24
Finished	Sep 11 05:52:12 AM UTC 24
Peak memory	217888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832593440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2832593440
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/5.keymgr_random.4260151815
Short name	T298
Test name
Test status
Simulation time	2275996457 ps
CPU time	28.93 seconds
Started	Sep 11 05:52:04 AM UTC 24
Finished	Sep 11 05:52:34 AM UTC 24
Peak memory	217944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260151815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.4260151815
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/5.keymgr_sideload.2003555466
Short name	T192
Test name
Test status
Simulation time	109470682 ps
CPU time	2.68 seconds
Started	Sep 11 05:52:01 AM UTC 24
Finished	Sep 11 05:52:04 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003555466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2003555466
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_aes.3417805386
Short name	T194
Test name
Test status
Simulation time	119705819 ps
CPU time	5.34 seconds
Started	Sep 11 05:52:01 AM UTC 24
Finished	Sep 11 05:52:07 AM UTC 24
Peak memory	217680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417805386 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3417805386
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_kmac.3020453073
Short name	T252
Test name
Test status
Simulation time	4817908440 ps
CPU time	31.21 seconds
Started	Sep 11 05:52:01 AM UTC 24
Finished	Sep 11 05:52:33 AM UTC 24
Peak memory	215712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020453073 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3020453073
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_otbn.2484834112
Short name	T193
Test name
Test status
Simulation time	54032643 ps
CPU time	2.79 seconds
Started	Sep 11 05:52:02 AM UTC 24
Finished	Sep 11 05:52:06 AM UTC 24
Peak memory	215864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484834112 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2484834112
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_protect.1501937890
Short name	T422
Test name
Test status
Simulation time	182770996 ps
CPU time	3.22 seconds
Started	Sep 11 05:52:20 AM UTC 24
Finished	Sep 11 05:52:25 AM UTC 24
Peak memory	224256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501937890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1501937890
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/5.keymgr_smoke.1645988850
Short name	T445
Test name
Test status
Simulation time	1715157948 ps
CPU time	20.99 seconds
Started	Sep 11 05:51:58 AM UTC 24
Finished	Sep 11 05:52:20 AM UTC 24
Peak memory	216096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645988850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1645988850
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/5.keymgr_sw_invalid_input.1549109453
Short name	T253
Test name
Test status
Simulation time	187273791 ps
CPU time	3.54 seconds
Started	Sep 11 05:52:12 AM UTC 24
Finished	Sep 11 05:52:17 AM UTC 24
Peak memory	228288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549109453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1549109453
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/5.keymgr_sync_async_fault_cross.1271938232
Short name	T93
Test name
Test status
Simulation time	140891583 ps
CPU time	3.36 seconds
Started	Sep 11 05:52:21 AM UTC 24
Finished	Sep 11 05:52:26 AM UTC 24
Peak memory	220020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271938232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1271938232
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/5.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/6.keymgr_alert_test.116991242
Short name	T447
Test name
Test status
Simulation time	35799510 ps
CPU time	0.95 seconds
Started	Sep 11 05:52:53 AM UTC 24
Finished	Sep 11 05:52:55 AM UTC 24
Peak memory	213584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116991242 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.116991242
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/6.keymgr_cfg_regwen.146955568
Short name	T244
Test name
Test status
Simulation time	552487695 ps
CPU time	8.6 seconds
Started	Sep 11 05:52:35 AM UTC 24
Finished	Sep 11 05:52:45 AM UTC 24
Peak memory	226140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146955568 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.146955568
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/6.keymgr_direct_to_disabled.1909470325
Short name	T302
Test name
Test status
Simulation time	483203762 ps
CPU time	5.19 seconds
Started	Sep 11 05:52:36 AM UTC 24
Finished	Sep 11 05:52:42 AM UTC 24
Peak memory	228300 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909470325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1909470325
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/6.keymgr_kmac_rsp_err.3796488927
Short name	T336
Test name
Test status
Simulation time	80010953 ps
CPU time	2.96 seconds
Started	Sep 11 05:52:43 AM UTC 24
Finished	Sep 11 05:52:48 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796488927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3796488927
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/6.keymgr_lc_disable.836624440
Short name	T135
Test name
Test status
Simulation time	557862403 ps
CPU time	4.61 seconds
Started	Sep 11 05:52:40 AM UTC 24
Finished	Sep 11 05:52:46 AM UTC 24
Peak memory	218052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836624440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.836624440
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/6.keymgr_random.295175143
Short name	T372
Test name
Test status
Simulation time	1309073075 ps
CPU time	4.97 seconds
Started	Sep 11 05:52:35 AM UTC 24
Finished	Sep 11 05:52:41 AM UTC 24
Peak memory	215832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295175143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.295175143
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/6.keymgr_sideload.1338024829
Short name	T331
Test name
Test status
Simulation time	243632478 ps
CPU time	4.72 seconds
Started	Sep 11 05:52:29 AM UTC 24
Finished	Sep 11 05:52:35 AM UTC 24
Peak memory	215832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338024829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1338024829
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_aes.4103066346
Short name	T409
Test name
Test status
Simulation time	599003800 ps
CPU time	5.39 seconds
Started	Sep 11 05:52:33 AM UTC 24
Finished	Sep 11 05:52:39 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103066346 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.4103066346
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_kmac.2273490849
Short name	T401
Test name
Test status
Simulation time	90411195 ps
CPU time	3.75 seconds
Started	Sep 11 05:52:31 AM UTC 24
Finished	Sep 11 05:52:36 AM UTC 24
Peak memory	216152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273490849 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2273490849
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_otbn.3625515405
Short name	T278
Test name
Test status
Simulation time	194085620 ps
CPU time	6.73 seconds
Started	Sep 11 05:52:34 AM UTC 24
Finished	Sep 11 05:52:42 AM UTC 24
Peak memory	218200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625515405 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3625515405
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_protect.3654862533
Short name	T423
Test name
Test status
Simulation time	565656769 ps
CPU time	5.39 seconds
Started	Sep 11 05:52:46 AM UTC 24
Finished	Sep 11 05:52:53 AM UTC 24
Peak memory	230580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654862533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3654862533
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/6.keymgr_smoke.3123621883
Short name	T407
Test name
Test status
Simulation time	37875895 ps
CPU time	1.99 seconds
Started	Sep 11 05:52:27 AM UTC 24
Finished	Sep 11 05:52:30 AM UTC 24
Peak memory	215704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123621883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3123621883
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all.1398329655
Short name	T147
Test name
Test status
Simulation time	2215905041 ps
CPU time	26.01 seconds
Started	Sep 11 05:52:49 AM UTC 24
Finished	Sep 11 05:53:16 AM UTC 24
Peak memory	231900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398329655 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1398329655
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all_with_rand_reset.243742471
Short name	T94
Test name
Test status
Simulation time	146681285 ps
CPU time	6.65 seconds
Started	Sep 11 05:52:49 AM UTC 24
Finished	Sep 11 05:52:56 AM UTC 24
Peak memory	232636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=243742471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_ stress_all_with_rand_reset.243742471
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/6.keymgr_sw_invalid_input.1605197341
Short name	T246
Test name
Test status
Simulation time	1374166547 ps
CPU time	22.66 seconds
Started	Sep 11 05:52:42 AM UTC 24
Finished	Sep 11 05:53:07 AM UTC 24
Peak memory	217876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605197341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1605197341
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/6.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/7.keymgr_alert_test.159433439
Short name	T450
Test name
Test status
Simulation time	36252436 ps
CPU time	1.06 seconds
Started	Sep 11 05:53:17 AM UTC 24
Finished	Sep 11 05:53:19 AM UTC 24
Peak memory	213588 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159433439 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.159433439
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/7.keymgr_cfg_regwen.1642291599
Short name	T245
Test name
Test status
Simulation time	1375474766 ps
CPU time	72.77 seconds
Started	Sep 11 05:53:02 AM UTC 24
Finished	Sep 11 05:54:17 AM UTC 24
Peak memory	226068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642291599 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1642291599
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/7.keymgr_direct_to_disabled.1404610087
Short name	T404
Test name
Test status
Simulation time	40447998 ps
CPU time	2.06 seconds
Started	Sep 11 05:53:03 AM UTC 24
Finished	Sep 11 05:53:06 AM UTC 24
Peak memory	215920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404610087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1404610087
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/7.keymgr_hwsw_invalid_input.172989804
Short name	T307
Test name
Test status
Simulation time	76186659 ps
CPU time	3.14 seconds
Started	Sep 11 05:53:08 AM UTC 24
Finished	Sep 11 05:53:12 AM UTC 24
Peak memory	224132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172989804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.172989804
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/7.keymgr_kmac_rsp_err.4261824504
Short name	T145
Test name
Test status
Simulation time	553848585 ps
CPU time	4.87 seconds
Started	Sep 11 05:53:08 AM UTC 24
Finished	Sep 11 05:53:14 AM UTC 24
Peak memory	223968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261824504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.4261824504
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/7.keymgr_lc_disable.4066077362
Short name	T216
Test name
Test status
Simulation time	167238695 ps
CPU time	3.92 seconds
Started	Sep 11 05:53:07 AM UTC 24
Finished	Sep 11 05:53:12 AM UTC 24
Peak memory	224032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066077362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.4066077362
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/7.keymgr_random.3861415608
Short name	T394
Test name
Test status
Simulation time	713185617 ps
CPU time	4.96 seconds
Started	Sep 11 05:53:01 AM UTC 24
Finished	Sep 11 05:53:07 AM UTC 24
Peak memory	228532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861415608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3861415608
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/7.keymgr_sideload.4172234445
Short name	T370
Test name
Test status
Simulation time	249658520 ps
CPU time	5.3 seconds
Started	Sep 11 05:52:54 AM UTC 24
Finished	Sep 11 05:53:00 AM UTC 24
Peak memory	217872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172234445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.4172234445
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_aes.2327309809
Short name	T449
Test name
Test status
Simulation time	412734310 ps
CPU time	4.36 seconds
Started	Sep 11 05:52:57 AM UTC 24
Finished	Sep 11 05:53:02 AM UTC 24
Peak memory	218296 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327309809 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2327309809
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_kmac.253155735
Short name	T364
Test name
Test status
Simulation time	235117411 ps
CPU time	3.75 seconds
Started	Sep 11 05:52:56 AM UTC 24
Finished	Sep 11 05:53:01 AM UTC 24
Peak memory	215832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253155735 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.253155735
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_otbn.3785258895
Short name	T295
Test name
Test status
Simulation time	3780400724 ps
CPU time	7.7 seconds
Started	Sep 11 05:52:58 AM UTC 24
Finished	Sep 11 05:53:07 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785258895 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3785258895
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_protect.3890836606
Short name	T428
Test name
Test status
Simulation time	91894324 ps
CPU time	1.53 seconds
Started	Sep 11 05:53:13 AM UTC 24
Finished	Sep 11 05:53:16 AM UTC 24
Peak memory	214144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890836606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3890836606
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/7.keymgr_smoke.1380264803
Short name	T448
Test name
Test status
Simulation time	33026386 ps
CPU time	2.66 seconds
Started	Sep 11 05:52:54 AM UTC 24
Finished	Sep 11 05:52:57 AM UTC 24
Peak memory	217984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380264803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1380264803
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/7.keymgr_sw_invalid_input.3942186702
Short name	T285
Test name
Test status
Simulation time	46842497 ps
CPU time	3.13 seconds
Started	Sep 11 05:53:07 AM UTC 24
Finished	Sep 11 05:53:11 AM UTC 24
Peak memory	216248 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942186702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3942186702
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/7.keymgr_sync_async_fault_cross.1075501633
Short name	T102
Test name
Test status
Simulation time	168177451 ps
CPU time	2.45 seconds
Started	Sep 11 05:53:14 AM UTC 24
Finished	Sep 11 05:53:17 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075501633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1075501633
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/7.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/8.keymgr_alert_test.1028944091
Short name	T453
Test name
Test status
Simulation time	13373646 ps
CPU time	1 seconds
Started	Sep 11 05:53:46 AM UTC 24
Finished	Sep 11 05:53:48 AM UTC 24
Peak memory	213600 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028944091 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1028944091
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/8.keymgr_cfg_regwen.1662457308
Short name	T112
Test name
Test status
Simulation time	36612610 ps
CPU time	3.51 seconds
Started	Sep 11 05:53:27 AM UTC 24
Finished	Sep 11 05:53:32 AM UTC 24
Peak memory	224020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662457308 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1662457308
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/8.keymgr_direct_to_disabled.3466341804
Short name	T429
Test name
Test status
Simulation time	222594037 ps
CPU time	2.48 seconds
Started	Sep 11 05:53:28 AM UTC 24
Finished	Sep 11 05:53:32 AM UTC 24
Peak memory	217872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466341804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3466341804
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/8.keymgr_hwsw_invalid_input.1037867512
Short name	T22
Test name
Test status
Simulation time	135728116 ps
CPU time	5.98 seconds
Started	Sep 11 05:53:34 AM UTC 24
Finished	Sep 11 05:53:41 AM UTC 24
Peak memory	217948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037867512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1037867512
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/8.keymgr_kmac_rsp_err.1922696308
Short name	T148
Test name
Test status
Simulation time	282738671 ps
CPU time	4.54 seconds
Started	Sep 11 05:53:37 AM UTC 24
Finished	Sep 11 05:53:43 AM UTC 24
Peak memory	232192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922696308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1922696308
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/8.keymgr_lc_disable.1212673257
Short name	T143
Test name
Test status
Simulation time	336175289 ps
CPU time	3.56 seconds
Started	Sep 11 05:53:32 AM UTC 24
Finished	Sep 11 05:53:37 AM UTC 24
Peak memory	219872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212673257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1212673257
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/8.keymgr_random.465029330
Short name	T387
Test name
Test status
Simulation time	486562273 ps
CPU time	8.19 seconds
Started	Sep 11 05:53:27 AM UTC 24
Finished	Sep 11 05:53:36 AM UTC 24
Peak memory	218020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465029330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.465029330
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/8.keymgr_sideload.3202067123
Short name	T452
Test name
Test status
Simulation time	234783920 ps
CPU time	3.07 seconds
Started	Sep 11 05:53:18 AM UTC 24
Finished	Sep 11 05:53:22 AM UTC 24
Peak memory	217876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202067123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3202067123
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_kmac.1392477337
Short name	T340
Test name
Test status
Simulation time	196563164 ps
CPU time	6.47 seconds
Started	Sep 11 05:53:20 AM UTC 24
Finished	Sep 11 05:53:27 AM UTC 24
Peak memory	217948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392477337 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1392477337
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_otbn.1349435815
Short name	T327
Test name
Test status
Simulation time	41496314 ps
CPU time	2.09 seconds
Started	Sep 11 05:53:23 AM UTC 24
Finished	Sep 11 05:53:26 AM UTC 24
Peak memory	215900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349435815 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1349435815
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_protect.3394081924
Short name	T424
Test name
Test status
Simulation time	69349467 ps
CPU time	4.04 seconds
Started	Sep 11 05:53:39 AM UTC 24
Finished	Sep 11 05:53:45 AM UTC 24
Peak memory	218012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394081924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3394081924
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/8.keymgr_smoke.1792913862
Short name	T451
Test name
Test status
Simulation time	71397324 ps
CPU time	1.79 seconds
Started	Sep 11 05:53:18 AM UTC 24
Finished	Sep 11 05:53:21 AM UTC 24
Peak memory	215612 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792913862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1792913862
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all.218911310
Short name	T281
Test name
Test status
Simulation time	125022435 ps
CPU time	4.29 seconds
Started	Sep 11 05:53:43 AM UTC 24
Finished	Sep 11 05:53:48 AM UTC 24
Peak memory	216156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218911310 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.218911310
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all_with_rand_reset.3334865186
Short name	T95
Test name
Test status
Simulation time	398999287 ps
CPU time	9.47 seconds
Started	Sep 11 05:53:44 AM UTC 24
Finished	Sep 11 05:53:54 AM UTC 24
Peak memory	228316 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3334865186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr _stress_all_with_rand_reset.3334865186
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/8.keymgr_sw_invalid_input.2058774182
Short name	T408
Test name
Test status
Simulation time	158341444 ps
CPU time	5.67 seconds
Started	Sep 11 05:53:32 AM UTC 24
Finished	Sep 11 05:53:39 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058774182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2058774182
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/8.keymgr_sync_async_fault_cross.72550703
Short name	T138
Test name
Test status
Simulation time	3943660253 ps
CPU time	20.5 seconds
Started	Sep 11 05:53:43 AM UTC 24
Finished	Sep 11 05:54:04 AM UTC 24
Peak memory	220068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72550703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.72550703
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/8.keymgr_sync_async_fault_cross/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/9.keymgr_alert_test.2691384405
Short name	T456
Test name
Test status
Simulation time	13606736 ps
CPU time	1.1 seconds
Started	Sep 11 05:54:18 AM UTC 24
Finished	Sep 11 05:54:20 AM UTC 24
Peak memory	213712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691384405 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2691384405
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/9.keymgr_cfg_regwen.3551906928
Short name	T113
Test name
Test status
Simulation time	60261537 ps
CPU time	4.66 seconds
Started	Sep 11 05:54:02 AM UTC 24
Finished	Sep 11 05:54:08 AM UTC 24
Peak memory	226124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551906928 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3551906928
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_cfg_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/9.keymgr_direct_to_disabled.280864327
Short name	T455
Test name
Test status
Simulation time	125850872 ps
CPU time	3.62 seconds
Started	Sep 11 05:54:02 AM UTC 24
Finished	Sep 11 05:54:07 AM UTC 24
Peak memory	228444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280864327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.280864327
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_direct_to_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/9.keymgr_hwsw_invalid_input.3633724754
Short name	T273
Test name
Test status
Simulation time	100473375 ps
CPU time	5.27 seconds
Started	Sep 11 05:54:08 AM UTC 24
Finished	Sep 11 05:54:15 AM UTC 24
Peak memory	226432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633724754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3633724754
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_hwsw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/9.keymgr_kmac_rsp_err.15019435
Short name	T146
Test name
Test status
Simulation time	109105990 ps
CPU time	5.59 seconds
Started	Sep 11 05:54:10 AM UTC 24
Finished	Sep 11 05:54:16 AM UTC 24
Peak memory	232516 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15019435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.15019435
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_kmac_rsp_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/9.keymgr_lc_disable.1730525840
Short name	T226
Test name
Test status
Simulation time	292809288 ps
CPU time	4 seconds
Started	Sep 11 05:54:05 AM UTC 24
Finished	Sep 11 05:54:10 AM UTC 24
Peak memory	217880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730525840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1730525840
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_lc_disable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/9.keymgr_random.1547977926
Short name	T371
Test name
Test status
Simulation time	933524718 ps
CPU time	6.74 seconds
Started	Sep 11 05:54:01 AM UTC 24
Finished	Sep 11 05:54:09 AM UTC 24
Peak memory	218272 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547977926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1547977926
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/9.keymgr_sideload.1596555900
Short name	T350
Test name
Test status
Simulation time	6335906616 ps
CPU time	68.52 seconds
Started	Sep 11 05:53:49 AM UTC 24
Finished	Sep 11 05:54:59 AM UTC 24
Peak memory	218268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596555900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1596555900
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_aes.2881730117
Short name	T365
Test name
Test status
Simulation time	92786777 ps
CPU time	3.93 seconds
Started	Sep 11 05:53:55 AM UTC 24
Finished	Sep 11 05:54:00 AM UTC 24
Peak memory	217944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881730117 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2881730117
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_sideload_aes/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_kmac.2928862410
Short name	T410
Test name
Test status
Simulation time	162351041 ps
CPU time	3.72 seconds
Started	Sep 11 05:53:53 AM UTC 24
Finished	Sep 11 05:53:58 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928862410 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2928862410
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_sideload_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_otbn.3553664703
Short name	T414
Test name
Test status
Simulation time	21920916 ps
CPU time	2.14 seconds
Started	Sep 11 05:53:58 AM UTC 24
Finished	Sep 11 05:54:01 AM UTC 24
Peak memory	215996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553664703 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3553664703
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_sideload_otbn/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_protect.2722757444
Short name	T457
Test name
Test status
Simulation time	1026977211 ps
CPU time	6.43 seconds
Started	Sep 11 05:54:13 AM UTC 24
Finished	Sep 11 05:54:20 AM UTC 24
Peak memory	218016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722757444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2722757444
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_sideload_protect/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/9.keymgr_smoke.587295699
Short name	T454
Test name
Test status
Simulation time	89724373 ps
CPU time	1.94 seconds
Started	Sep 11 05:53:49 AM UTC 24
Finished	Sep 11 05:53:52 AM UTC 24
Peak memory	214172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587295699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.587295699
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all.1472419025
Short name	T223
Test name
Test status
Simulation time	4300850165 ps
CPU time	114.77 seconds
Started	Sep 11 05:54:17 AM UTC 24
Finished	Sep 11 05:56:14 AM UTC 24
Peak memory	228512 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472419025 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1472419025
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/9.keymgr_sw_invalid_input.4007895196
Short name	T425
Test name
Test status
Simulation time	357995110 ps
CPU time	2.88 seconds
Started	Sep 11 05:54:07 AM UTC 24
Finished	Sep 11 05:54:11 AM UTC 24
Peak memory	216152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007895196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.4007895196
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_sw_invalid_input/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/coverage/default/9.keymgr_sync_async_fault_cross.2715162014
Short name	T201
Test name
Test status
Simulation time	108742703 ps
CPU time	4.24 seconds
Started	Sep 11 05:54:16 AM UTC 24
Finished	Sep 11 05:54:21 AM UTC 24
Peak memory	218304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715162014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2715162014
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/9.keymgr_sync_async_fault_cross/latest