SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 12 | 2 | 10 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
fault_cp | 12 | 2 | 10 | 83.33 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 12 | 2 | 10 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
auto[FaultKmacOp] | 0 | 1 | 1 | |
auto[FaultKmacOut] | 0 | 1 | 1 |
NAME | COUNT | STATUS |
auto[FaultRegIntg] | 0 | Excluded |
auto[FaultShadow] | 0 | Excluded |
auto[FaultLastPos] | 0 | Illegal |
illegal | 0 | Illegal |
ignore | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[FaultKmacCmd] | 16 | 1 | T19 | 1 | T21 | 1 | T23 | 1 | ||||
auto[FaultKmacFsm] | 140 | 1 | T10 | 40 | T11 | 20 | T12 | 20 | ||||
auto[FaultKmacDone] | 8 | 1 | T30 | 1 | T31 | 1 | T32 | 1 | ||||
auto[FaultCtrlFsm] | 210 | 1 | T10 | 60 | T11 | 30 | T12 | 30 | ||||
auto[FaultCtrlFsmChk] | 8 | 1 | T22 | 1 | T24 | 1 | T397 | 1 | ||||
auto[FaultCtrlCnt] | 70 | 1 | T10 | 20 | T11 | 10 | T12 | 10 | ||||
auto[FaultReseedCnt] | 70 | 1 | T10 | 20 | T11 | 10 | T12 | 10 | ||||
auto[FaultSideFsm] | 70 | 1 | T10 | 20 | T11 | 10 | T12 | 10 | ||||
auto[FaultSideSel] | 9 | 1 | T37 | 1 | T38 | 1 | T39 | 1 | ||||
auto[FaultKeyEcc] | 9 | 1 | T68 | 1 | T186 | 1 | T187 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |