Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
71.43	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

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Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	17	32	65.31

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	16	19	54.29	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	52	1			T101	1		T22	1		T102	1
auto[OpGenId]	12	1			T14	1		T93	1		T135	1
auto[OpGenSwOut]	8	1			T7	1		T169	1		T229	1
auto[OpGenHwOut]	22	1			T5	1		T6	1		T24	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1619	1			T28	1		T10	180		T230	1
auto[StInit]	87	1			T14	1		T40	1		T22	1
auto[StCreatorRootKey]	57	1			T19	1		T37	1		T28	1
auto[StOwnerIntKey]	41	1			T35	1		T93	1		T21	1
auto[StOwnerKey]	37	1			T66	1		T38	1		T135	1
auto[StDisabled]	449	1			T28	3		T101	1		T45	3
auto[StInvalid]	50	1			T2	1		T20	1		T36	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3331

1

T1

1

T2

2

T3

1

auto[1]

94

1

T14

1

T93

1

T101

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1614	1			T28	1		T10	180		T230	1
auto[StReset]	auto[1]	5	1			T103	1		T231	1		T136	1
auto[StInit]	auto[0]	41	1			T40	1		T103	1		T48	2
auto[StInit]	auto[1]	46	1			T14	1		T22	1		T68	1
auto[StCreatorRootKey]	auto[0]	41	1			T19	1		T37	1		T28	1
auto[StCreatorRootKey]	auto[1]	16	1			T102	1		T48	1		T7	1
auto[StOwnerIntKey]	auto[0]	33	1			T35	1		T21	1		T46	1
auto[StOwnerIntKey]	auto[1]	8	1			T93	1		T7	1		T231	1
auto[StOwnerKey]	auto[0]	27	1			T66	1		T38	1		T49	1
auto[StOwnerKey]	auto[1]	10	1			T135	1		T136	1		T232	1
auto[StDisabled]	auto[0]	440	1			T28	3		T45	3		T46	3
auto[StDisabled]	auto[1]	9	1			T101	1		T79	1		T233	1
auto[StInvalid]	auto[0]	50	1			T2	1		T20	1		T36	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	16	19	54.29	16

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[StOwnerIntKey]]	[auto[OpGenSwOut]]	0	1	1
[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpGenSwOut]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	5	1			T103	1		T231	1		T136	1
auto[StInit]	auto[OpAdvance]	25	1			T22	1		T68	1		T7	1
auto[StInit]	auto[OpGenId]	4	1			T14	1		T234	1		T235	1
auto[StInit]	auto[OpGenSwOut]	5	1			T7	1		T236	1		T237	1
auto[StInit]	auto[OpGenHwOut]	12	1			T5	1		T6	1		T24	1
auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T102	1		T48	1		T32	1
auto[StCreatorRootKey]	auto[OpGenId]	2	1			T78	1		T191	1		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	1	1			T169	1		-	-		-	-
auto[StCreatorRootKey]	auto[OpGenHwOut]	5	1			T7	1		T238	1		T149	1
auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T7	1		T231	1		T239	1
auto[StOwnerIntKey]	auto[OpGenId]	2	1			T93	1		T240	1		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	2	1			T209	1		T241	1		-	-
auto[StOwnerKey]	auto[OpAdvance]	4	1			T242	1		T243	1		T244	1
auto[StOwnerKey]	auto[OpGenId]	3	1			T135	1		T136	1		T232	1
auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T229	1		T245	1		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T246	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	6	1			T101	1		T233	1		T247	1
auto[StDisabled]	auto[OpGenId]	1	1			T248	1		-	-		-	-
auto[StDisabled]	auto[OpGenHwOut]	2	1			T79	1		T249	1		-	-