Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4746

1

T1

2

T2

4

T3

4

auto[1]

584

1

T16

3

T18

4

T44

4

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4746

1

T1

2

T2

4

T3

4

auto[1]

584

1

T16

3

T18

4

T44

4

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4809

1

T1

2

T2

4

T3

2

auto[1]

521

1

T3

2

T13

2

T18

2

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4809

1

T1

2

T2

4

T3

2

auto[1]

521

1

T3

2

T13

2

T18

2

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	440	1			T2	1		T4	3		T18	1
auto[OpGenId]	1064	1			T14	1		T18	1		T120	1
auto[OpGenSwOut]	1182	1			T2	2		T3	3		T4	3
auto[OpGenHwOut]	2581	1			T1	1		T2	1		T3	1
auto[OpDisable]	63	1			T1	1		T127	1		T139	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	440	1			T2	1		T4	3		T18	1
auto[OpGenId]	1064	1			T14	1		T18	1		T120	1
auto[OpGenSwOut]	1182	1			T2	2		T3	3		T4	3
auto[OpGenHwOut]	2581	1			T1	1		T2	1		T3	1
auto[OpDisable]	63	1			T1	1		T127	1		T139	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4777

1

T1

2

T2

4

T3

4

auto[1]

553

1

T4

1

T120

1

T95

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4777

1

T1

2

T2

4

T3

4

auto[1]

553

1

T4

1

T120

1

T95

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5076

1

T1

2

T2

4

T3

4

auto[1]

254

1

T60

2

T100

1

T64

9

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1750	1			T1	1		T2	1		T3	2
auto[1]	718	1			T1	1		T4	1		T13	1
auto[2]	721	1			T3	2		T4	3		T13	1
auto[3]	700	1			T13	2		T16	2		T18	2
auto[4]	380	1			T2	2		T4	1		T13	1
auto[5]	374	1			T2	1		T13	2		T16	1
auto[6]	339	1			T13	1		T16	1		T44	1
auto[7]	348	1			T94	1		T95	1		T96	2

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1441	1			T2	3		T4	1		T13	4
clear_one[1]	718	1			T1	1		T4	1		T13	1
clear_one[2]	721	1			T3	2		T4	3		T13	1
clear_one[3]	700	1			T13	2		T16	2		T18	2
clear_none	1750	1			T1	1		T2	1		T3	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1044	1			T2	1		T13	1		T14	2
auto[StInit]	602	1			T1	1		T13	1		T16	1
auto[StCreatorRootKey]	573	1			T4	1		T13	1		T16	1
auto[StOwnerIntKey]	510	1			T13	1		T16	1		T18	1
auto[StOwnerKey]	473	1			T3	1		T4	1		T13	1
auto[StDisabled]	1825	1			T1	1		T3	3		T4	4
auto[StInvalid]	303	1			T2	3		T20	5		T94	5

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1044	1			T2	1		T13	1		T14	2
auto[StInit]	602	1			T1	1		T13	1		T16	1
auto[StCreatorRootKey]	573	1			T4	1		T13	1		T16	1
auto[StOwnerIntKey]	510	1			T13	1		T16	1		T18	1
auto[StOwnerKey]	473	1			T3	1		T4	1		T13	1
auto[StDisabled]	1825	1			T1	1		T3	3		T4	4
auto[StInvalid]	303	1			T2	3		T20	5		T94	5

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	10
[auto[0] - auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[2] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[2] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[2] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[2] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[4]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[4]]	[auto[StCreatorRootKey]]	[auto[OpGenSwOut]]	0	1	1
[auto[4]]	[auto[StCreatorRootKey]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	2
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[5] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[5] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	1	1			T250	1		-	-		-	-
auto[0]	auto[StReset]	auto[OpGenId]	137	1			T14	1		T37	1		T60	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	173	1			T19	1		T21	1		T217	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	267	1			T2	1		T13	1		T16	1
auto[0]	auto[StInit]	auto[OpAdvance]	30	1			T28	1		T59	1		T45	1
auto[0]	auto[StInit]	auto[OpGenId]	78	1			T120	1		T60	1		T103	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	88	1			T95	1		T54	1		T21	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	160	1			T1	1		T34	1		T44	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	22	1			T46	1		T70	1		T76	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	47	1			T56	1		T110	1		T45	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	54	1			T4	1		T100	2		T101	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	83	1			T216	1		T227	1		T65	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	15	1			T100	1		T251	1		T252	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	29	1			T18	1		T46	1		T139	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	35	1			T46	1		T223	1		T144	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	55	1			T221	1		T65	1		T73	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T205	1		T253	1		T254	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	17	1			T255	1		T136	1		T256	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	25	1			T3	1		T257	1		T258	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	34	1			T97	1		T124	1		T47	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	15	1			T59	1		T207	1		T7	1
auto[0]	auto[StDisabled]	auto[OpGenId]	53	1			T110	1		T122	1		T127	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	61	1			T221	1		T220	1		T70	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	167	1			T3	1		T16	1		T18	1
auto[0]	auto[StDisabled]	auto[OpDisable]	20	1			T103	1		T259	1		T51	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	4	1			T260	1		T261	1		T262	1
auto[0]	auto[StInvalid]	auto[OpGenId]	26	1			T20	1		T94	1		T119	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	24	1			T119	1		T107	1		T222	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	20	1			T69	1		T108	1		T263	1
auto[1]	auto[StReset]	auto[OpAdvance]	1	1			T264	1		-	-		-	-
auto[1]	auto[StReset]	auto[OpGenId]	29	1			T30	1		T202	1		T265	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	25	1			T14	1		T199	1		T266	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	63	1			T96	1		T226	2		T227	2
auto[1]	auto[StInit]	auto[OpAdvance]	4	1			T19	1		T80	1		T113	1
auto[1]	auto[StInit]	auto[OpGenId]	9	1			T121	1		T47	1		T267	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	13	1			T217	1		T268	2		T269	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	27	1			T227	1		T270	1		T268	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T64	1		T80	1		T271	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T7	1		T269	1		T136	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	16	1			T200	1		T48	1		T233	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	41	1			T44	1		T73	1		T272	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T200	1		T273	1		T274	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	18	1			T28	1		T140	1		T275	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T276	1		T52	1		T277	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	30	1			T13	1		T124	1		T103	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T72	1		T278	1		T274	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	11	1			T140	1		T76	1		T231	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T95	1		T279	1		T273	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T57	1		T73	1		T103	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	30	1			T46	1		T64	1		T207	1
auto[1]	auto[StDisabled]	auto[OpGenId]	70	1			T60	1		T64	4		T207	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	59	1			T4	1		T18	1		T218	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	131	1			T16	2		T124	1		T125	1
auto[1]	auto[StDisabled]	auto[OpDisable]	5	1			T1	1		T76	1		T280	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	7	1			T281	1		T282	1		T283	1
auto[1]	auto[StInvalid]	auto[OpGenId]	9	1			T206	1		T284	1		T285	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T94	3		T108	1		T286	2
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	15	1			T206	1		T287	1		T286	1
auto[2]	auto[StReset]	auto[OpGenId]	25	1			T64	1		T30	2		T288	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	13	1			T21	1		T106	1		T289	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	44	1			T96	1		T97	1		T60	1
auto[2]	auto[StInit]	auto[OpAdvance]	6	1			T64	1		T276	1		T290	1
auto[2]	auto[StInit]	auto[OpGenId]	9	1			T291	1		T292	1		T229	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	12	1			T289	1		T142	1		T167	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	26	1			T226	1		T30	1		T293	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T64	1		T51	1		T294	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T102	1		T295	1		T292	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T59	1		T123	1		T45	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	32	1			T13	1		T124	1		T127	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T25	1		T296	1		T297	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T45	1		T298	1		T299	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	21	1			T46	1		T105	1		T300	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	48	1			T16	1		T97	1		T125	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	14	1			T103	1		T105	1		T77	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	13	1			T221	1		T101	1		T200	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	19	1			T301	1		T7	1		T142	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	44	1			T302	1		T301	2		T268	4
auto[2]	auto[StDisabled]	auto[OpAdvance]	39	1			T4	3		T103	1		T207	1
auto[2]	auto[StDisabled]	auto[OpGenId]	56	1			T28	1		T60	1		T72	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	56	1			T3	2		T60	1		T202	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	136	1			T18	1		T95	1		T96	2
auto[2]	auto[StDisabled]	auto[OpDisable]	8	1			T127	1		T140	1		T303	2
auto[2]	auto[StInvalid]	auto[OpAdvance]	11	1			T107	1		T108	1		T206	1
auto[2]	auto[StInvalid]	auto[OpGenId]	9	1			T304	1		T305	1		T261	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T306	1		T261	1		T307	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	15	1			T20	1		T107	1		T108	1
auto[3]	auto[StReset]	auto[OpGenId]	15	1			T76	1		T308	1		T309	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	16	1			T310	1		T280	1		T311	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	51	1			T226	1		T227	1		T291	1
auto[3]	auto[StInit]	auto[OpAdvance]	7	1			T48	1		T26	1		T312	1
auto[3]	auto[StInit]	auto[OpGenId]	3	1			T313	1		T136	1		T149	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	8	1			T101	1		T314	1		T315	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	26	1			T13	1		T16	1		T96	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T72	1		T74	1		T316	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T231	1		T317	1		T318	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	21	1			T19	1		T95	1		T319	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	40	1			T16	1		T54	1		T226	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T74	1		T135	1		T82	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T101	1		T199	1		T207	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T7	1		T231	1		T320	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	37	1			T44	1		T96	1		T55	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T61	1		T50	1		T254	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	16	1			T202	1		T38	1		T291	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T18	1		T45	1		T49	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	47	1			T44	1		T55	1		T59	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	27	1			T18	1		T45	1		T295	1
auto[3]	auto[StDisabled]	auto[OpGenId]	39	1			T221	1		T110	1		T45	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	55	1			T123	1		T46	1		T47	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	157	1			T13	1		T44	2		T55	1
auto[3]	auto[StDisabled]	auto[OpDisable]	8	1			T139	1		T143	1		T321	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	8	1			T36	1		T322	1		T323	1
auto[3]	auto[StInvalid]	auto[OpGenId]	11	1			T20	1		T36	1		T106	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	17	1			T20	1		T119	1		T206	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T119	1		T263	1		T305	1
auto[4]	auto[StReset]	auto[OpAdvance]	1	1			T324	1		-	-		-	-
auto[4]	auto[StReset]	auto[OpGenId]	4	1			T106	1		T325	1		T326	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	9	1			T306	1		T327	1		T328	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	31	1			T16	1		T48	1		T329	1
auto[4]	auto[StInit]	auto[OpAdvance]	3	1			T292	1		T249	1		T330	1
auto[4]	auto[StInit]	auto[OpGenId]	5	1			T223	1		T273	1		T142	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	3	1			T267	1		T324	1		T331	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	9	1			T308	1		T111	1		T332	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T229	1		T333	1		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T334	1		T335	1		T229	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T96	1		T97	1		T121	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T336	1		T337	1		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T70	1		T338	1		T339	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T205	1		T334	1		T267	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T59	1		T340	1		T231	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T216	1		T105	1		T76	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	6	1			T136	1		T264	1		T168	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T4	1		T218	1		T341	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	26	1			T13	1		T71	1		T199	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	17	1			T28	1		T105	2		T7	1
auto[4]	auto[StDisabled]	auto[OpGenId]	36	1			T342	1		T298	1		T320	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	34	1			T48	1		T105	1		T7	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	82	1			T44	1		T97	1		T55	1
auto[4]	auto[StDisabled]	auto[OpDisable]	5	1			T231	1		T147	2		T343	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	3	1			T2	1		T36	1		T344	1
auto[4]	auto[StInvalid]	auto[OpGenId]	12	1			T107	1		T305	1		T306	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T2	1		T263	1		T283	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T284	1		T306	1		T261	1
auto[5]	auto[StReset]	auto[OpGenId]	9	1			T253	1		T113	1		T229	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	10	1			T60	1		T106	1		T140	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	26	1			T96	1		T125	1		T300	1
auto[5]	auto[StInit]	auto[OpAdvance]	5	1			T265	1		T292	1		T345	3
auto[5]	auto[StInit]	auto[OpGenId]	5	1			T140	1		T25	1		T136	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	2	1			T37	1		T76	1		-	-
auto[5]	auto[StInit]	auto[OpGenHwOut]	11	1			T64	2		T346	1		T318	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T38	1		T265	1		T268	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T30	1		T136	1		T27	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T50	1		T76	1		T320	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	28	1			T34	1		T201	1		T203	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T75	1		T231	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T216	1		T48	1		T347	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T289	1		T314	1		T348	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T270	1		T349	1		T142	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T75	1		T350	1		T351	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	5	1			T7	1		T352	1		T353	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T80	1		T231	1		T229	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	12	1			T265	1		T231	1		T354	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	10	1			T28	1		T46	1		T79	1
auto[5]	auto[StDisabled]	auto[OpGenId]	29	1			T54	1		T61	1		T121	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	33	1			T95	1		T293	1		T310	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	94	1			T13	2		T16	1		T57	1
auto[5]	auto[StDisabled]	auto[OpDisable]	7	1			T76	1		T355	1		T229	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	2	1			T306	1		T356	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	5	1			T69	1		T263	1		T327	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T2	1		T108	1		T357	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T263	1		T358	1		T359	1
auto[6]	auto[StReset]	auto[OpGenId]	9	1			T106	2		T48	1		T280	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	11	1			T123	1		T347	1		T360	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	22	1			T64	1		T316	1		T270	1
auto[6]	auto[StInit]	auto[OpAdvance]	1	1			T198	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenId]	6	1			T53	1		T361	1		T229	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	7	1			T49	1		T362	2		T363	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	13	1			T125	1		T48	1		T364	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T76	1		T347	1		T352	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T103	2		T142	1		T292	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	2	1			T140	1		T365	1		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	14	1			T57	1		T45	1		T366	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T76	1		T142	1		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T95	1		T229	1		T164	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T103	1		T79	1		T367	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T226	1		T201	1		T329	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T319	1		T246	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	4	1			T123	1		T76	1		T340	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T368	1		T367	1		T112	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T16	1		T366	1		T369	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	15	1			T45	1		T370	1		T276	1
auto[6]	auto[StDisabled]	auto[OpGenId]	31	1			T110	1		T291	1		T251	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T7	1		T77	2		T111	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	71	1			T13	1		T44	1		T96	2
auto[6]	auto[StDisabled]	auto[OpDisable]	5	1			T164	1		T371	1		T372	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T304	1		T373	1		T157	1
auto[6]	auto[StInvalid]	auto[OpGenId]	4	1			T222	1		T374	1		T375	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T284	1		T376	1		T377	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T20	1		T305	1		T306	1
auto[7]	auto[StReset]	auto[OpGenId]	12	1			T74	1		T378	1		T379	2
auto[7]	auto[StReset]	auto[OpGenSwOut]	12	1			T380	1		T268	1		T162	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	28	1			T96	1		T97	1		T106	1
auto[7]	auto[StInit]	auto[OpAdvance]	2	1			T381	1		T382	1		-	-
auto[7]	auto[StInit]	auto[OpGenId]	4	1			T26	1		T383	1		T384	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	5	1			T118	1		T114	1		T385	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	15	1			T124	1		T127	1		T45	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T60	1		T7	1		T266	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T207	1		T49	1		T111	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T231	1		T386	1		T156	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	15	1			T55	1		T387	1		T388	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T239	1		T389	1		T390	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	2	1			T7	1		T292	1		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T143	1		T50	1		T309	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T391	1		T203	1		T316	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T380	1		-	-		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	4	1			T266	1		T362	2		T392	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T313	1		T111	1		T312	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	15	1			T96	1		T226	1		T393	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	12	1			T296	1		T153	1		T162	1
auto[7]	auto[StDisabled]	auto[OpGenId]	20	1			T95	1		T394	1		T7	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T60	1		T123	1		T47	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	77	1			T55	1		T57	1		T226	1
auto[7]	auto[StDisabled]	auto[OpDisable]	5	1			T50	1		T81	1		T280	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	3	1			T262	1		T395	1		T396	1
auto[7]	auto[StInvalid]	auto[OpGenId]	6	1			T109	1		T281	1		T395	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T94	1		T287	1		T358	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T106	1		T287	1		T373	1