Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

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Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1441

1

T2

3

T4

1

T13

4

clear_one[1]

auto[0]

auto[0]

auto[0]

413

1

T1

1

T4

1

T14

1

clear_one[1]

auto[0]

auto[0]

auto[1]

143

1

T28

1

T124

2

T46

1

clear_one[1]

auto[0]

auto[1]

auto[0]

115

1

T13

1

T18

1

T125

1

clear_one[1]

auto[0]

auto[1]

auto[1]

47

1

T301

1

T52

1

T81

1

clear_one[2]

auto[0]

auto[0]

auto[0]

415

1

T3

2

T4

3

T13

1

clear_one[2]

auto[0]

auto[0]

auto[1]

119

1

T95

1

T96

2

T28

1

clear_one[2]

auto[1]

auto[0]

auto[0]

150

1

T16

1

T18

1

T57

1

clear_one[2]

auto[1]

auto[0]

auto[1]

37

1

T218

1

T103

1

T48

1

clear_one[3]

auto[0]

auto[0]

auto[0]

410

1

T13

1

T16

1

T20

2

clear_one[3]

auto[0]

auto[1]

auto[0]

120

1

T13

1

T19

1

T54

1

clear_one[3]

auto[1]

auto[0]

auto[0]

137

1

T16

1

T18

2

T44

4

clear_one[3]

auto[1]

auto[1]

auto[0]

33

1

T251

1

T49

1

T82

1

clear_none

auto[0]

auto[0]

auto[0]

1252

1

T1

1

T2

1

T13

1

clear_none

auto[0]

auto[0]

auto[1]

124

1

T4

1

T221

1

T124

1

clear_none

auto[0]

auto[1]

auto[0]

116

1

T3

2

T97

3

T55

1

clear_none

auto[0]

auto[1]

auto[1]

31

1

T122

1

T65

2

T103

1

clear_none

auto[1]

auto[0]

auto[0]

142

1

T16

1

T216

1

T100

2

clear_none

auto[1]

auto[0]

auto[1]

26

1

T110

1

T45

2

T75

2

clear_none

auto[1]

auto[1]

auto[0]

33

1

T18

1

T100

1

T103

1

clear_none

auto[1]

auto[1]

auto[1]

26

1

T120

1

T48

1

T207

2

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1357	1			T2	3		T4	1		T13	4
clear_all	auto[1]	84	1			T60	1		T64	1		T105	3
clear_one[1]	auto[0]	662	1			T1	1		T4	1		T13	1
clear_one[1]	auto[1]	56	1			T64	7		T268	2		T80	2
clear_one[2]	auto[0]	670	1			T3	2		T4	3		T13	1
clear_one[2]	auto[1]	51	1			T60	1		T64	1		T105	2
clear_one[3]	auto[0]	676	1			T13	2		T16	2		T18	2
clear_one[3]	auto[1]	24	1			T74	2		T265	3		T301	1
clear_none	auto[0]	1711	1			T1	1		T2	1		T3	2
clear_none	auto[1]	39	1			T100	1		T105	1		T74	3