Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10910

1

T1

1

T2

7

T3

11

auto[Attestation]

7444

1

T1

4

T3

9

T4

4

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2670	1			T1	1		T2	1		T3	7
auto[Aes]	3351	1			T1	1		T2	1		T3	2
auto[Kmac]	3304	1			T3	5		T4	2		T13	11
auto[Otbn]	3375	1			T1	2		T2	3		T3	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7545	1			T1	1		T2	1		T3	8
auto[OpGenId]	5654	1			T1	1		T2	2		T3	5
auto[OpGenSwOut]	5842	1			T1	2		T2	3		T3	8
auto[OpGenHwOut]	6858	1			T1	2		T2	2		T3	7
auto[OpDisable]	142	1			T1	1		T120	1		T56	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10363

1

T1

2

T2

1

T3

12

auto[OpDoneFail]

15678

1

T1

5

T2

7

T3

16

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6544	1			T1	1		T2	8		T3	1
auto[StInit]	3602	1			T1	2		T3	4		T4	1
auto[StCreatorRootKey]	3073	1			T3	1		T4	5		T13	2
auto[StOwnerIntKey]	2711	1			T3	5		T4	1		T13	2
auto[StOwnerKey]	2385	1			T3	4		T4	3		T13	2
auto[StDisabled]	7726	1			T1	4		T3	13		T4	6

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	338	1			T2	1		T14	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	98	1			T45	1		T134	1		T30	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	81	1			T45	1		T46	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	71	1			T216	1		T101	1		T103	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	70	1			T4	1		T18	1		T126	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	217	1			T3	2		T15	1		T120	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	390	1			T2	1		T18	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	76	1			T34	1		T36	1		T217	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	82	1			T4	1		T34	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	69	1			T138	1		T47	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	53	1			T3	1		T218	1		T219	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	211	1			T4	1		T100	2		T220	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	321	1			T19	1		T28	2		T217	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	112	1			T95	1		T221	1		T54	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	72	1			T4	1		T59	1		T101	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	79	1			T18	1		T28	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	67	1			T4	1		T98	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	206	1			T3	1		T221	1		T100	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	318	1			T2	1		T221	2		T28	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	114	1			T18	1		T120	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	74	1			T93	1		T45	1		T103	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	71	1			T3	1		T28	1		T103	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	65	1			T28	1		T45	1		T139	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	206	1			T1	1		T15	1		T95	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	95	1			T106	4		T222	1		T76	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	107	1			T21	1		T110	1		T216	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	94	1			T34	1		T120	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	65	1			T221	1		T46	1		T72	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	72	1			T95	1		T45	2		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	194	1			T1	1		T3	1		T58	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	68	1			T223	1		T7	1		T76	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	111	1			T127	1		T224	1		T47	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	74	1			T93	1		T100	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	74	1			T3	1		T35	1		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	56	1			T100	1		T47	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	192	1			T18	2		T98	1		T221	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	79	1			T106	2		T47	2		T223	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	97	1			T3	1		T60	1		T100	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	68	1			T98	1		T221	1		T28	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	62	1			T35	1		T218	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	60	1			T101	1		T218	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	186	1			T18	2		T28	1		T61	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	78	1			T47	2		T223	1		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	104	1			T35	1		T37	1		T217	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	81	1			T18	1		T95	1		T100	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	83	1			T110	1		T122	1		T46	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	48	1			T139	1		T49	1		T143	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	233	1			T18	1		T221	1		T28	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	271	1			T35	1		T19	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	75	1			T3	1		T20	1		T28	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	69	1			T37	1		T45	1		T103	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	51	1			T3	1		T121	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	40	1			T47	1		T207	1		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	161	1			T3	1		T120	1		T54	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	483	1			T16	7		T18	1		T120	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	111	1			T16	1		T34	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	108	1			T216	1		T225	3		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	101	1			T16	1		T120	1		T54	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	86	1			T44	1		T60	1		T65	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	285	1			T16	2		T18	1		T44	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	486	1			T13	3		T37	1		T97	8
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	111	1			T97	1		T55	1		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	105	1			T34	1		T19	1		T97	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	104	1			T3	1		T120	1		T55	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	97	1			T13	1		T28	1		T55	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	256	1			T13	3		T18	1		T28	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	491	1			T2	2		T14	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	126	1			T226	1		T227	1		T71	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	105	1			T34	2		T35	1		T96	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	98	1			T226	1		T124	1		T227	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	81	1			T96	1		T60	1		T227	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	276	1			T96	1		T28	1		T226	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	66	1			T106	1		T222	2		T51	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	84	1			T3	1		T35	1		T123	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	68	1			T19	2		T37	1		T100	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	52	1			T120	1		T221	1		T218	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	47	1			T101	1		T30	1		T200	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	184	1			T4	1		T18	1		T59	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	52	1			T222	1		T223	1		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	105	1			T34	1		T44	1		T221	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	115	1			T16	1		T44	1		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	91	1			T44	1		T59	1		T72	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	78	1			T16	1		T18	1		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	280	1			T1	1		T16	2		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	62	1			T106	1		T223	1		T76	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	109	1			T13	1		T93	1		T125	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	105	1			T13	1		T54	1		T55	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	97	1			T13	1		T97	1		T125	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	94	1			T3	1		T97	1		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	269	1			T3	1		T13	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	71	1			T222	1		T223	1		T76	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	103	1			T1	1		T34	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	109	1			T4	1		T34	1		T28	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	86	1			T96	1		T66	1		T71	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	86	1			T28	1		T59	1		T226	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	268	1			T120	1		T95	1		T96	3

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	207	1			T4	1		T18	1		T216	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	668	1			T2	1		T3	2		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	190	1			T3	1		T4	1		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	691	1			T2	1		T4	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	204	1			T4	2		T18	1		T98	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	653	1			T3	1		T19	1		T95	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	191	1			T3	1		T93	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	657	1			T1	1		T2	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	209	1			T34	1		T120	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	418	1			T1	1		T3	1		T58	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	186	1			T3	1		T35	1		T93	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	389	1			T18	2		T98	1		T221	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	175	1			T35	1		T98	1		T221	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	377	1			T3	1		T18	2		T28	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	197	1			T18	1		T95	1		T110	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	430	1			T18	1		T35	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	148	1			T3	1		T37	1		T121	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	519	1			T3	2		T35	1		T120	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	286	1			T16	1		T44	1		T120	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	888	1			T16	10		T18	2		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	289	1			T3	1		T13	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	870	1			T13	6		T18	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	268	1			T34	2		T35	1		T96	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	909	1			T2	2		T14	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	152	1			T120	1		T19	2		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	349	1			T3	1		T4	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	270	1			T16	2		T18	1		T44	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	451	1			T1	1		T16	2		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	276	1			T3	1		T13	2		T97	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	460	1			T3	1		T13	2		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	265	1			T4	1		T34	1		T96	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	458	1			T1	1		T34	1		T35	1