Unified Coverage Report :: Group Instance : attest_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32204

1

T1

7

T2

30

T3

30

auto[1]

257

1

T60

5

T100

5

T64

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32213	1			T1	7		T2	30		T3	30
auto[134217728:268435455]	11	1			T60	1		T64	1		T75	1
auto[268435456:402653183]	13	1			T60	1		T74	1		T80	1
auto[402653184:536870911]	4	1			T105	1		T80	1		T324	1
auto[536870912:671088639]	11	1			T105	2		T268	1		T77	3
auto[671088640:805306367]	6	1			T64	1		T74	1		T268	1
auto[805306368:939524095]	12	1			T60	1		T64	1		T74	1
auto[939524096:1073741823]	8	1			T74	1		T265	1		T264	1
auto[1073741824:1207959551]	7	1			T105	1		T74	1		T324	1
auto[1207959552:1342177279]	7	1			T64	1		T77	1		T250	1
auto[1342177280:1476395007]	13	1			T268	1		T80	1		T324	1
auto[1476395008:1610612735]	11	1			T74	2		T75	1		T409	1
auto[1610612736:1744830463]	6	1			T254	1		T351	1		T345	1
auto[1744830464:1879048191]	8	1			T105	1		T265	1		T268	1
auto[1879048192:2013265919]	8	1			T268	1		T300	1		T351	1
auto[2013265920:2147483647]	8	1			T312	1		T422	1		T250	1
auto[2147483648:2281701375]	6	1			T265	1		T409	1		T365	1
auto[2281701376:2415919103]	8	1			T100	1		T268	1		T274	1
auto[2415919104:2550136831]	8	1			T100	1		T64	1		T268	1
auto[2550136832:2684354559]	10	1			T105	3		T264	1		T412	1
auto[2684354560:2818572287]	15	1			T100	1		T74	1		T75	1
auto[2818572288:2952790015]	4	1			T324	1		T348	1		T423	1
auto[2952790016:3087007743]	5	1			T105	1		T422	1		T423	1
auto[3087007744:3221225471]	9	1			T60	1		T100	1		T105	1
auto[3221225472:3355443199]	4	1			T60	1		T324	1		T424	1
auto[3355443200:3489660927]	9	1			T265	2		T300	1		T324	1
auto[3489660928:3623878655]	4	1			T77	1		T254	2		T385	1
auto[3623878656:3758096383]	8	1			T64	1		T301	1		T422	1
auto[3758096384:3892314111]	2	1			T64	1		T423	1		-	-
auto[3892314112:4026531839]	9	1			T100	1		T74	1		T75	1
auto[4026531840:4160749567]	9	1			T105	1		T268	1		T80	1
auto[4160749568:4294967295]	5	1			T80	1		T264	1		T422	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32204	1			T1	7		T2	30		T3	30
auto[0:134217727]	auto[1]	9	1			T268	1		T77	1		T382	1
auto[134217728:268435455]	auto[1]	11	1			T60	1		T64	1		T75	1
auto[268435456:402653183]	auto[1]	13	1			T60	1		T74	1		T80	1
auto[402653184:536870911]	auto[1]	4	1			T105	1		T80	1		T324	1
auto[536870912:671088639]	auto[1]	11	1			T105	2		T268	1		T77	3
auto[671088640:805306367]	auto[1]	6	1			T64	1		T74	1		T268	1
auto[805306368:939524095]	auto[1]	12	1			T60	1		T64	1		T74	1
auto[939524096:1073741823]	auto[1]	8	1			T74	1		T265	1		T264	1
auto[1073741824:1207959551]	auto[1]	7	1			T105	1		T74	1		T324	1
auto[1207959552:1342177279]	auto[1]	7	1			T64	1		T77	1		T250	1
auto[1342177280:1476395007]	auto[1]	13	1			T268	1		T80	1		T324	1
auto[1476395008:1610612735]	auto[1]	11	1			T74	2		T75	1		T409	1
auto[1610612736:1744830463]	auto[1]	6	1			T254	1		T351	1		T345	1
auto[1744830464:1879048191]	auto[1]	8	1			T105	1		T265	1		T268	1
auto[1879048192:2013265919]	auto[1]	8	1			T268	1		T300	1		T351	1
auto[2013265920:2147483647]	auto[1]	8	1			T312	1		T422	1		T250	1
auto[2147483648:2281701375]	auto[1]	6	1			T265	1		T409	1		T365	1
auto[2281701376:2415919103]	auto[1]	8	1			T100	1		T268	1		T274	1
auto[2415919104:2550136831]	auto[1]	8	1			T100	1		T64	1		T268	1
auto[2550136832:2684354559]	auto[1]	10	1			T105	3		T264	1		T412	1
auto[2684354560:2818572287]	auto[1]	15	1			T100	1		T74	1		T75	1
auto[2818572288:2952790015]	auto[1]	4	1			T324	1		T348	1		T423	1
auto[2952790016:3087007743]	auto[1]	5	1			T105	1		T422	1		T423	1
auto[3087007744:3221225471]	auto[1]	9	1			T60	1		T100	1		T105	1
auto[3221225472:3355443199]	auto[1]	4	1			T60	1		T324	1		T424	1
auto[3355443200:3489660927]	auto[1]	9	1			T265	2		T300	1		T324	1
auto[3489660928:3623878655]	auto[1]	4	1			T77	1		T254	2		T385	1
auto[3623878656:3758096383]	auto[1]	8	1			T64	1		T301	1		T422	1
auto[3758096384:3892314111]	auto[1]	2	1			T64	1		T423	1		-	-
auto[3892314112:4026531839]	auto[1]	9	1			T100	1		T74	1		T75	1
auto[4026531840:4160749567]	auto[1]	9	1			T105	1		T268	1		T80	1
auto[4160749568:4294967295]	auto[1]	5	1			T80	1		T264	1		T422	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1583

1

T2

4

T4

1

T14

10

auto[1]

1758

1

T1

2

T2

3

T3

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	98	1			T1	1		T14	1		T221	1
auto[134217728:268435455]	107	1			T120	1		T221	1		T28	1
auto[268435456:402653183]	105	1			T93	1		T217	1		T110	1
auto[402653184:536870911]	113	1			T14	1		T18	1		T28	1
auto[536870912:671088639]	102	1			T28	1		T61	1		T45	1
auto[671088640:805306367]	104	1			T19	1		T103	1		T108	1
auto[805306368:939524095]	100	1			T221	1		T30	1		T103	2
auto[939524096:1073741823]	107	1			T18	1		T28	1		T217	1
auto[1073741824:1207959551]	88	1			T59	1		T36	1		T101	1
auto[1207959552:1342177279]	92	1			T94	1		T36	1		T107	1
auto[1342177280:1476395007]	104	1			T14	1		T20	1		T36	1
auto[1476395008:1610612735]	103	1			T18	1		T94	1		T36	1
auto[1610612736:1744830463]	107	1			T93	1		T21	1		T110	1
auto[1744830464:1879048191]	110	1			T2	1		T221	1		T60	1
auto[1879048192:2013265919]	84	1			T93	1		T59	1		T100	1
auto[2013265920:2147483647]	103	1			T93	1		T221	1		T61	1
auto[2147483648:2281701375]	109	1			T2	2		T14	1		T119	1
auto[2281701376:2415919103]	103	1			T110	1		T218	1		T22	1
auto[2415919104:2550136831]	103	1			T34	1		T20	1		T221	1
auto[2550136832:2684354559]	126	1			T94	1		T60	1		T21	1
auto[2684354560:2818572287]	118	1			T59	1		T61	1		T106	1
auto[2818572288:2952790015]	99	1			T14	1		T28	1		T218	1
auto[2952790016:3087007743]	115	1			T1	1		T2	1		T14	1
auto[3087007744:3221225471]	93	1			T4	1		T20	1		T28	1
auto[3221225472:3355443199]	103	1			T3	2		T4	1		T14	1
auto[3355443200:3489660927]	99	1			T3	1		T93	1		T101	1
auto[3489660928:3623878655]	115	1			T2	1		T19	1		T94	1
auto[3623878656:3758096383]	113	1			T14	1		T93	1		T60	1
auto[3758096384:3892314111]	113	1			T2	2		T14	1		T18	1
auto[3892314112:4026531839]	107	1			T14	1		T28	1		T110	1
auto[4026531840:4160749567]	98	1			T3	1		T34	1		T221	1
auto[4160749568:4294967295]	100	1			T14	1		T221	1		T28	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T14	1		T36	1		T106	1
auto[0:134217727]	auto[1]	50	1			T1	1		T221	1		T28	1
auto[134217728:268435455]	auto[0]	50	1			T221	1		T64	1		T30	1
auto[134217728:268435455]	auto[1]	57	1			T120	1		T28	1		T45	1
auto[268435456:402653183]	auto[0]	51	1			T93	1		T103	2		T108	1
auto[268435456:402653183]	auto[1]	54	1			T217	1		T110	1		T45	1
auto[402653184:536870911]	auto[0]	46	1			T14	1		T60	1		T36	1
auto[402653184:536870911]	auto[1]	67	1			T18	1		T28	1		T102	1
auto[536870912:671088639]	auto[0]	49	1			T28	1		T61	1		T46	1
auto[536870912:671088639]	auto[1]	53	1			T45	1		T103	1		T104	1
auto[671088640:805306367]	auto[0]	44	1			T19	1		T108	1		T199	1
auto[671088640:805306367]	auto[1]	60	1			T103	1		T48	1		T291	1
auto[805306368:939524095]	auto[0]	49	1			T30	1		T48	1		T7	1
auto[805306368:939524095]	auto[1]	51	1			T221	1		T103	2		T140	1
auto[939524096:1073741823]	auto[0]	49	1			T28	1		T135	1		T265	1
auto[939524096:1073741823]	auto[1]	58	1			T18	1		T217	1		T64	2
auto[1073741824:1207959551]	auto[0]	35	1			T36	1		T103	3		T104	1
auto[1073741824:1207959551]	auto[1]	53	1			T59	1		T101	1		T45	1
auto[1207959552:1342177279]	auto[0]	43	1			T94	1		T36	1		T69	1
auto[1207959552:1342177279]	auto[1]	49	1			T107	1		T199	1		T263	1
auto[1342177280:1476395007]	auto[0]	45	1			T20	1		T21	1		T48	1
auto[1342177280:1476395007]	auto[1]	59	1			T14	1		T36	1		T103	1
auto[1476395008:1610612735]	auto[0]	46	1			T94	1		T36	1		T21	1
auto[1476395008:1610612735]	auto[1]	57	1			T18	1		T45	1		T65	1
auto[1610612736:1744830463]	auto[0]	52	1			T21	1		T110	1		T102	1
auto[1610612736:1744830463]	auto[1]	55	1			T93	1		T230	1		T119	1
auto[1744830464:1879048191]	auto[0]	54	1			T2	1		T60	1		T230	1
auto[1744830464:1879048191]	auto[1]	56	1			T221	1		T101	1		T46	1
auto[1879048192:2013265919]	auto[0]	38	1			T100	1		T200	1		T284	1
auto[1879048192:2013265919]	auto[1]	46	1			T93	1		T59	1		T122	1
auto[2013265920:2147483647]	auto[0]	51	1			T93	1		T61	1		T69	1
auto[2013265920:2147483647]	auto[1]	52	1			T221	1		T102	1		T107	1
auto[2147483648:2281701375]	auto[0]	58	1			T2	1		T14	1		T46	1
auto[2147483648:2281701375]	auto[1]	51	1			T2	1		T119	1		T45	1
auto[2281701376:2415919103]	auto[0]	50	1			T103	2		T205	1		T287	1
auto[2281701376:2415919103]	auto[1]	53	1			T110	1		T218	1		T22	1
auto[2415919104:2550136831]	auto[0]	42	1			T221	1		T101	1		T230	1
auto[2415919104:2550136831]	auto[1]	61	1			T34	1		T20	1		T45	1
auto[2550136832:2684354559]	auto[0]	61	1			T94	1		T60	1		T21	1
auto[2550136832:2684354559]	auto[1]	65	1			T101	1		T230	1		T106	1
auto[2684354560:2818572287]	auto[0]	56	1			T106	1		T30	2		T103	1
auto[2684354560:2818572287]	auto[1]	62	1			T59	1		T61	1		T222	1
auto[2818572288:2952790015]	auto[0]	48	1			T14	1		T218	1		T106	1
auto[2818572288:2952790015]	auto[1]	51	1			T28	1		T70	1		T30	1
auto[2952790016:3087007743]	auto[0]	58	1			T2	1		T14	1		T45	1
auto[2952790016:3087007743]	auto[1]	57	1			T1	1		T59	1		T100	1
auto[3087007744:3221225471]	auto[0]	47	1			T4	1		T36	1		T103	2
auto[3087007744:3221225471]	auto[1]	46	1			T20	1		T28	1		T56	1
auto[3221225472:3355443199]	auto[0]	47	1			T14	1		T230	1		T106	1
auto[3221225472:3355443199]	auto[1]	56	1			T3	2		T4	1		T18	1
auto[3355443200:3489660927]	auto[0]	50	1			T106	1		T69	1		T103	1
auto[3355443200:3489660927]	auto[1]	49	1			T3	1		T93	1		T101	1
auto[3489660928:3623878655]	auto[0]	60	1			T19	1		T94	1		T122	1
auto[3489660928:3623878655]	auto[1]	55	1			T2	1		T100	1		T127	1
auto[3623878656:3758096383]	auto[0]	50	1			T14	1		T199	1		T104	1
auto[3623878656:3758096383]	auto[1]	63	1			T93	1		T60	1		T110	1
auto[3758096384:3892314111]	auto[0]	52	1			T2	1		T14	1		T18	1
auto[3758096384:3892314111]	auto[1]	61	1			T2	1		T94	1		T45	2
auto[3892314112:4026531839]	auto[0]	52	1			T14	1		T122	1		T69	1
auto[3892314112:4026531839]	auto[1]	55	1			T28	1		T110	1		T216	1
auto[4026531840:4160749567]	auto[0]	54	1			T34	1		T61	1		T106	1
auto[4026531840:4160749567]	auto[1]	44	1			T3	1		T221	1		T56	1
auto[4160749568:4294967295]	auto[0]	48	1			T14	1		T28	1		T56	1
auto[4160749568:4294967295]	auto[1]	52	1			T221	1		T45	1		T30	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1592

1

T2

5

T4

1

T14

10

auto[1]

1749

1

T1

2

T2

2

T3

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T2	1		T93	1		T59	1
auto[134217728:268435455]	98	1			T14	1		T61	1		T230	1
auto[268435456:402653183]	100	1			T93	1		T110	1		T101	1
auto[402653184:536870911]	115	1			T4	1		T28	1		T127	1
auto[536870912:671088639]	94	1			T94	1		T56	2		T45	1
auto[671088640:805306367]	124	1			T2	1		T14	1		T28	1
auto[805306368:939524095]	81	1			T28	1		T59	1		T100	1
auto[939524096:1073741823]	99	1			T14	1		T20	1		T61	1
auto[1073741824:1207959551]	102	1			T69	1		T222	1		T74	1
auto[1207959552:1342177279]	116	1			T94	1		T59	1		T218	1
auto[1342177280:1476395007]	113	1			T2	1		T221	2		T28	1
auto[1476395008:1610612735]	91	1			T110	1		T100	1		T106	1
auto[1610612736:1744830463]	131	1			T2	1		T14	2		T18	1
auto[1744830464:1879048191]	101	1			T34	1		T94	1		T221	1
auto[1879048192:2013265919]	114	1			T221	1		T21	1		T100	1
auto[2013265920:2147483647]	116	1			T93	1		T230	1		T218	1
auto[2147483648:2281701375]	101	1			T2	1		T3	1		T28	1
auto[2281701376:2415919103]	110	1			T2	1		T217	1		T101	1
auto[2415919104:2550136831]	110	1			T14	1		T93	1		T20	1
auto[2550136832:2684354559]	105	1			T3	1		T230	1		T68	1
auto[2684354560:2818572287]	96	1			T1	1		T3	2		T110	1
auto[2818572288:2952790015]	95	1			T14	1		T19	1		T60	1
auto[2952790016:3087007743]	110	1			T28	1		T60	1		T45	1
auto[3087007744:3221225471]	87	1			T94	1		T28	1		T46	1
auto[3221225472:3355443199]	101	1			T14	1		T36	1		T21	1
auto[3355443200:3489660927]	99	1			T110	1		T106	1		T102	1
auto[3489660928:3623878655]	107	1			T28	1		T59	1		T122	1
auto[3623878656:3758096383]	101	1			T18	1		T20	1		T60	1
auto[3758096384:3892314111]	113	1			T14	1		T18	2		T19	1
auto[3892314112:4026531839]	99	1			T1	1		T2	1		T4	1
auto[4026531840:4160749567]	100	1			T18	1		T93	1		T94	1
auto[4160749568:4294967295]	104	1			T14	1		T120	1		T221	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	52	1			T2	1		T59	1		T36	2
auto[0:134217727]	auto[1]	56	1			T93	1		T101	1		T316	1
auto[134217728:268435455]	auto[0]	44	1			T14	1		T61	1		T230	1
auto[134217728:268435455]	auto[1]	54	1			T45	1		T46	1		T205	1
auto[268435456:402653183]	auto[0]	45	1			T93	1		T127	1		T103	3
auto[268435456:402653183]	auto[1]	55	1			T110	1		T101	1		T107	1
auto[402653184:536870911]	auto[0]	63	1			T4	1		T106	2		T45	1
auto[402653184:536870911]	auto[1]	52	1			T28	1		T127	1		T103	1
auto[536870912:671088639]	auto[0]	44	1			T94	1		T56	1		T103	1
auto[536870912:671088639]	auto[1]	50	1			T56	1		T45	1		T263	1
auto[671088640:805306367]	auto[0]	60	1			T14	1		T102	1		T103	2
auto[671088640:805306367]	auto[1]	64	1			T2	1		T28	1		T45	1
auto[805306368:939524095]	auto[0]	33	1			T65	1		T69	1		T104	1
auto[805306368:939524095]	auto[1]	48	1			T28	1		T59	1		T100	1
auto[939524096:1073741823]	auto[0]	54	1			T14	1		T61	1		T108	1
auto[939524096:1073741823]	auto[1]	45	1			T20	1		T217	1		T110	1
auto[1073741824:1207959551]	auto[0]	47	1			T69	1		T222	1		T287	1
auto[1073741824:1207959551]	auto[1]	55	1			T74	1		T75	1		T144	1
auto[1207959552:1342177279]	auto[0]	55	1			T94	1		T106	1		T69	1
auto[1207959552:1342177279]	auto[1]	61	1			T59	1		T218	1		T70	1
auto[1342177280:1476395007]	auto[0]	51	1			T2	1		T28	1		T100	1
auto[1342177280:1476395007]	auto[1]	62	1			T221	2		T45	1		T135	1
auto[1476395008:1610612735]	auto[0]	39	1			T70	1		T103	1		T263	1
auto[1476395008:1610612735]	auto[1]	52	1			T110	1		T100	1		T106	1
auto[1610612736:1744830463]	auto[0]	70	1			T2	1		T14	2		T93	1
auto[1610612736:1744830463]	auto[1]	61	1			T18	1		T221	1		T119	1
auto[1744830464:1879048191]	auto[0]	40	1			T221	1		T134	1		T287	1
auto[1744830464:1879048191]	auto[1]	61	1			T34	1		T94	1		T119	1
auto[1879048192:2013265919]	auto[0]	53	1			T221	1		T21	1		T100	1
auto[1879048192:2013265919]	auto[1]	61	1			T218	1		T107	1		T139	1
auto[2013265920:2147483647]	auto[0]	49	1			T218	1		T72	1		T103	1
auto[2013265920:2147483647]	auto[1]	67	1			T93	1		T230	1		T103	1
auto[2147483648:2281701375]	auto[0]	49	1			T2	1		T36	1		T122	2
auto[2147483648:2281701375]	auto[1]	52	1			T3	1		T28	1		T36	1
auto[2281701376:2415919103]	auto[0]	53	1			T127	1		T106	1		T45	1
auto[2281701376:2415919103]	auto[1]	57	1			T2	1		T217	1		T101	1
auto[2415919104:2550136831]	auto[0]	47	1			T20	1		T64	1		T200	1
auto[2415919104:2550136831]	auto[1]	63	1			T14	1		T93	1		T101	1
auto[2550136832:2684354559]	auto[0]	49	1			T230	1		T222	1		T49	1
auto[2550136832:2684354559]	auto[1]	56	1			T3	1		T68	1		T70	1
auto[2684354560:2818572287]	auto[0]	41	1			T106	1		T103	1		T144	1
auto[2684354560:2818572287]	auto[1]	55	1			T1	1		T3	2		T110	1
auto[2818572288:2952790015]	auto[0]	43	1			T14	1		T19	1		T45	1
auto[2818572288:2952790015]	auto[1]	52	1			T60	1		T122	2		T45	1
auto[2952790016:3087007743]	auto[0]	50	1			T28	1		T60	1		T140	1
auto[2952790016:3087007743]	auto[1]	60	1			T45	1		T199	1		T370	1
auto[3087007744:3221225471]	auto[0]	50	1			T94	1		T205	1		T48	1
auto[3087007744:3221225471]	auto[1]	37	1			T28	1		T46	1		T107	1
auto[3221225472:3355443199]	auto[0]	55	1			T14	1		T36	1		T21	1
auto[3221225472:3355443199]	auto[1]	46	1			T101	1		T103	1		T48	1
auto[3355443200:3489660927]	auto[0]	54	1			T102	1		T5	1		T103	1
auto[3355443200:3489660927]	auto[1]	45	1			T110	1		T106	1		T70	1
auto[3489660928:3623878655]	auto[0]	50	1			T102	1		T30	1		T103	3
auto[3489660928:3623878655]	auto[1]	57	1			T28	1		T59	1		T122	1
auto[3623878656:3758096383]	auto[0]	46	1			T20	1		T60	1		T30	1
auto[3623878656:3758096383]	auto[1]	55	1			T18	1		T230	1		T119	1
auto[3758096384:3892314111]	auto[0]	53	1			T14	1		T18	1		T64	1
auto[3758096384:3892314111]	auto[1]	60	1			T18	1		T19	1		T60	1
auto[3892314112:4026531839]	auto[0]	45	1			T2	1		T14	1		T34	1
auto[3892314112:4026531839]	auto[1]	54	1			T1	1		T4	1		T103	2
auto[4026531840:4160749567]	auto[0]	51	1			T93	1		T94	1		T21	1
auto[4026531840:4160749567]	auto[1]	49	1			T18	1		T221	2		T46	1
auto[4160749568:4294967295]	auto[0]	57	1			T14	1		T21	1		T30	1
auto[4160749568:4294967295]	auto[1]	47	1			T120	1		T221	1		T28	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1599

1

T2

4

T3

1

T14

10

auto[1]

1741

1

T1

2

T2

3

T3

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T18	1		T36	2		T119	1
auto[134217728:268435455]	93	1			T2	1		T93	1		T127	1
auto[268435456:402653183]	116	1			T2	1		T14	1		T93	1
auto[402653184:536870911]	105	1			T14	1		T120	1		T94	2
auto[536870912:671088639]	103	1			T28	2		T56	1		T61	1
auto[671088640:805306367]	129	1			T3	1		T59	1		T60	1
auto[805306368:939524095]	88	1			T216	1		T100	1		T45	1
auto[939524096:1073741823]	104	1			T221	1		T59	1		T36	2
auto[1073741824:1207959551]	102	1			T60	1		T21	1		T107	1
auto[1207959552:1342177279]	103	1			T93	1		T221	1		T36	1
auto[1342177280:1476395007]	99	1			T14	1		T94	1		T221	1
auto[1476395008:1610612735]	85	1			T3	1		T93	1		T221	1
auto[1610612736:1744830463]	109	1			T93	1		T19	1		T20	1
auto[1744830464:1879048191]	101	1			T19	1		T122	1		T101	1
auto[1879048192:2013265919]	121	1			T14	1		T28	1		T61	1
auto[2013265920:2147483647]	105	1			T59	1		T102	1		T64	2
auto[2147483648:2281701375]	99	1			T1	1		T4	1		T21	1
auto[2281701376:2415919103]	102	1			T2	1		T3	1		T221	1
auto[2415919104:2550136831]	113	1			T14	2		T221	2		T46	1
auto[2550136832:2684354559]	93	1			T106	1		T46	1		T69	1
auto[2684354560:2818572287]	100	1			T1	1		T3	1		T94	1
auto[2818572288:2952790015]	95	1			T110	1		T200	1		T104	1
auto[2952790016:3087007743]	112	1			T101	1		T230	1		T64	1
auto[3087007744:3221225471]	107	1			T21	1		T122	1		T230	1
auto[3221225472:3355443199]	99	1			T2	1		T18	1		T45	2
auto[3355443200:3489660927]	120	1			T14	1		T18	1		T34	1
auto[3489660928:3623878655]	126	1			T2	1		T4	1		T14	1
auto[3623878656:3758096383]	107	1			T14	1		T28	1		T60	1
auto[3758096384:3892314111]	105	1			T2	1		T18	1		T110	1
auto[3892314112:4026531839]	110	1			T18	1		T34	1		T94	1
auto[4026531840:4160749567]	108	1			T2	1		T14	2		T20	1
auto[4160749568:4294967295]	79	1			T93	1		T122	1		T69	1