Unified Coverage Report :: Group Instance : max_owner_int_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4456

1

T1

4

T2

12

T3

6

auto[1]

2224

1

T2

2

T3

2

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	222	1			T2	2		T110	2		T102	2
auto[134217728:268435455]	188	1			T2	2		T4	2		T19	2
auto[268435456:402653183]	212	1			T28	2		T230	2		T46	2
auto[402653184:536870911]	246	1			T14	2		T28	2		T127	2
auto[536870912:671088639]	188	1			T14	2		T93	2		T56	2
auto[671088640:805306367]	216	1			T1	2		T20	2		T36	2
auto[805306368:939524095]	244	1			T4	2		T93	2		T221	2
auto[939524096:1073741823]	238	1			T14	2		T19	2		T20	2
auto[1073741824:1207959551]	216	1			T2	2		T14	2		T221	2
auto[1207959552:1342177279]	234	1			T2	2		T18	2		T221	2
auto[1342177280:1476395007]	214	1			T28	2		T101	2		T230	2
auto[1476395008:1610612735]	180	1			T14	2		T93	2		T94	2
auto[1610612736:1744830463]	184	1			T18	2		T34	2		T20	2
auto[1744830464:1879048191]	220	1			T221	2		T60	2		T110	2
auto[1879048192:2013265919]	210	1			T1	2		T14	2		T34	2
auto[2013265920:2147483647]	220	1			T3	2		T93	2		T122	2
auto[2147483648:2281701375]	204	1			T2	2		T18	2		T221	2
auto[2281701376:2415919103]	194	1			T28	2		T36	2		T61	2
auto[2415919104:2550136831]	208	1			T14	2		T120	2		T218	2
auto[2550136832:2684354559]	202	1			T28	2		T101	2		T46	2
auto[2684354560:2818572287]	218	1			T2	2		T94	2		T59	2
auto[2818572288:2952790015]	236	1			T3	2		T28	2		T127	2
auto[2952790016:3087007743]	202	1			T60	2		T110	2		T45	2
auto[3087007744:3221225471]	212	1			T3	2		T94	2		T122	2
auto[3221225472:3355443199]	218	1			T18	2		T64	2		T47	2
auto[3355443200:3489660927]	160	1			T3	2		T14	2		T94	2
auto[3489660928:3623878655]	200	1			T14	2		T93	2		T59	2
auto[3623878656:3758096383]	182	1			T14	2		T60	2		T36	2
auto[3758096384:3892314111]	184	1			T93	2		T28	2		T60	2
auto[3892314112:4026531839]	206	1			T2	2		T14	2		T18	2
auto[4026531840:4160749567]	208	1			T28	2		T216	2		T100	2
auto[4160749568:4294967295]	214	1			T94	2		T46	2		T107	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	144	1			T2	2		T110	2		T102	2
auto[0:134217727]	auto[1]	78	1			T48	8		T140	2		T260	2
auto[134217728:268435455]	auto[0]	120	1			T2	2		T4	2		T19	2
auto[134217728:268435455]	auto[1]	68	1			T101	2		T218	2		T119	2
auto[268435456:402653183]	auto[0]	148	1			T28	2		T46	2		T30	2
auto[268435456:402653183]	auto[1]	64	1			T230	2		T49	2		T300	2
auto[402653184:536870911]	auto[0]	166	1			T14	2		T28	2		T134	2
auto[402653184:536870911]	auto[1]	80	1			T127	2		T45	2		T102	2
auto[536870912:671088639]	auto[0]	126	1			T14	2		T93	2		T56	2
auto[536870912:671088639]	auto[1]	62	1			T47	2		T207	2		T373	2
auto[671088640:805306367]	auto[0]	148	1			T1	2		T20	2		T69	2
auto[671088640:805306367]	auto[1]	68	1			T36	2		T222	2		T47	2
auto[805306368:939524095]	auto[0]	166	1			T4	2		T93	2		T221	2
auto[805306368:939524095]	auto[1]	78	1			T122	2		T139	2		T207	2
auto[939524096:1073741823]	auto[0]	148	1			T14	2		T20	2		T122	2
auto[939524096:1073741823]	auto[1]	90	1			T19	2		T61	2		T230	2
auto[1073741824:1207959551]	auto[0]	144	1			T2	2		T14	2		T21	2
auto[1073741824:1207959551]	auto[1]	72	1			T221	2		T36	2		T127	2
auto[1207959552:1342177279]	auto[0]	154	1			T2	2		T18	2		T221	2
auto[1207959552:1342177279]	auto[1]	80	1			T28	2		T59	2		T106	2
auto[1342177280:1476395007]	auto[0]	160	1			T28	2		T101	2		T230	2
auto[1342177280:1476395007]	auto[1]	54	1			T140	2		T295	2		T109	2
auto[1476395008:1610612735]	auto[0]	124	1			T93	2		T221	2		T36	2
auto[1476395008:1610612735]	auto[1]	56	1			T14	2		T94	2		T230	2
auto[1610612736:1744830463]	auto[0]	140	1			T18	2		T221	2		T101	2
auto[1610612736:1744830463]	auto[1]	44	1			T34	2		T20	2		T79	2
auto[1744830464:1879048191]	auto[0]	162	1			T221	2		T60	2		T110	2
auto[1744830464:1879048191]	auto[1]	58	1			T122	2		T45	2		T48	4
auto[1879048192:2013265919]	auto[0]	140	1			T1	2		T14	2		T34	2
auto[1879048192:2013265919]	auto[1]	70	1			T106	2		T45	2		T103	2
auto[2013265920:2147483647]	auto[0]	158	1			T3	2		T122	2		T101	2
auto[2013265920:2147483647]	auto[1]	62	1			T93	2		T103	2		T207	2
auto[2147483648:2281701375]	auto[0]	122	1			T2	2		T18	2		T221	2
auto[2147483648:2281701375]	auto[1]	82	1			T59	2		T119	4		T106	2
auto[2281701376:2415919103]	auto[0]	136	1			T28	2		T36	2		T106	4
auto[2281701376:2415919103]	auto[1]	58	1			T61	2		T21	2		T103	2
auto[2415919104:2550136831]	auto[0]	144	1			T14	2		T218	2		T106	2
auto[2415919104:2550136831]	auto[1]	64	1			T120	2		T45	2		T102	2
auto[2550136832:2684354559]	auto[0]	140	1			T28	2		T101	2		T103	4
auto[2550136832:2684354559]	auto[1]	62	1			T46	2		T65	2		T68	2
auto[2684354560:2818572287]	auto[0]	146	1			T59	2		T70	2		T30	2
auto[2684354560:2818572287]	auto[1]	72	1			T2	2		T94	2		T200	2
auto[2818572288:2952790015]	auto[0]	142	1			T3	2		T45	2		T103	6
auto[2818572288:2952790015]	auto[1]	94	1			T28	2		T127	2		T222	2
auto[2952790016:3087007743]	auto[0]	134	1			T110	2		T107	2		T108	2
auto[2952790016:3087007743]	auto[1]	68	1			T60	2		T45	2		T64	2
auto[3087007744:3221225471]	auto[0]	132	1			T94	2		T122	2		T46	2
auto[3087007744:3221225471]	auto[1]	80	1			T3	2		T68	2		T287	2
auto[3221225472:3355443199]	auto[0]	146	1			T18	2		T64	2		T199	2
auto[3221225472:3355443199]	auto[1]	72	1			T47	2		T38	2		T260	2
auto[3355443200:3489660927]	auto[0]	106	1			T3	2		T14	2		T94	2
auto[3355443200:3489660927]	auto[1]	54	1			T30	2		T287	2		T76	2
auto[3489660928:3623878655]	auto[0]	124	1			T14	2		T93	2		T102	2
auto[3489660928:3623878655]	auto[1]	76	1			T59	2		T102	2		T295	2
auto[3623878656:3758096383]	auto[0]	114	1			T14	2		T60	2		T36	2
auto[3623878656:3758096383]	auto[1]	68	1			T64	2		T222	2		T49	4
auto[3758096384:3892314111]	auto[0]	112	1			T217	2		T64	2		T199	2
auto[3758096384:3892314111]	auto[1]	72	1			T93	2		T28	2		T60	2
auto[3892314112:4026531839]	auto[0]	136	1			T2	2		T14	2		T18	2
auto[3892314112:4026531839]	auto[1]	70	1			T61	2		T72	2		T140	2
auto[4026531840:4160749567]	auto[0]	134	1			T28	2		T100	2		T107	2
auto[4026531840:4160749567]	auto[1]	74	1			T216	2		T103	4		T49	4
auto[4160749568:4294967295]	auto[0]	140	1			T94	2		T46	2		T107	2
auto[4160749568:4294967295]	auto[1]	74	1			T103	2		T48	2		T143	2