Unified Coverage Report :: Group Instance : salt_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2916

1

T1

2

T2

7

T3

4

auto[1]

237

1

T60

5

T100

4

T64

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	94	1			T2	1		T20	1		T122	1
auto[134217728:268435455]	116	1			T2	1		T18	1		T19	1
auto[268435456:402653183]	102	1			T4	1		T221	1		T59	1
auto[402653184:536870911]	102	1			T221	1		T60	2		T106	1
auto[536870912:671088639]	110	1			T1	1		T18	1		T221	1
auto[671088640:805306367]	105	1			T2	1		T36	1		T110	1
auto[805306368:939524095]	110	1			T34	1		T20	1		T221	1
auto[939524096:1073741823]	82	1			T122	1		T106	2		T64	3
auto[1073741824:1207959551]	112	1			T94	1		T60	1		T61	2
auto[1207959552:1342177279]	123	1			T2	1		T93	1		T221	1
auto[1342177280:1476395007]	92	1			T14	1		T110	1		T106	1
auto[1476395008:1610612735]	115	1			T2	1		T18	1		T100	1
auto[1610612736:1744830463]	103	1			T45	1		T64	1		T103	2
auto[1744830464:1879048191]	104	1			T94	1		T60	1		T36	1
auto[1879048192:2013265919]	90	1			T3	1		T4	1		T36	1
auto[2013265920:2147483647]	98	1			T14	1		T93	1		T28	1
auto[2147483648:2281701375]	93	1			T56	1		T36	1		T110	1
auto[2281701376:2415919103]	90	1			T18	1		T60	1		T119	1
auto[2415919104:2550136831]	87	1			T217	1		T119	1		T65	1
auto[2550136832:2684354559]	93	1			T3	1		T28	1		T110	1
auto[2684354560:2818572287]	89	1			T28	1		T36	2		T122	1
auto[2818572288:2952790015]	82	1			T1	1		T94	1		T60	1
auto[2952790016:3087007743]	95	1			T217	1		T106	1		T64	1
auto[3087007744:3221225471]	97	1			T28	1		T21	1		T100	1
auto[3221225472:3355443199]	111	1			T3	1		T28	1		T59	1
auto[3355443200:3489660927]	103	1			T2	1		T3	1		T34	1
auto[3489660928:3623878655]	92	1			T221	1		T100	1		T122	1
auto[3623878656:3758096383]	72	1			T18	1		T28	2		T60	1
auto[3758096384:3892314111]	105	1			T14	1		T221	1		T56	1
auto[3892314112:4026531839]	111	1			T2	1		T59	1		T21	1
auto[4026531840:4160749567]	90	1			T28	1		T101	1		T218	1
auto[4160749568:4294967295]	85	1			T120	1		T100	1		T107	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	85	1			T2	1		T20	1		T122	1
auto[0:134217727]	auto[1]	9	1			T105	1		T75	1		T268	1
auto[134217728:268435455]	auto[0]	104	1			T2	1		T18	1		T19	1
auto[134217728:268435455]	auto[1]	12	1			T60	1		T75	1		T250	1
auto[268435456:402653183]	auto[0]	90	1			T4	1		T221	1		T59	1
auto[268435456:402653183]	auto[1]	12	1			T64	1		T265	1		T268	2
auto[402653184:536870911]	auto[0]	94	1			T221	1		T60	1		T106	1
auto[402653184:536870911]	auto[1]	8	1			T60	1		T105	2		T74	1
auto[536870912:671088639]	auto[0]	100	1			T1	1		T18	1		T221	1
auto[536870912:671088639]	auto[1]	10	1			T74	1		T77	1		T274	1
auto[671088640:805306367]	auto[0]	100	1			T2	1		T36	1		T110	1
auto[671088640:805306367]	auto[1]	5	1			T278	1		T312	1		T390	1
auto[805306368:939524095]	auto[0]	102	1			T34	1		T20	1		T221	1
auto[805306368:939524095]	auto[1]	8	1			T268	2		T390	1		T422	1
auto[939524096:1073741823]	auto[0]	78	1			T122	1		T106	2		T68	1
auto[939524096:1073741823]	auto[1]	4	1			T64	3		T312	1		-	-
auto[1073741824:1207959551]	auto[0]	104	1			T94	1		T61	2		T21	1
auto[1073741824:1207959551]	auto[1]	8	1			T60	1		T100	1		T80	1
auto[1207959552:1342177279]	auto[0]	114	1			T2	1		T93	1		T221	1
auto[1207959552:1342177279]	auto[1]	9	1			T80	1		T409	1		T324	1
auto[1342177280:1476395007]	auto[0]	82	1			T14	1		T110	1		T106	1
auto[1342177280:1476395007]	auto[1]	10	1			T301	1		T274	1		T409	1
auto[1476395008:1610612735]	auto[0]	105	1			T2	1		T18	1		T127	1
auto[1476395008:1610612735]	auto[1]	10	1			T100	1		T105	2		T80	2
auto[1610612736:1744830463]	auto[0]	94	1			T45	1		T103	2		T199	1
auto[1610612736:1744830463]	auto[1]	9	1			T64	1		T105	1		T274	1
auto[1744830464:1879048191]	auto[0]	100	1			T94	1		T36	1		T21	1
auto[1744830464:1879048191]	auto[1]	4	1			T60	1		T75	1		T422	1
auto[1879048192:2013265919]	auto[0]	81	1			T3	1		T4	1		T36	1
auto[1879048192:2013265919]	auto[1]	9	1			T74	1		T75	1		T301	1
auto[2013265920:2147483647]	auto[0]	91	1			T14	1		T93	1		T28	1
auto[2013265920:2147483647]	auto[1]	7	1			T268	1		T80	1		T312	1
auto[2147483648:2281701375]	auto[0]	83	1			T56	1		T36	1		T110	1
auto[2147483648:2281701375]	auto[1]	10	1			T74	1		T268	1		T264	1
auto[2281701376:2415919103]	auto[0]	81	1			T18	1		T60	1		T119	1
auto[2281701376:2415919103]	auto[1]	9	1			T105	2		T412	1		T422	1
auto[2415919104:2550136831]	auto[0]	82	1			T217	1		T119	1		T65	1
auto[2415919104:2550136831]	auto[1]	5	1			T77	1		T80	1		T412	1
auto[2550136832:2684354559]	auto[0]	86	1			T3	1		T28	1		T110	1
auto[2550136832:2684354559]	auto[1]	7	1			T274	1		T422	2		T348	2
auto[2684354560:2818572287]	auto[0]	85	1			T28	1		T36	2		T122	1
auto[2684354560:2818572287]	auto[1]	4	1			T301	1		T264	1		T409	1
auto[2818572288:2952790015]	auto[0]	78	1			T1	1		T94	1		T60	1
auto[2818572288:2952790015]	auto[1]	4	1			T264	1		T422	1		T429	1
auto[2952790016:3087007743]	auto[0]	87	1			T217	1		T106	1		T64	1
auto[2952790016:3087007743]	auto[1]	8	1			T74	1		T77	2		T254	2
auto[3087007744:3221225471]	auto[0]	91	1			T28	1		T21	1		T100	1
auto[3087007744:3221225471]	auto[1]	6	1			T64	1		T409	1		T250	2
auto[3221225472:3355443199]	auto[0]	102	1			T3	1		T28	1		T59	1
auto[3221225472:3355443199]	auto[1]	9	1			T100	1		T265	1		T268	2
auto[3355443200:3489660927]	auto[0]	95	1			T2	1		T3	1		T34	1
auto[3355443200:3489660927]	auto[1]	8	1			T105	1		T264	1		T412	1
auto[3489660928:3623878655]	auto[0]	86	1			T221	1		T122	1		T127	1
auto[3489660928:3623878655]	auto[1]	6	1			T100	1		T80	1		T278	1
auto[3623878656:3758096383]	auto[0]	66	1			T18	1		T28	2		T22	1
auto[3623878656:3758096383]	auto[1]	6	1			T60	1		T64	1		T75	1
auto[3758096384:3892314111]	auto[0]	97	1			T14	1		T221	1		T56	1
auto[3758096384:3892314111]	auto[1]	8	1			T301	1		T390	1		T422	2
auto[3892314112:4026531839]	auto[0]	106	1			T2	1		T59	1		T21	1
auto[3892314112:4026531839]	auto[1]	5	1			T390	1		T250	1		T294	2
auto[4026531840:4160749567]	auto[0]	86	1			T28	1		T101	1		T218	1
auto[4026531840:4160749567]	auto[1]	4	1			T105	1		T422	1		T408	1
auto[4160749568:4294967295]	auto[0]	81	1			T120	1		T100	1		T107	1
auto[4160749568:4294967295]	auto[1]	4	1			T422	1		T348	1		T430	1