Unified Coverage Report :: Group Instance : sealing_sw_binding_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1607

1

T2

5

T14

10

T34

1

auto[1]

1733

1

T1

2

T2

2

T3

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T14	1		T61	1		T46	1
auto[134217728:268435455]	86	1			T18	1		T72	1		T30	1
auto[268435456:402653183]	104	1			T221	1		T28	1		T61	1
auto[402653184:536870911]	90	1			T2	1		T60	1		T216	1
auto[536870912:671088639]	134	1			T1	1		T221	2		T60	1
auto[671088640:805306367]	122	1			T3	1		T120	1		T93	1
auto[805306368:939524095]	97	1			T4	1		T20	1		T230	1
auto[939524096:1073741823]	98	1			T14	1		T19	1		T94	1
auto[1073741824:1207959551]	113	1			T14	1		T93	1		T36	1
auto[1207959552:1342177279]	114	1			T2	1		T3	1		T34	1
auto[1342177280:1476395007]	95	1			T14	1		T59	1		T100	1
auto[1476395008:1610612735]	103	1			T94	1		T221	1		T64	1
auto[1610612736:1744830463]	106	1			T1	1		T18	1		T28	2
auto[1744830464:1879048191]	108	1			T2	1		T59	1		T230	1
auto[1879048192:2013265919]	95	1			T14	2		T18	2		T36	1
auto[2013265920:2147483647]	106	1			T2	1		T230	1		T64	1
auto[2147483648:2281701375]	125	1			T14	1		T60	1		T100	1
auto[2281701376:2415919103]	95	1			T93	1		T56	1		T36	1
auto[2415919104:2550136831]	90	1			T93	1		T56	1		T122	1
auto[2550136832:2684354559]	107	1			T34	1		T45	1		T102	1
auto[2684354560:2818572287]	89	1			T2	1		T14	1		T28	1
auto[2818572288:2952790015]	108	1			T14	1		T93	1		T19	1
auto[2952790016:3087007743]	109	1			T14	1		T28	1		T60	1
auto[3087007744:3221225471]	99	1			T18	1		T60	1		T36	1
auto[3221225472:3355443199]	102	1			T101	1		T103	4		T199	1
auto[3355443200:3489660927]	112	1			T20	1		T221	1		T64	1
auto[3489660928:3623878655]	103	1			T122	1		T218	1		T106	2
auto[3623878656:3758096383]	109	1			T2	1		T94	2		T36	1
auto[3758096384:3892314111]	99	1			T28	1		T101	2		T134	1
auto[3892314112:4026531839]	105	1			T3	1		T4	1		T14	1
auto[4026531840:4160749567]	110	1			T2	1		T20	1		T217	1
auto[4160749568:4294967295]	106	1			T3	1		T94	1		T28	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	49	1			T14	1		T46	1		T48	1
auto[0:134217727]	auto[1]	52	1			T61	1		T74	1		T207	2
auto[134217728:268435455]	auto[0]	45	1			T72	1		T30	1		T103	1
auto[134217728:268435455]	auto[1]	41	1			T18	1		T200	1		T295	1
auto[268435456:402653183]	auto[0]	54	1			T61	1		T106	1		T69	1
auto[268435456:402653183]	auto[1]	50	1			T221	1		T28	1		T45	1
auto[402653184:536870911]	auto[0]	50	1			T2	1		T60	1		T68	1
auto[402653184:536870911]	auto[1]	40	1			T216	1		T100	1		T45	1
auto[536870912:671088639]	auto[0]	71	1			T221	2		T60	1		T110	1
auto[536870912:671088639]	auto[1]	63	1			T1	1		T110	1		T127	1
auto[671088640:805306367]	auto[0]	62	1			T93	1		T36	1		T100	1
auto[671088640:805306367]	auto[1]	60	1			T3	1		T120	1		T103	1
auto[805306368:939524095]	auto[0]	48	1			T20	1		T230	1		T103	1
auto[805306368:939524095]	auto[1]	49	1			T4	1		T119	1		T45	1
auto[939524096:1073741823]	auto[0]	51	1			T14	1		T19	1		T94	1
auto[939524096:1073741823]	auto[1]	47	1			T217	1		T218	2		T46	1
auto[1073741824:1207959551]	auto[0]	53	1			T14	1		T93	1		T36	1
auto[1073741824:1207959551]	auto[1]	60	1			T119	1		T64	1		T30	1
auto[1207959552:1342177279]	auto[0]	55	1			T106	1		T64	1		T103	1
auto[1207959552:1342177279]	auto[1]	59	1			T2	1		T3	1		T34	1
auto[1342177280:1476395007]	auto[0]	44	1			T14	1		T100	1		T102	1
auto[1342177280:1476395007]	auto[1]	51	1			T59	1		T101	1		T65	1
auto[1476395008:1610612735]	auto[0]	47	1			T94	1		T64	1		T140	1
auto[1476395008:1610612735]	auto[1]	56	1			T221	1		T70	1		T139	1
auto[1610612736:1744830463]	auto[0]	47	1			T28	1		T102	1		T103	1
auto[1610612736:1744830463]	auto[1]	59	1			T1	1		T18	1		T28	1
auto[1744830464:1879048191]	auto[0]	51	1			T2	1		T230	1		T103	1
auto[1744830464:1879048191]	auto[1]	57	1			T59	1		T24	1		T50	1
auto[1879048192:2013265919]	auto[0]	46	1			T14	2		T36	1		T45	1
auto[1879048192:2013265919]	auto[1]	49	1			T18	2		T110	1		T122	1
auto[2013265920:2147483647]	auto[0]	43	1			T30	1		T284	1		T273	1
auto[2013265920:2147483647]	auto[1]	63	1			T2	1		T230	1		T64	1
auto[2147483648:2281701375]	auto[0]	53	1			T14	1		T60	1		T106	1
auto[2147483648:2281701375]	auto[1]	72	1			T100	1		T45	1		T107	1
auto[2281701376:2415919103]	auto[0]	44	1			T56	1		T36	1		T230	1
auto[2281701376:2415919103]	auto[1]	51	1			T93	1		T110	1		T108	1
auto[2415919104:2550136831]	auto[0]	37	1			T127	1		T70	1		T104	1
auto[2415919104:2550136831]	auto[1]	53	1			T93	1		T56	1		T122	1
auto[2550136832:2684354559]	auto[0]	46	1			T34	1		T102	1		T69	1
auto[2550136832:2684354559]	auto[1]	61	1			T45	1		T107	1		T30	1
auto[2684354560:2818572287]	auto[0]	43	1			T2	1		T14	1		T56	1
auto[2684354560:2818572287]	auto[1]	46	1			T28	1		T205	1		T316	1
auto[2818572288:2952790015]	auto[0]	46	1			T14	1		T93	1		T221	1
auto[2818572288:2952790015]	auto[1]	62	1			T19	1		T221	2		T59	1
auto[2952790016:3087007743]	auto[0]	58	1			T14	1		T60	1		T205	1
auto[2952790016:3087007743]	auto[1]	51	1			T28	1		T122	1		T101	1
auto[3087007744:3221225471]	auto[0]	49	1			T60	1		T36	1		T21	1
auto[3087007744:3221225471]	auto[1]	50	1			T18	1		T122	1		T291	1
auto[3221225472:3355443199]	auto[0]	50	1			T103	1		T199	1		T205	1
auto[3221225472:3355443199]	auto[1]	52	1			T101	1		T103	3		T380	1
auto[3355443200:3489660927]	auto[0]	54	1			T64	1		T103	2		T199	1
auto[3355443200:3489660927]	auto[1]	58	1			T20	1		T221	1		T103	1
auto[3489660928:3623878655]	auto[0]	51	1			T106	1		T48	1		T287	1
auto[3489660928:3623878655]	auto[1]	52	1			T122	1		T218	1		T106	1
auto[3623878656:3758096383]	auto[0]	51	1			T2	1		T94	1		T61	1
auto[3623878656:3758096383]	auto[1]	58	1			T94	1		T36	1		T119	1
auto[3758096384:3892314111]	auto[0]	51	1			T134	1		T103	1		T199	1
auto[3758096384:3892314111]	auto[1]	48	1			T28	1		T101	2		T46	2
auto[3892314112:4026531839]	auto[0]	47	1			T28	2		T106	1		T45	1
auto[3892314112:4026531839]	auto[1]	58	1			T3	1		T4	1		T14	1
auto[4026531840:4160749567]	auto[0]	52	1			T2	1		T206	1		T207	1
auto[4026531840:4160749567]	auto[1]	58	1			T20	1		T217	1		T110	1
auto[4160749568:4294967295]	auto[0]	59	1			T94	1		T103	1		T47	1
auto[4160749568:4294967295]	auto[1]	47	1			T3	1		T28	1		T65	1