Unified Coverage Report :: Group Instance : sealing_sw_binding_6

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1596

1

T2

4

T3

1

T4

1

auto[1]

1745

1

T1

2

T2

3

T3

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	92	1			T14	1		T94	1		T100	1
auto[134217728:268435455]	90	1			T14	2		T120	1		T45	1
auto[268435456:402653183]	104	1			T34	1		T56	1		T59	1
auto[402653184:536870911]	92	1			T2	1		T59	1		T36	1
auto[536870912:671088639]	128	1			T14	2		T93	1		T59	1
auto[671088640:805306367]	96	1			T18	1		T28	1		T110	1
auto[805306368:939524095]	101	1			T221	1		T122	1		T101	1
auto[939524096:1073741823]	106	1			T3	1		T14	1		T18	1
auto[1073741824:1207959551]	110	1			T20	1		T60	1		T36	2
auto[1207959552:1342177279]	93	1			T127	1		T46	1		T69	1
auto[1342177280:1476395007]	98	1			T3	1		T221	1		T56	1
auto[1476395008:1610612735]	99	1			T94	1		T36	1		T21	1
auto[1610612736:1744830463]	104	1			T21	1		T106	1		T45	1
auto[1744830464:1879048191]	129	1			T1	1		T3	1		T4	1
auto[1879048192:2013265919]	107	1			T2	1		T230	2		T103	2
auto[2013265920:2147483647]	108	1			T14	1		T56	1		T230	1
auto[2147483648:2281701375]	102	1			T14	1		T20	1		T221	1
auto[2281701376:2415919103]	106	1			T93	2		T94	1		T218	1
auto[2415919104:2550136831]	104	1			T14	1		T18	1		T94	1
auto[2550136832:2684354559]	96	1			T28	1		T61	1		T110	1
auto[2684354560:2818572287]	107	1			T2	1		T14	1		T221	1
auto[2818572288:2952790015]	107	1			T2	1		T4	1		T18	1
auto[2952790016:3087007743]	103	1			T93	1		T59	1		T127	1
auto[3087007744:3221225471]	130	1			T60	1		T100	1		T122	1
auto[3221225472:3355443199]	111	1			T2	1		T93	1		T28	1
auto[3355443200:3489660927]	109	1			T60	1		T110	1		T218	1
auto[3489660928:3623878655]	110	1			T34	1		T221	2		T21	1
auto[3623878656:3758096383]	94	1			T19	1		T20	1		T61	1
auto[3758096384:3892314111]	107	1			T1	1		T3	1		T60	1
auto[3892314112:4026531839]	105	1			T2	2		T19	1		T28	1
auto[4026531840:4160749567]	93	1			T45	1		T72	1		T103	1
auto[4160749568:4294967295]	100	1			T18	1		T93	1		T221	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	49	1			T14	1		T94	1		T100	1
auto[0:134217727]	auto[1]	43	1			T119	1		T46	1		T64	1
auto[134217728:268435455]	auto[0]	38	1			T14	2		T102	1		T103	2
auto[134217728:268435455]	auto[1]	52	1			T120	1		T45	1		T287	1
auto[268435456:402653183]	auto[0]	49	1			T56	1		T100	1		T103	1
auto[268435456:402653183]	auto[1]	55	1			T34	1		T59	1		T230	1
auto[402653184:536870911]	auto[0]	43	1			T36	1		T74	2		T284	1
auto[402653184:536870911]	auto[1]	49	1			T2	1		T59	1		T100	1
auto[536870912:671088639]	auto[0]	60	1			T14	1		T60	1		T101	1
auto[536870912:671088639]	auto[1]	68	1			T14	1		T93	1		T59	1
auto[671088640:805306367]	auto[0]	48	1			T18	1		T28	1		T106	1
auto[671088640:805306367]	auto[1]	48	1			T110	1		T122	1		T101	1
auto[805306368:939524095]	auto[0]	46	1			T106	1		T103	1		T380	1
auto[805306368:939524095]	auto[1]	55	1			T221	1		T122	1		T101	1
auto[939524096:1073741823]	auto[0]	47	1			T14	1		T94	1		T28	1
auto[939524096:1073741823]	auto[1]	59	1			T3	1		T18	1		T217	2
auto[1073741824:1207959551]	auto[0]	63	1			T20	1		T60	1		T36	2
auto[1073741824:1207959551]	auto[1]	47	1			T108	1		T47	1		T48	1
auto[1207959552:1342177279]	auto[0]	49	1			T127	1		T69	1		T103	1
auto[1207959552:1342177279]	auto[1]	44	1			T46	1		T284	1		T7	1
auto[1342177280:1476395007]	auto[0]	40	1			T46	1		T104	1		T287	1
auto[1342177280:1476395007]	auto[1]	58	1			T3	1		T221	1		T56	1
auto[1476395008:1610612735]	auto[0]	52	1			T21	1		T103	2		T222	1
auto[1476395008:1610612735]	auto[1]	47	1			T94	1		T36	1		T216	1
auto[1610612736:1744830463]	auto[0]	50	1			T21	1		T106	1		T64	1
auto[1610612736:1744830463]	auto[1]	54	1			T45	1		T22	1		T47	1
auto[1744830464:1879048191]	auto[0]	55	1			T3	1		T14	1		T45	1
auto[1744830464:1879048191]	auto[1]	74	1			T1	1		T4	1		T122	1
auto[1879048192:2013265919]	auto[0]	58	1			T230	1		T103	1		T47	1
auto[1879048192:2013265919]	auto[1]	49	1			T2	1		T230	1		T103	1
auto[2013265920:2147483647]	auto[0]	59	1			T56	1		T230	1		T103	1
auto[2013265920:2147483647]	auto[1]	49	1			T14	1		T64	1		T103	1
auto[2147483648:2281701375]	auto[0]	41	1			T14	1		T64	1		T103	1
auto[2147483648:2281701375]	auto[1]	61	1			T20	1		T221	1		T28	1
auto[2281701376:2415919103]	auto[0]	49	1			T93	2		T94	1		T30	1
auto[2281701376:2415919103]	auto[1]	57	1			T218	1		T45	1		T5	1
auto[2415919104:2550136831]	auto[0]	55	1			T14	1		T94	1		T221	1
auto[2415919104:2550136831]	auto[1]	49	1			T18	1		T101	1		T24	1
auto[2550136832:2684354559]	auto[0]	53	1			T61	1		T127	1		T199	1
auto[2550136832:2684354559]	auto[1]	43	1			T28	1		T110	1		T69	1
auto[2684354560:2818572287]	auto[0]	57	1			T2	1		T14	1		T36	1
auto[2684354560:2818572287]	auto[1]	50	1			T221	1		T101	1		T45	1
auto[2818572288:2952790015]	auto[0]	50	1			T2	1		T4	1		T18	1
auto[2818572288:2952790015]	auto[1]	57	1			T28	1		T218	1		T119	1
auto[2952790016:3087007743]	auto[0]	45	1			T64	1		T30	1		T222	1
auto[2952790016:3087007743]	auto[1]	58	1			T93	1		T59	1		T127	1
auto[3087007744:3221225471]	auto[0]	65	1			T60	1		T45	1		T134	1
auto[3087007744:3221225471]	auto[1]	65	1			T100	1		T122	1		T45	1
auto[3221225472:3355443199]	auto[0]	48	1			T2	1		T93	1		T230	1
auto[3221225472:3355443199]	auto[1]	63	1			T28	1		T61	1		T64	1
auto[3355443200:3489660927]	auto[0]	44	1			T60	1		T134	1		T70	1
auto[3355443200:3489660927]	auto[1]	65	1			T110	1		T218	1		T106	2
auto[3489660928:3623878655]	auto[0]	45	1			T34	1		T21	1		T69	2
auto[3489660928:3623878655]	auto[1]	65	1			T221	2		T45	1		T48	1
auto[3623878656:3758096383]	auto[0]	54	1			T19	1		T61	1		T64	1
auto[3623878656:3758096383]	auto[1]	40	1			T20	1		T103	2		T207	1
auto[3758096384:3892314111]	auto[0]	47	1			T60	1		T45	1		T102	1
auto[3758096384:3892314111]	auto[1]	60	1			T1	1		T3	1		T101	2
auto[3892314112:4026531839]	auto[0]	56	1			T2	1		T61	1		T287	1
auto[3892314112:4026531839]	auto[1]	49	1			T2	1		T19	1		T28	1
auto[4026531840:4160749567]	auto[0]	35	1			T45	1		T72	1		T200	1
auto[4026531840:4160749567]	auto[1]	58	1			T103	1		T206	1		T48	1
auto[4160749568:4294967295]	auto[0]	46	1			T221	1		T28	1		T106	1
auto[4160749568:4294967295]	auto[1]	54	1			T18	1		T93	1		T28	1