Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6884

1

T1

4

T2

13

T3

13

auto[1]

252

1

T60

8

T100

4

T64

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2878	1			T1	2		T2	6		T3	5
auto[134217728:268435455]	168	1			T4	1		T14	1		T56	1
auto[268435456:402653183]	148	1			T18	1		T94	2		T28	1
auto[402653184:536870911]	136	1			T1	1		T28	1		T60	1
auto[536870912:671088639]	142	1			T18	1		T34	1		T93	1
auto[671088640:805306367]	139	1			T2	1		T3	1		T60	1
auto[805306368:939524095]	125	1			T18	1		T60	1		T36	1
auto[939524096:1073741823]	162	1			T94	1		T217	1		T107	1
auto[1073741824:1207959551]	143	1			T3	1		T221	1		T45	1
auto[1207959552:1342177279]	139	1			T2	1		T14	1		T120	1
auto[1342177280:1476395007]	137	1			T2	1		T21	1		T217	1
auto[1476395008:1610612735]	134	1			T59	1		T60	2		T36	1
auto[1610612736:1744830463]	126	1			T100	1		T45	1		T69	1
auto[1744830464:1879048191]	149	1			T4	1		T34	1		T94	1
auto[1879048192:2013265919]	131	1			T19	1		T20	1		T60	2
auto[2013265920:2147483647]	146	1			T2	1		T28	1		T59	1
auto[2147483648:2281701375]	134	1			T3	1		T18	1		T28	1
auto[2281701376:2415919103]	122	1			T93	1		T94	1		T28	2
auto[2415919104:2550136831]	112	1			T2	1		T20	1		T94	1
auto[2550136832:2684354559]	121	1			T221	1		T61	1		T122	1
auto[2684354560:2818572287]	118	1			T2	1		T94	1		T221	1
auto[2818572288:2952790015]	134	1			T4	1		T221	1		T60	1
auto[2952790016:3087007743]	129	1			T1	1		T3	1		T100	1
auto[3087007744:3221225471]	116	1			T94	1		T28	1		T122	1
auto[3221225472:3355443199]	162	1			T221	1		T28	2		T110	1
auto[3355443200:3489660927]	143	1			T3	2		T14	1		T93	1
auto[3489660928:3623878655]	149	1			T60	1		T101	1		T218	1
auto[3623878656:3758096383]	159	1			T20	1		T59	1		T60	1
auto[3758096384:3892314111]	142	1			T20	1		T94	1		T221	1
auto[3892314112:4026531839]	127	1			T3	1		T28	1		T127	1
auto[4026531840:4160749567]	124	1			T2	1		T18	1		T101	1
auto[4160749568:4294967295]	141	1			T3	1		T93	1		T94	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2865	1			T1	2		T2	6		T3	5
auto[0:134217727]	auto[1]	13	1			T64	2		T105	1		T75	1
auto[134217728:268435455]	auto[0]	160	1			T4	1		T14	1		T56	1
auto[134217728:268435455]	auto[1]	8	1			T268	1		T412	1		T422	1
auto[268435456:402653183]	auto[0]	133	1			T18	1		T94	2		T28	1
auto[268435456:402653183]	auto[1]	15	1			T74	1		T265	1		T268	1
auto[402653184:536870911]	auto[0]	131	1			T1	1		T28	1		T101	1
auto[402653184:536870911]	auto[1]	5	1			T60	1		T100	1		T250	1
auto[536870912:671088639]	auto[0]	139	1			T18	1		T34	1		T93	1
auto[536870912:671088639]	auto[1]	3	1			T60	1		T412	1		T422	1
auto[671088640:805306367]	auto[0]	127	1			T2	1		T3	1		T61	1
auto[671088640:805306367]	auto[1]	12	1			T60	1		T265	1		T80	1
auto[805306368:939524095]	auto[0]	120	1			T18	1		T36	1		T110	1
auto[805306368:939524095]	auto[1]	5	1			T60	1		T64	1		T312	1
auto[939524096:1073741823]	auto[0]	155	1			T94	1		T217	1		T107	1
auto[939524096:1073741823]	auto[1]	7	1			T254	1		T422	1		T406	1
auto[1073741824:1207959551]	auto[0]	136	1			T3	1		T221	1		T45	1
auto[1073741824:1207959551]	auto[1]	7	1			T105	2		T80	1		T422	1
auto[1207959552:1342177279]	auto[0]	135	1			T2	1		T14	1		T120	1
auto[1207959552:1342177279]	auto[1]	4	1			T390	1		T422	1		T294	1
auto[1342177280:1476395007]	auto[0]	127	1			T2	1		T21	1		T217	1
auto[1342177280:1476395007]	auto[1]	10	1			T74	1		T75	1		T80	2
auto[1476395008:1610612735]	auto[0]	125	1			T59	1		T36	1		T21	1
auto[1476395008:1610612735]	auto[1]	9	1			T60	2		T268	1		T312	1
auto[1610612736:1744830463]	auto[0]	123	1			T45	1		T69	1		T48	1
auto[1610612736:1744830463]	auto[1]	3	1			T100	1		T424	1		T345	1
auto[1744830464:1879048191]	auto[0]	141	1			T4	1		T34	1		T94	1
auto[1744830464:1879048191]	auto[1]	8	1			T312	1		T324	1		T412	1
auto[1879048192:2013265919]	auto[0]	126	1			T19	1		T20	1		T46	1
auto[1879048192:2013265919]	auto[1]	5	1			T60	2		T64	1		T296	1
auto[2013265920:2147483647]	auto[0]	140	1			T2	1		T28	1		T59	1
auto[2013265920:2147483647]	auto[1]	6	1			T77	1		T274	1		T424	1
auto[2147483648:2281701375]	auto[0]	129	1			T3	1		T18	1		T28	1
auto[2147483648:2281701375]	auto[1]	5	1			T301	1		T409	1		T312	1
auto[2281701376:2415919103]	auto[0]	118	1			T93	1		T94	1		T28	2
auto[2281701376:2415919103]	auto[1]	4	1			T75	1		T350	1		T385	1
auto[2415919104:2550136831]	auto[0]	105	1			T2	1		T20	1		T94	1
auto[2415919104:2550136831]	auto[1]	7	1			T105	1		T390	1		T294	2
auto[2550136832:2684354559]	auto[0]	110	1			T221	1		T61	1		T122	1
auto[2550136832:2684354559]	auto[1]	11	1			T265	1		T268	1		T409	1
auto[2684354560:2818572287]	auto[0]	110	1			T2	1		T94	1		T221	1
auto[2684354560:2818572287]	auto[1]	8	1			T100	1		T75	1		T264	1
auto[2818572288:2952790015]	auto[0]	125	1			T4	1		T221	1		T60	1
auto[2818572288:2952790015]	auto[1]	9	1			T64	1		T324	1		T294	1
auto[2952790016:3087007743]	auto[0]	124	1			T1	1		T3	1		T100	1
auto[2952790016:3087007743]	auto[1]	5	1			T254	1		T348	2		T362	1
auto[3087007744:3221225471]	auto[0]	108	1			T94	1		T28	1		T122	1
auto[3087007744:3221225471]	auto[1]	8	1			T74	1		T278	1		T422	1
auto[3221225472:3355443199]	auto[0]	150	1			T221	1		T28	2		T110	1
auto[3221225472:3355443199]	auto[1]	12	1			T74	1		T265	1		T77	1
auto[3355443200:3489660927]	auto[0]	138	1			T3	2		T14	1		T93	1
auto[3355443200:3489660927]	auto[1]	5	1			T409	1		T312	1		T424	1
auto[3489660928:3623878655]	auto[0]	139	1			T60	1		T101	1		T218	1
auto[3489660928:3623878655]	auto[1]	10	1			T64	1		T74	1		T80	1
auto[3623878656:3758096383]	auto[0]	147	1			T20	1		T59	1		T60	1
auto[3623878656:3758096383]	auto[1]	12	1			T75	1		T301	1		T268	1
auto[3758096384:3892314111]	auto[0]	129	1			T20	1		T94	1		T221	1
auto[3758096384:3892314111]	auto[1]	13	1			T100	1		T64	1		T324	1
auto[3892314112:4026531839]	auto[0]	118	1			T3	1		T28	1		T127	1
auto[3892314112:4026531839]	auto[1]	9	1			T265	1		T390	1		T424	2
auto[4026531840:4160749567]	auto[0]	117	1			T2	1		T18	1		T101	1
auto[4026531840:4160749567]	auto[1]	7	1			T324	1		T294	1		T348	1
auto[4160749568:4294967295]	auto[0]	134	1			T3	1		T93	1		T94	1
auto[4160749568:4294967295]	auto[1]	7	1			T64	1		T265	1		T278	1