Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4600

1

T1

2

T2

10

T3

8

auto[1]

2080

1

T1

2

T2

4

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	196	1			T2	2		T36	2		T100	2
auto[134217728:268435455]	198	1			T14	2		T93	2		T101	2
auto[268435456:402653183]	184	1			T36	2		T100	2		T101	2
auto[402653184:536870911]	202	1			T2	2		T46	4		T103	2
auto[536870912:671088639]	200	1			T2	2		T34	2		T45	4
auto[671088640:805306367]	240	1			T18	2		T34	2		T93	2
auto[805306368:939524095]	242	1			T14	2		T221	2		T61	2
auto[939524096:1073741823]	208	1			T3	4		T18	2		T20	2
auto[1073741824:1207959551]	216	1			T2	2		T14	2		T93	2
auto[1207959552:1342177279]	202	1			T18	2		T19	2		T221	2
auto[1342177280:1476395007]	180	1			T221	2		T59	2		T36	2
auto[1476395008:1610612735]	214	1			T28	2		T56	2		T36	2
auto[1610612736:1744830463]	188	1			T3	2		T60	2		T46	4
auto[1744830464:1879048191]	224	1			T14	2		T221	2		T56	2
auto[1879048192:2013265919]	228	1			T94	2		T28	2		T218	2
auto[2013265920:2147483647]	190	1			T4	2		T21	2		T45	2
auto[2147483648:2281701375]	242	1			T20	2		T56	2		T36	6
auto[2281701376:2415919103]	226	1			T14	2		T28	6		T127	2
auto[2415919104:2550136831]	210	1			T28	2		T60	2		T122	2
auto[2550136832:2684354559]	204	1			T14	2		T18	2		T28	2
auto[2684354560:2818572287]	220	1			T18	2		T61	2		T110	2
auto[2818572288:2952790015]	186	1			T14	2		T93	2		T59	2
auto[2952790016:3087007743]	226	1			T120	2		T20	2		T94	2
auto[3087007744:3221225471]	194	1			T3	2		T4	2		T14	2
auto[3221225472:3355443199]	248	1			T94	4		T28	2		T100	2
auto[3355443200:3489660927]	198	1			T2	2		T19	2		T28	2
auto[3489660928:3623878655]	202	1			T1	2		T14	4		T93	2
auto[3623878656:3758096383]	202	1			T60	2		T21	2		T45	2
auto[3758096384:3892314111]	208	1			T2	2		T61	2		T122	2
auto[3892314112:4026531839]	196	1			T94	2		T21	2		T230	2
auto[4026531840:4160749567]	186	1			T1	2		T14	2		T106	4
auto[4160749568:4294967295]	220	1			T2	2		T221	2		T101	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	134	1			T36	2		T100	2		T64	2
auto[0:134217727]	auto[1]	62	1			T2	2		T102	2		T108	2
auto[134217728:268435455]	auto[0]	142	1			T14	2		T93	2		T101	2
auto[134217728:268435455]	auto[1]	56	1			T104	2		T370	2		T426	2
auto[268435456:402653183]	auto[0]	136	1			T100	2		T101	2		T106	2
auto[268435456:402653183]	auto[1]	48	1			T36	2		T5	2		T77	2
auto[402653184:536870911]	auto[0]	148	1			T2	2		T46	4		T103	2
auto[402653184:536870911]	auto[1]	54	1			T268	2		T427	2		T52	2
auto[536870912:671088639]	auto[0]	132	1			T34	2		T107	2		T64	2
auto[536870912:671088639]	auto[1]	68	1			T2	2		T45	4		T48	2
auto[671088640:805306367]	auto[0]	170	1			T18	2		T34	2		T59	2
auto[671088640:805306367]	auto[1]	70	1			T93	2		T218	2		T263	2
auto[805306368:939524095]	auto[0]	176	1			T14	2		T221	2		T61	2
auto[805306368:939524095]	auto[1]	66	1			T110	2		T7	4		T426	2
auto[939524096:1073741823]	auto[0]	132	1			T3	4		T18	2		T221	2
auto[939524096:1073741823]	auto[1]	76	1			T20	2		T221	2		T48	2
auto[1073741824:1207959551]	auto[0]	154	1			T2	2		T14	2		T93	2
auto[1073741824:1207959551]	auto[1]	62	1			T119	2		T200	2		T104	2
auto[1207959552:1342177279]	auto[0]	144	1			T18	2		T19	2		T221	2
auto[1207959552:1342177279]	auto[1]	58	1			T127	2		T103	2		T316	2
auto[1342177280:1476395007]	auto[0]	134	1			T221	2		T59	2		T36	2
auto[1342177280:1476395007]	auto[1]	46	1			T291	2		T136	2		T142	2
auto[1476395008:1610612735]	auto[0]	144	1			T28	2		T56	2		T36	2
auto[1476395008:1610612735]	auto[1]	70	1			T103	2		T263	2		T287	2
auto[1610612736:1744830463]	auto[0]	126	1			T3	2		T46	2		T265	2
auto[1610612736:1744830463]	auto[1]	62	1			T60	2		T46	2		T107	2
auto[1744830464:1879048191]	auto[0]	146	1			T14	2		T221	2		T217	2
auto[1744830464:1879048191]	auto[1]	78	1			T56	2		T110	2		T103	2
auto[1879048192:2013265919]	auto[0]	146	1			T94	2		T218	2		T119	2
auto[1879048192:2013265919]	auto[1]	82	1			T28	2		T72	2		T30	2
auto[2013265920:2147483647]	auto[0]	116	1			T45	2		T199	4		T287	2
auto[2013265920:2147483647]	auto[1]	74	1			T4	2		T21	2		T30	2
auto[2147483648:2281701375]	auto[0]	190	1			T20	2		T56	2		T36	6
auto[2147483648:2281701375]	auto[1]	52	1			T103	2		T104	2		T304	2
auto[2281701376:2415919103]	auto[0]	156	1			T14	2		T28	2		T45	2
auto[2281701376:2415919103]	auto[1]	70	1			T28	4		T127	2		T69	2
auto[2415919104:2550136831]	auto[0]	146	1			T28	2		T60	2		T122	2
auto[2415919104:2550136831]	auto[1]	64	1			T119	2		T206	2		T287	2
auto[2550136832:2684354559]	auto[0]	128	1			T14	2		T18	2		T28	2
auto[2550136832:2684354559]	auto[1]	76	1			T127	2		T140	2		T319	2
auto[2684354560:2818572287]	auto[0]	148	1			T18	2		T110	2		T216	2
auto[2684354560:2818572287]	auto[1]	72	1			T61	2		T22	2		T103	4
auto[2818572288:2952790015]	auto[0]	132	1			T14	2		T59	2		T60	2
auto[2818572288:2952790015]	auto[1]	54	1			T93	2		T60	2		T200	2
auto[2952790016:3087007743]	auto[0]	158	1			T106	2		T102	2		T46	2
auto[2952790016:3087007743]	auto[1]	68	1			T120	2		T20	2		T94	2
auto[3087007744:3221225471]	auto[0]	138	1			T3	2		T4	2		T14	2
auto[3087007744:3221225471]	auto[1]	56	1			T104	2		T49	2		T252	2
auto[3221225472:3355443199]	auto[0]	174	1			T28	2		T100	2		T101	2
auto[3221225472:3355443199]	auto[1]	74	1			T94	4		T134	2		T222	2
auto[3355443200:3489660927]	auto[0]	134	1			T2	2		T19	2		T59	2
auto[3355443200:3489660927]	auto[1]	64	1			T28	2		T139	2		T103	2
auto[3489660928:3623878655]	auto[0]	130	1			T1	2		T14	2		T93	2
auto[3489660928:3623878655]	auto[1]	72	1			T14	2		T222	2		T47	2
auto[3623878656:3758096383]	auto[0]	136	1			T60	2		T102	2		T64	2
auto[3623878656:3758096383]	auto[1]	66	1			T21	2		T45	2		T46	2
auto[3758096384:3892314111]	auto[0]	138	1			T2	2		T61	2		T122	2
auto[3758096384:3892314111]	auto[1]	70	1			T230	2		T45	2		T205	2
auto[3892314112:4026531839]	auto[0]	130	1			T94	2		T230	2		T103	2
auto[3892314112:4026531839]	auto[1]	66	1			T21	2		T45	2		T103	2
auto[4026531840:4160749567]	auto[0]	136	1			T14	2		T106	2		T5	2
auto[4026531840:4160749567]	auto[1]	50	1			T1	2		T106	2		T70	2
auto[4160749568:4294967295]	auto[0]	146	1			T2	2		T221	2		T101	2
auto[4160749568:4294967295]	auto[1]	74	1			T45	2		T47	2		T78	2