| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.78 | 99.03 | 97.95 | 98.71 | 100.00 | 99.01 | 98.63 | 91.14 |
| T1007 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.1635777132 | Sep 18 07:59:46 PM UTC 24 | Sep 18 07:59:48 PM UTC 24 | 39649135 ps | ||
| T1008 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.1417886651 | Sep 18 07:59:46 PM UTC 24 | Sep 18 07:59:48 PM UTC 24 | 58595393 ps | ||
| T1009 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.3020378455 | Sep 18 07:59:52 PM UTC 24 | Sep 18 07:59:53 PM UTC 24 | 22312666 ps | ||
| T1010 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2551050134 | Sep 18 07:59:46 PM UTC 24 | Sep 18 07:59:49 PM UTC 24 | 96025810 ps | ||
| T1011 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1538432934 | Sep 18 07:59:46 PM UTC 24 | Sep 18 07:59:49 PM UTC 24 | 497047177 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.1412682031 | Sep 18 07:59:47 PM UTC 24 | Sep 18 07:59:49 PM UTC 24 | 11280760 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.3636945756 | Sep 18 07:59:48 PM UTC 24 | Sep 18 07:59:50 PM UTC 24 | 16633415 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.4061468618 | Sep 18 07:59:44 PM UTC 24 | Sep 18 07:59:50 PM UTC 24 | 159914453 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.1310185805 | Sep 18 07:59:46 PM UTC 24 | Sep 18 07:59:50 PM UTC 24 | 231290871 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.1060474767 | Sep 18 07:59:47 PM UTC 24 | Sep 18 07:59:50 PM UTC 24 | 32434536 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.625630625 | Sep 18 07:59:44 PM UTC 24 | Sep 18 07:59:50 PM UTC 24 | 237373020 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.3132619677 | Sep 18 07:59:44 PM UTC 24 | Sep 18 07:59:50 PM UTC 24 | 234119192 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1836189982 | Sep 18 07:59:47 PM UTC 24 | Sep 18 07:59:50 PM UTC 24 | 21602017 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.1187593074 | Sep 18 07:59:48 PM UTC 24 | Sep 18 07:59:53 PM UTC 24 | 397450776 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.2563924263 | Sep 18 07:59:49 PM UTC 24 | Sep 18 07:59:53 PM UTC 24 | 179723092 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_intg_err.3103338206 | Sep 18 07:59:42 PM UTC 24 | Sep 18 07:59:50 PM UTC 24 | 603673358 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2756925433 | Sep 18 07:59:46 PM UTC 24 | Sep 18 07:59:51 PM UTC 24 | 274861547 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2353740692 | Sep 18 07:59:46 PM UTC 24 | Sep 18 07:59:51 PM UTC 24 | 361773839 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.4271089292 | Sep 18 07:59:47 PM UTC 24 | Sep 18 07:59:51 PM UTC 24 | 202985796 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.4160729815 | Sep 18 07:59:46 PM UTC 24 | Sep 18 07:59:51 PM UTC 24 | 341914690 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.766704383 | Sep 18 07:59:49 PM UTC 24 | Sep 18 07:59:51 PM UTC 24 | 22888002 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.457908961 | Sep 18 07:59:43 PM UTC 24 | Sep 18 07:59:51 PM UTC 24 | 787141695 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2221437502 | Sep 18 07:59:49 PM UTC 24 | Sep 18 07:59:51 PM UTC 24 | 145297430 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3880573621 | Sep 18 07:59:42 PM UTC 24 | Sep 18 07:59:51 PM UTC 24 | 604313817 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2460156057 | Sep 18 07:59:47 PM UTC 24 | Sep 18 07:59:51 PM UTC 24 | 227651596 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3504098204 | Sep 18 07:59:44 PM UTC 24 | Sep 18 07:59:51 PM UTC 24 | 351688538 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3256596970 | Sep 18 07:59:49 PM UTC 24 | Sep 18 07:59:52 PM UTC 24 | 35435632 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.2788721005 | Sep 18 07:59:47 PM UTC 24 | Sep 18 07:59:52 PM UTC 24 | 163506395 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.2244299423 | Sep 18 07:59:50 PM UTC 24 | Sep 18 07:59:52 PM UTC 24 | 25745708 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.1232714859 | Sep 18 07:59:46 PM UTC 24 | Sep 18 07:59:52 PM UTC 24 | 126409251 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.158624699 | Sep 18 07:59:49 PM UTC 24 | Sep 18 07:59:52 PM UTC 24 | 827549868 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.1024121875 | Sep 18 07:59:50 PM UTC 24 | Sep 18 07:59:53 PM UTC 24 | 16584143 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2377911116 | Sep 18 07:59:49 PM UTC 24 | Sep 18 07:59:53 PM UTC 24 | 134612043 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.3070133298 | Sep 18 07:59:47 PM UTC 24 | Sep 18 07:59:53 PM UTC 24 | 131093016 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1677970497 | Sep 18 07:59:50 PM UTC 24 | Sep 18 07:59:53 PM UTC 24 | 37668610 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2306844319 | Sep 18 07:59:47 PM UTC 24 | Sep 18 07:59:53 PM UTC 24 | 158420381 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.4125547148 | Sep 18 07:59:50 PM UTC 24 | Sep 18 07:59:54 PM UTC 24 | 109500868 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.3648990953 | Sep 18 07:59:52 PM UTC 24 | Sep 18 07:59:54 PM UTC 24 | 38385401 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3180868549 | Sep 18 07:59:47 PM UTC 24 | Sep 18 07:59:54 PM UTC 24 | 803456389 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2149214564 | Sep 18 07:59:52 PM UTC 24 | Sep 18 07:59:54 PM UTC 24 | 136813438 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3693228256 | Sep 18 07:59:47 PM UTC 24 | Sep 18 07:59:54 PM UTC 24 | 201063314 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1947619333 | Sep 18 07:59:52 PM UTC 24 | Sep 18 07:59:54 PM UTC 24 | 85423876 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.794317087 | Sep 18 07:59:52 PM UTC 24 | Sep 18 07:59:55 PM UTC 24 | 29592557 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2989510683 | Sep 18 07:59:49 PM UTC 24 | Sep 18 07:59:55 PM UTC 24 | 93764301 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3133226015 | Sep 18 07:59:52 PM UTC 24 | Sep 18 07:59:55 PM UTC 24 | 39273565 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.4205349400 | Sep 18 07:59:50 PM UTC 24 | Sep 18 07:59:55 PM UTC 24 | 178258766 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.1282298718 | Sep 18 07:59:53 PM UTC 24 | Sep 18 07:59:55 PM UTC 24 | 26417404 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.2495033550 | Sep 18 07:59:53 PM UTC 24 | Sep 18 07:59:55 PM UTC 24 | 161303329 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.3106256299 | Sep 18 07:59:53 PM UTC 24 | Sep 18 07:59:55 PM UTC 24 | 33071177 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.4016879225 | Sep 18 07:59:53 PM UTC 24 | Sep 18 07:59:55 PM UTC 24 | 13112236 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.4264407956 | Sep 18 07:59:53 PM UTC 24 | Sep 18 07:59:55 PM UTC 24 | 15165590 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.3407179436 | Sep 18 07:59:50 PM UTC 24 | Sep 18 07:59:55 PM UTC 24 | 325271130 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.1652691302 | Sep 18 07:59:53 PM UTC 24 | Sep 18 07:59:55 PM UTC 24 | 11613943 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.1736159390 | Sep 18 07:59:53 PM UTC 24 | Sep 18 07:59:55 PM UTC 24 | 41480499 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.4107635804 | Sep 18 07:59:53 PM UTC 24 | Sep 18 07:59:55 PM UTC 24 | 26845984 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.3735932797 | Sep 18 07:59:53 PM UTC 24 | Sep 18 07:59:55 PM UTC 24 | 48679740 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.2728343603 | Sep 18 07:59:53 PM UTC 24 | Sep 18 07:59:56 PM UTC 24 | 40723805 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.655136137 | Sep 18 07:59:52 PM UTC 24 | Sep 18 07:59:56 PM UTC 24 | 374012410 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1275691542 | Sep 18 07:59:52 PM UTC 24 | Sep 18 07:59:56 PM UTC 24 | 58601453 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1528465559 | Sep 18 07:59:52 PM UTC 24 | Sep 18 07:59:56 PM UTC 24 | 270746786 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.1227185845 | Sep 18 07:59:55 PM UTC 24 | Sep 18 07:59:57 PM UTC 24 | 125742309 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.104147624 | Sep 18 07:59:55 PM UTC 24 | Sep 18 07:59:57 PM UTC 24 | 35234344 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.815597940 | Sep 18 07:59:55 PM UTC 24 | Sep 18 07:59:57 PM UTC 24 | 46175949 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.2819446797 | Sep 18 07:59:55 PM UTC 24 | Sep 18 07:59:57 PM UTC 24 | 14460084 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.1642612139 | Sep 18 07:59:55 PM UTC 24 | Sep 18 07:59:57 PM UTC 24 | 11178182 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.3867216486 | Sep 18 07:59:55 PM UTC 24 | Sep 18 07:59:57 PM UTC 24 | 36563193 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.2731522346 | Sep 18 07:59:55 PM UTC 24 | Sep 18 07:59:57 PM UTC 24 | 11068079 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.1372902256 | Sep 18 07:59:55 PM UTC 24 | Sep 18 07:59:57 PM UTC 24 | 8336012 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.3029785789 | Sep 18 07:59:55 PM UTC 24 | Sep 18 07:59:57 PM UTC 24 | 27594899 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.1577252664 | Sep 18 07:59:55 PM UTC 24 | Sep 18 07:59:57 PM UTC 24 | 43510554 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.16092939 | Sep 18 07:59:55 PM UTC 24 | Sep 18 07:59:57 PM UTC 24 | 24941206 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.2631039647 | Sep 18 07:59:55 PM UTC 24 | Sep 18 07:59:57 PM UTC 24 | 11186560 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.1895762997 | Sep 18 07:59:56 PM UTC 24 | Sep 18 07:59:58 PM UTC 24 | 27160674 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.2788274745 | Sep 18 07:59:56 PM UTC 24 | Sep 18 07:59:58 PM UTC 24 | 8961990 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.3858962010 | Sep 18 07:59:56 PM UTC 24 | Sep 18 07:59:58 PM UTC 24 | 12667212 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1017664954 | Sep 18 07:59:32 PM UTC 24 | Sep 18 07:59:58 PM UTC 24 | 903837526 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.1444962065 | Sep 18 07:59:56 PM UTC 24 | Sep 18 07:59:58 PM UTC 24 | 17803374 ps | ||
| T1080 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.1474235112 | Sep 18 07:59:56 PM UTC 24 | Sep 18 07:59:58 PM UTC 24 | 7597023 ps | ||
| T1081 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.1330931195 | Sep 18 07:59:56 PM UTC 24 | Sep 18 07:59:58 PM UTC 24 | 38480149 ps | ||
| T1082 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.3521632703 | Sep 18 07:59:56 PM UTC 24 | Sep 18 07:59:58 PM UTC 24 | 15432064 ps | ||
| T1083 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.3797046419 | Sep 18 07:59:56 PM UTC 24 | Sep 18 07:59:58 PM UTC 24 | 37604516 ps | ||
| T1084 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.162421353 | Sep 18 07:59:50 PM UTC 24 | Sep 18 08:00:00 PM UTC 24 | 1290682629 ps | ||
| T1085 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.556148891 | Sep 18 07:59:52 PM UTC 24 | Sep 18 08:00:00 PM UTC 24 | 208399223 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.2263004468 | Sep 18 07:59:52 PM UTC 24 | Sep 18 08:00:02 PM UTC 24 | 437325376 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.1656394334 | Sep 18 07:59:52 PM UTC 24 | Sep 18 08:00:03 PM UTC 24 | 289635463 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/0.keymgr_hwsw_invalid_input.1261657160 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 32148141 ps |
| CPU time | 2.49 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:54:25 PM UTC 24 |
| Peak memory | 217392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261657160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1261657160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all.3569554711 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 6153047873 ps |
| CPU time | 22.98 seconds |
| Started | Sep 18 07:54:34 PM UTC 24 |
| Finished | Sep 18 07:54:59 PM UTC 24 |
| Peak memory | 227692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569554711 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3569554711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all.2727262285 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 9815695796 ps |
| CPU time | 61.1 seconds |
| Started | Sep 18 07:54:26 PM UTC 24 |
| Finished | Sep 18 07:55:29 PM UTC 24 |
| Peak memory | 227696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727262285 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2727262285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/0.keymgr_custom_cm.1714601227 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 400205725 ps |
| CPU time | 3.89 seconds |
| Started | Sep 18 07:54:26 PM UTC 24 |
| Finished | Sep 18 07:54:31 PM UTC 24 |
| Peak memory | 217480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714601227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1714601227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all_with_rand_reset.3268086454 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 616574459 ps |
| CPU time | 21.72 seconds |
| Started | Sep 18 07:55:19 PM UTC 24 |
| Finished | Sep 18 07:55:42 PM UTC 24 |
| Peak memory | 231672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3268086454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr _stress_all_with_rand_reset.3268086454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/0.keymgr_sec_cm.160840626 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 826572912 ps |
| CPU time | 11.96 seconds |
| Started | Sep 18 07:54:26 PM UTC 24 |
| Finished | Sep 18 07:54:39 PM UTC 24 |
| Peak memory | 259320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160840626 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.160840626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/1.keymgr_stress_all_with_rand_reset.1910142521 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 875445624 ps |
| CPU time | 11.49 seconds |
| Started | Sep 18 07:54:27 PM UTC 24 |
| Finished | Sep 18 07:54:47 PM UTC 24 |
| Peak memory | 231664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1910142521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr _stress_all_with_rand_reset.1910142521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/11.keymgr_custom_cm.104378068 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 211825921 ps |
| CPU time | 3.77 seconds |
| Started | Sep 18 07:55:32 PM UTC 24 |
| Finished | Sep 18 07:55:37 PM UTC 24 |
| Peak memory | 230692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104378068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.104378068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/3.keymgr_cfg_regwen.2900870689 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 490736376 ps |
| CPU time | 10.8 seconds |
| Started | Sep 18 07:54:39 PM UTC 24 |
| Finished | Sep 18 07:54:51 PM UTC 24 |
| Peak memory | 225260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900870689 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2900870689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all_with_rand_reset.4171757985 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 122651302 ps |
| CPU time | 6.84 seconds |
| Started | Sep 18 07:54:26 PM UTC 24 |
| Finished | Sep 18 07:54:34 PM UTC 24 |
| Peak memory | 230052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4171757985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr _stress_all_with_rand_reset.4171757985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2603681850 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 820881041 ps |
| CPU time | 6.33 seconds |
| Started | Sep 18 07:59:16 PM UTC 24 |
| Finished | Sep 18 07:59:24 PM UTC 24 |
| Peak memory | 225792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603681850 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors_with_csr_rw.2603681850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all.1310431793 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1332633300 ps |
| CPU time | 43.59 seconds |
| Started | Sep 18 07:55:19 PM UTC 24 |
| Finished | Sep 18 07:56:04 PM UTC 24 |
| Peak memory | 227564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310431793 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1310431793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/0.keymgr_cfg_regwen.127740098 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1151957783 ps |
| CPU time | 47.29 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:55:10 PM UTC 24 |
| Peak memory | 225544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127740098 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.127740098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/1.keymgr_cfg_regwen.3729398246 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 405036256 ps |
| CPU time | 8.59 seconds |
| Started | Sep 18 07:54:26 PM UTC 24 |
| Finished | Sep 18 07:54:36 PM UTC 24 |
| Peak memory | 225592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729398246 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3729398246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/0.keymgr_kmac_rsp_err.1007443853 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 189291468 ps |
| CPU time | 2.35 seconds |
| Started | Sep 18 07:54:22 PM UTC 24 |
| Finished | Sep 18 07:54:25 PM UTC 24 |
| Peak memory | 213100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007443853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1007443853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/2.keymgr_cfg_regwen.503573532 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 1205028286 ps |
| CPU time | 54.59 seconds |
| Started | Sep 18 07:54:32 PM UTC 24 |
| Finished | Sep 18 07:55:29 PM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503573532 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.503573532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/3.keymgr_kmac_rsp_err.3981850653 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 68102552 ps |
| CPU time | 4.9 seconds |
| Started | Sep 18 07:54:39 PM UTC 24 |
| Finished | Sep 18 07:54:45 PM UTC 24 |
| Peak memory | 231492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981850653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3981850653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/23.keymgr_hwsw_invalid_input.50823501 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 391288388 ps |
| CPU time | 4.84 seconds |
| Started | Sep 18 07:56:49 PM UTC 24 |
| Finished | Sep 18 07:56:55 PM UTC 24 |
| Peak memory | 230928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50823501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.50823501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/23.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/4.keymgr_stress_all.3938640668 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 2770971070 ps |
| CPU time | 38.81 seconds |
| Started | Sep 18 07:54:49 PM UTC 24 |
| Finished | Sep 18 07:55:29 PM UTC 24 |
| Peak memory | 225772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938640668 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3938640668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/19.keymgr_cfg_regwen.2258453883 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 5701053155 ps |
| CPU time | 72.09 seconds |
| Started | Sep 18 07:56:22 PM UTC 24 |
| Finished | Sep 18 07:57:36 PM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258453883 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2258453883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/5.keymgr_custom_cm.144825651 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 207980615 ps |
| CPU time | 3.67 seconds |
| Started | Sep 18 07:54:54 PM UTC 24 |
| Finished | Sep 18 07:54:59 PM UTC 24 |
| Peak memory | 223820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144825651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.144825651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/39.keymgr_cfg_regwen.2705636654 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 863451326 ps |
| CPU time | 42.73 seconds |
| Started | Sep 18 07:58:17 PM UTC 24 |
| Finished | Sep 18 07:59:02 PM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705636654 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2705636654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/39.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/3.keymgr_stress_all.3057054109 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 3933911523 ps |
| CPU time | 28.43 seconds |
| Started | Sep 18 07:54:42 PM UTC 24 |
| Finished | Sep 18 07:55:11 PM UTC 24 |
| Peak memory | 227628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057054109 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3057054109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all_with_rand_reset.3161173184 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 242947537 ps |
| CPU time | 14.94 seconds |
| Started | Sep 18 07:58:38 PM UTC 24 |
| Finished | Sep 18 07:58:54 PM UTC 24 |
| Peak memory | 231980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3161173184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymg r_stress_all_with_rand_reset.3161173184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/42.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/3.keymgr_custom_cm.3901228168 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 306963557 ps |
| CPU time | 8.14 seconds |
| Started | Sep 18 07:54:39 PM UTC 24 |
| Finished | Sep 18 07:54:49 PM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901228168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3901228168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/5.keymgr_cfg_regwen.1356438237 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 9013519214 ps |
| CPU time | 117.18 seconds |
| Started | Sep 18 07:54:53 PM UTC 24 |
| Finished | Sep 18 07:56:52 PM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356438237 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1356438237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all.2341198155 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 6809228366 ps |
| CPU time | 47.77 seconds |
| Started | Sep 18 07:55:03 PM UTC 24 |
| Finished | Sep 18 07:55:52 PM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341198155 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2341198155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/6.keymgr_custom_cm.3347937246 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 98790790 ps |
| CPU time | 3.74 seconds |
| Started | Sep 18 07:55:01 PM UTC 24 |
| Finished | Sep 18 07:55:06 PM UTC 24 |
| Peak memory | 225528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347937246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3347937246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/4.keymgr_custom_cm.1444072472 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 504633642 ps |
| CPU time | 4.67 seconds |
| Started | Sep 18 07:54:48 PM UTC 24 |
| Finished | Sep 18 07:54:53 PM UTC 24 |
| Peak memory | 231688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444072472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1444072472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/4.keymgr_stress_all_with_rand_reset.2037825997 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 380223201 ps |
| CPU time | 15.95 seconds |
| Started | Sep 18 07:54:49 PM UTC 24 |
| Finished | Sep 18 07:55:06 PM UTC 24 |
| Peak memory | 231688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2037825997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr _stress_all_with_rand_reset.2037825997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2898828500 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 311295667 ps |
| CPU time | 7.72 seconds |
| Started | Sep 18 07:59:28 PM UTC 24 |
| Finished | Sep 18 07:59:36 PM UTC 24 |
| Peak memory | 225960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898828500 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors_with_csr_rw.2898828500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/22.keymgr_cfg_regwen.2773533246 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2711038638 ps |
| CPU time | 40.29 seconds |
| Started | Sep 18 07:56:44 PM UTC 24 |
| Finished | Sep 18 07:57:26 PM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773533246 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2773533246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/22.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/5.keymgr_sync_async_fault_cross.1677106561 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 183149968 ps |
| CPU time | 3.63 seconds |
| Started | Sep 18 07:54:55 PM UTC 24 |
| Finished | Sep 18 07:55:00 PM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677106561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1677106561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/4.keymgr_hwsw_invalid_input.1632438120 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 70406102 ps |
| CPU time | 3.53 seconds |
| Started | Sep 18 07:54:45 PM UTC 24 |
| Finished | Sep 18 07:54:50 PM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632438120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1632438120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/16.keymgr_hwsw_invalid_input.1485710392 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 458314054 ps |
| CPU time | 5.45 seconds |
| Started | Sep 18 07:56:07 PM UTC 24 |
| Finished | Sep 18 07:56:14 PM UTC 24 |
| Peak memory | 217248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485710392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1485710392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/26.keymgr_cfg_regwen.2637577112 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 819709811 ps |
| CPU time | 12.28 seconds |
| Started | Sep 18 07:57:07 PM UTC 24 |
| Finished | Sep 18 07:57:20 PM UTC 24 |
| Peak memory | 225788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637577112 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2637577112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/26.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.3132619677 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 234119192 ps |
| CPU time | 4.66 seconds |
| Started | Sep 18 07:59:44 PM UTC 24 |
| Finished | Sep 18 07:59:50 PM UTC 24 |
| Peak memory | 225668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132619677 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err.3132619677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/27.keymgr_stress_all.3004153582 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 4766385149 ps |
| CPU time | 59.95 seconds |
| Started | Sep 18 07:57:15 PM UTC 24 |
| Finished | Sep 18 07:58:17 PM UTC 24 |
| Peak memory | 231604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004153582 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3004153582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/27.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_aes.191018738 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 63836153 ps |
| CPU time | 4.18 seconds |
| Started | Sep 18 07:54:51 PM UTC 24 |
| Finished | Sep 18 07:54:57 PM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191018738 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.191018738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/0.keymgr_alert_test.262908854 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11827502 ps |
| CPU time | 0.95 seconds |
| Started | Sep 18 07:54:26 PM UTC 24 |
| Finished | Sep 18 07:54:28 PM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262908854 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.262908854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_otbn.2490306813 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 70463057 ps |
| CPU time | 4.17 seconds |
| Started | Sep 18 07:54:26 PM UTC 24 |
| Finished | Sep 18 07:54:32 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490306813 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2490306813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/10.keymgr_cfg_regwen.709078636 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 72555777 ps |
| CPU time | 4.18 seconds |
| Started | Sep 18 07:55:26 PM UTC 24 |
| Finished | Sep 18 07:55:31 PM UTC 24 |
| Peak memory | 223468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709078636 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.709078636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all_with_rand_reset.2414248765 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 417796654 ps |
| CPU time | 11.82 seconds |
| Started | Sep 18 07:54:37 PM UTC 24 |
| Finished | Sep 18 07:54:50 PM UTC 24 |
| Peak memory | 231592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2414248765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr _stress_all_with_rand_reset.2414248765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/9.keymgr_kmac_rsp_err.2562821475 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 307471387 ps |
| CPU time | 4.68 seconds |
| Started | Sep 18 07:55:21 PM UTC 24 |
| Finished | Sep 18 07:55:27 PM UTC 24 |
| Peak memory | 223416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562821475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2562821475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/16.keymgr_cfg_regwen.1983487477 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 1676681461 ps |
| CPU time | 85.03 seconds |
| Started | Sep 18 07:56:07 PM UTC 24 |
| Finished | Sep 18 07:57:35 PM UTC 24 |
| Peak memory | 231544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983487477 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1983487477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/22.keymgr_stress_all.4040320383 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 1818789998 ps |
| CPU time | 19.97 seconds |
| Started | Sep 18 07:56:44 PM UTC 24 |
| Finished | Sep 18 07:57:06 PM UTC 24 |
| Peak memory | 230300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040320383 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.4040320383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/22.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all.4038693872 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 12176020692 ps |
| CPU time | 77.25 seconds |
| Started | Sep 18 07:54:56 PM UTC 24 |
| Finished | Sep 18 07:56:15 PM UTC 24 |
| Peak memory | 225580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038693872 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.4038693872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_intg_err.1492474280 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 403817428 ps |
| CPU time | 4.62 seconds |
| Started | Sep 18 07:59:40 PM UTC 24 |
| Finished | Sep 18 07:59:45 PM UTC 24 |
| Peak memory | 225396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492474280 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.1492474280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/36.keymgr_custom_cm.2323489786 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 68060800 ps |
| CPU time | 4.47 seconds |
| Started | Sep 18 07:58:02 PM UTC 24 |
| Finished | Sep 18 07:58:08 PM UTC 24 |
| Peak memory | 225684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323489786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2323489786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/36.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/38.keymgr_custom_cm.3978077201 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 641649490 ps |
| CPU time | 3.37 seconds |
| Started | Sep 18 07:58:12 PM UTC 24 |
| Finished | Sep 18 07:58:17 PM UTC 24 |
| Peak memory | 231688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978077201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3978077201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/38.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/41.keymgr_custom_cm.3327865606 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 445948885 ps |
| CPU time | 3.5 seconds |
| Started | Sep 18 07:58:31 PM UTC 24 |
| Finished | Sep 18 07:58:36 PM UTC 24 |
| Peak memory | 225548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327865606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3327865606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/41.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all.1433034631 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 7751720433 ps |
| CPU time | 36.28 seconds |
| Started | Sep 18 07:56:20 PM UTC 24 |
| Finished | Sep 18 07:56:58 PM UTC 24 |
| Peak memory | 231588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433034631 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1433034631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/11.keymgr_lc_disable.1646951204 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 66659567 ps |
| CPU time | 6.62 seconds |
| Started | Sep 18 07:55:32 PM UTC 24 |
| Finished | Sep 18 07:55:40 PM UTC 24 |
| Peak memory | 219324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646951204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1646951204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/12.keymgr_hwsw_invalid_input.3801872471 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 228801472 ps |
| CPU time | 3.56 seconds |
| Started | Sep 18 07:55:41 PM UTC 24 |
| Finished | Sep 18 07:55:46 PM UTC 24 |
| Peak memory | 223420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801872471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3801872471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/14.keymgr_hwsw_invalid_input.2415988631 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 38895614 ps |
| CPU time | 3.49 seconds |
| Started | Sep 18 07:55:51 PM UTC 24 |
| Finished | Sep 18 07:55:56 PM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415988631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2415988631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/12.keymgr_custom_cm.1571083393 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 233629905 ps |
| CPU time | 2.93 seconds |
| Started | Sep 18 07:55:41 PM UTC 24 |
| Finished | Sep 18 07:55:45 PM UTC 24 |
| Peak memory | 217672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571083393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1571083393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3541217886 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 54158959 ps |
| CPU time | 2.21 seconds |
| Started | Sep 18 07:59:16 PM UTC 24 |
| Finished | Sep 18 07:59:20 PM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541217886 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors.3541217886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.1656394334 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 289635463 ps |
| CPU time | 10.45 seconds |
| Started | Sep 18 07:59:52 PM UTC 24 |
| Finished | Sep 18 08:00:03 PM UTC 24 |
| Peak memory | 225368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656394334 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err.1656394334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/34.keymgr_custom_cm.1384576113 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 113740008 ps |
| CPU time | 3.24 seconds |
| Started | Sep 18 07:57:51 PM UTC 24 |
| Finished | Sep 18 07:57:56 PM UTC 24 |
| Peak memory | 231556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384576113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1384576113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/34.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/1.keymgr_lc_disable.3086227506 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 254416425 ps |
| CPU time | 3.09 seconds |
| Started | Sep 18 07:54:26 PM UTC 24 |
| Finished | Sep 18 07:54:31 PM UTC 24 |
| Peak memory | 227496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086227506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3086227506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/1.keymgr_stress_all.3877118850 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 68432380126 ps |
| CPU time | 427.9 seconds |
| Started | Sep 18 07:54:27 PM UTC 24 |
| Finished | Sep 18 08:01:40 PM UTC 24 |
| Peak memory | 231936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877118850 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3877118850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/1.keymgr_sync_async_fault_cross.2194151452 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 60116841 ps |
| CPU time | 1.96 seconds |
| Started | Sep 18 07:54:27 PM UTC 24 |
| Finished | Sep 18 07:54:37 PM UTC 24 |
| Peak memory | 215420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194151452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2194151452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/27.keymgr_cfg_regwen.3155152166 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 131484877 ps |
| CPU time | 3.37 seconds |
| Started | Sep 18 07:57:13 PM UTC 24 |
| Finished | Sep 18 07:57:17 PM UTC 24 |
| Peak memory | 225788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155152166 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3155152166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/27.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/30.keymgr_hwsw_invalid_input.1014672184 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 49785204 ps |
| CPU time | 2.76 seconds |
| Started | Sep 18 07:57:31 PM UTC 24 |
| Finished | Sep 18 07:57:35 PM UTC 24 |
| Peak memory | 223744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014672184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1014672184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/30.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/35.keymgr_cfg_regwen.327145440 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 230749443 ps |
| CPU time | 5.4 seconds |
| Started | Sep 18 07:57:57 PM UTC 24 |
| Finished | Sep 18 07:58:03 PM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327145440 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.327145440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/35.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/35.keymgr_stress_all.3234732995 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 19087516555 ps |
| CPU time | 512.87 seconds |
| Started | Sep 18 07:57:58 PM UTC 24 |
| Finished | Sep 18 08:06:37 PM UTC 24 |
| Peak memory | 231672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234732995 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3234732995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/35.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/41.keymgr_hwsw_invalid_input.3826344739 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 163499735 ps |
| CPU time | 4.13 seconds |
| Started | Sep 18 07:58:30 PM UTC 24 |
| Finished | Sep 18 07:58:35 PM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826344739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3826344739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/41.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all_with_rand_reset.3607671808 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 2450953555 ps |
| CPU time | 23.16 seconds |
| Started | Sep 18 07:59:08 PM UTC 24 |
| Finished | Sep 18 07:59:33 PM UTC 24 |
| Peak memory | 230560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3607671808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymg r_stress_all_with_rand_reset.3607671808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/47.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all_with_rand_reset.2689726680 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1160839338 ps |
| CPU time | 22.55 seconds |
| Started | Sep 18 07:55:03 PM UTC 24 |
| Finished | Sep 18 07:55:27 PM UTC 24 |
| Peak memory | 231692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2689726680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr _stress_all_with_rand_reset.2689726680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_kmac.2664277793 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 52383437 ps |
| CPU time | 2.81 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:54:25 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664277793 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2664277793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/19.keymgr_custom_cm.3170264352 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 372508553 ps |
| CPU time | 2.62 seconds |
| Started | Sep 18 07:56:25 PM UTC 24 |
| Finished | Sep 18 07:56:29 PM UTC 24 |
| Peak memory | 225552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170264352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3170264352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/27.keymgr_custom_cm.2772576217 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 176188828 ps |
| CPU time | 7.6 seconds |
| Started | Sep 18 07:57:14 PM UTC 24 |
| Finished | Sep 18 07:57:23 PM UTC 24 |
| Peak memory | 227792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772576217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2772576217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/27.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/31.keymgr_custom_cm.2900379779 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 335279414 ps |
| CPU time | 4.24 seconds |
| Started | Sep 18 07:57:36 PM UTC 24 |
| Finished | Sep 18 07:57:41 PM UTC 24 |
| Peak memory | 231992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900379779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2900379779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/31.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/32.keymgr_custom_cm.1481323989 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 208242995 ps |
| CPU time | 3.22 seconds |
| Started | Sep 18 07:57:42 PM UTC 24 |
| Finished | Sep 18 07:57:46 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481323989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1481323989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/32.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/11.keymgr_cfg_regwen.3718402224 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 169987242 ps |
| CPU time | 10.12 seconds |
| Started | Sep 18 07:55:31 PM UTC 24 |
| Finished | Sep 18 07:55:42 PM UTC 24 |
| Peak memory | 231620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718402224 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3718402224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all_with_rand_reset.2563707193 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 2915209774 ps |
| CPU time | 10.93 seconds |
| Started | Sep 18 07:56:16 PM UTC 24 |
| Finished | Sep 18 07:56:28 PM UTC 24 |
| Peak memory | 231736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2563707193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymg r_stress_all_with_rand_reset.2563707193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/25.keymgr_stress_all.4085647271 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 21393696093 ps |
| CPU time | 71.27 seconds |
| Started | Sep 18 07:57:02 PM UTC 24 |
| Finished | Sep 18 07:58:15 PM UTC 24 |
| Peak memory | 225644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085647271 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.4085647271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/25.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/31.keymgr_kmac_rsp_err.4184391628 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 58933999 ps |
| CPU time | 3.35 seconds |
| Started | Sep 18 07:57:36 PM UTC 24 |
| Finished | Sep 18 07:57:40 PM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184391628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.4184391628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/31.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/43.keymgr_kmac_rsp_err.2289513398 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 111584444 ps |
| CPU time | 3.56 seconds |
| Started | Sep 18 07:58:43 PM UTC 24 |
| Finished | Sep 18 07:58:47 PM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289513398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2289513398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/43.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/6.keymgr_sw_invalid_input.2380608055 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 678870648 ps |
| CPU time | 5.49 seconds |
| Started | Sep 18 07:55:01 PM UTC 24 |
| Finished | Sep 18 07:55:07 PM UTC 24 |
| Peak memory | 227516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380608055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2380608055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_intg_err.4223233437 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 751068293 ps |
| CPU time | 4.04 seconds |
| Started | Sep 18 07:59:16 PM UTC 24 |
| Finished | Sep 18 07:59:22 PM UTC 24 |
| Peak memory | 225432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223233437 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.4223233437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_intg_err.2406401297 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 316211907 ps |
| CPU time | 8.97 seconds |
| Started | Sep 18 07:59:24 PM UTC 24 |
| Finished | Sep 18 07:59:34 PM UTC 24 |
| Peak memory | 225364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406401297 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.2406401297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_intg_err.2847771135 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 142818656 ps |
| CPU time | 4.71 seconds |
| Started | Sep 18 07:59:41 PM UTC 24 |
| Finished | Sep 18 07:59:47 PM UTC 24 |
| Peak memory | 225440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847771135 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err.2847771135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_intg_err.3103338206 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 603673358 ps |
| CPU time | 6.88 seconds |
| Started | Sep 18 07:59:42 PM UTC 24 |
| Finished | Sep 18 07:59:50 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103338206 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err.3103338206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.1232714859 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 126409251 ps |
| CPU time | 5.28 seconds |
| Started | Sep 18 07:59:46 PM UTC 24 |
| Finished | Sep 18 07:59:52 PM UTC 24 |
| Peak memory | 225684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232714859 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err.1232714859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_intg_err.905196996 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 186965647 ps |
| CPU time | 4.15 seconds |
| Started | Sep 18 07:59:24 PM UTC 24 |
| Finished | Sep 18 07:59:30 PM UTC 24 |
| Peak memory | 215120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905196996 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.905196996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/10.keymgr_hwsw_invalid_input.3424512735 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 280025349 ps |
| CPU time | 8.71 seconds |
| Started | Sep 18 07:55:27 PM UTC 24 |
| Finished | Sep 18 07:55:37 PM UTC 24 |
| Peak memory | 231672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424512735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3424512735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_otbn.3705117497 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 94225240 ps |
| CPU time | 2.94 seconds |
| Started | Sep 18 07:55:26 PM UTC 24 |
| Finished | Sep 18 07:55:30 PM UTC 24 |
| Peak memory | 217352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705117497 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3705117497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/10.keymgr_sync_async_fault_cross.3472804493 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 2543669895 ps |
| CPU time | 7.03 seconds |
| Started | Sep 18 07:55:28 PM UTC 24 |
| Finished | Sep 18 07:55:36 PM UTC 24 |
| Peak memory | 219368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472804493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3472804493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/11.keymgr_hwsw_invalid_input.3978539430 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 159335308 ps |
| CPU time | 6.75 seconds |
| Started | Sep 18 07:55:32 PM UTC 24 |
| Finished | Sep 18 07:55:40 PM UTC 24 |
| Peak memory | 229652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978539430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3978539430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/12.keymgr_stress_all_with_rand_reset.2581191303 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 939293370 ps |
| CPU time | 9.28 seconds |
| Started | Sep 18 07:55:41 PM UTC 24 |
| Finished | Sep 18 07:55:52 PM UTC 24 |
| Peak memory | 231860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2581191303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymg r_stress_all_with_rand_reset.2581191303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all.3610063939 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 1761352329 ps |
| CPU time | 41.52 seconds |
| Started | Sep 18 07:55:53 PM UTC 24 |
| Finished | Sep 18 07:56:36 PM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610063939 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3610063939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_protect.2234659023 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 64787194 ps |
| CPU time | 4.44 seconds |
| Started | Sep 18 07:55:57 PM UTC 24 |
| Finished | Sep 18 07:56:03 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234659023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2234659023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/17.keymgr_cfg_regwen.3570104841 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 50854244 ps |
| CPU time | 3.74 seconds |
| Started | Sep 18 07:56:12 PM UTC 24 |
| Finished | Sep 18 07:56:17 PM UTC 24 |
| Peak memory | 225596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570104841 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3570104841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/17.keymgr_direct_to_disabled.2840151054 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 295119335 ps |
| CPU time | 5.33 seconds |
| Started | Sep 18 07:56:12 PM UTC 24 |
| Finished | Sep 18 07:56:19 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840151054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2840151054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/18.keymgr_kmac_rsp_err.3832900226 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 52054356 ps |
| CPU time | 3.83 seconds |
| Started | Sep 18 07:56:20 PM UTC 24 |
| Finished | Sep 18 07:56:25 PM UTC 24 |
| Peak memory | 223500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832900226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3832900226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/20.keymgr_lc_disable.580856289 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 60571888 ps |
| CPU time | 4.4 seconds |
| Started | Sep 18 07:56:34 PM UTC 24 |
| Finished | Sep 18 07:56:39 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580856289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.580856289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/20.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/21.keymgr_stress_all.3878281583 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 282806458 ps |
| CPU time | 9.98 seconds |
| Started | Sep 18 07:56:39 PM UTC 24 |
| Finished | Sep 18 07:56:50 PM UTC 24 |
| Peak memory | 225708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878281583 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3878281583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/21.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/24.keymgr_kmac_rsp_err.3587450185 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 178174853 ps |
| CPU time | 4.79 seconds |
| Started | Sep 18 07:57:00 PM UTC 24 |
| Finished | Sep 18 07:57:06 PM UTC 24 |
| Peak memory | 229780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587450185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3587450185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/24.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/28.keymgr_cfg_regwen.4182116558 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 175123867 ps |
| CPU time | 10.31 seconds |
| Started | Sep 18 07:57:18 PM UTC 24 |
| Finished | Sep 18 07:57:29 PM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182116558 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.4182116558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/28.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/29.keymgr_cfg_regwen.1246266703 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 137746330 ps |
| CPU time | 8.16 seconds |
| Started | Sep 18 07:57:24 PM UTC 24 |
| Finished | Sep 18 07:57:34 PM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246266703 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1246266703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/29.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/30.keymgr_cfg_regwen.62820200 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 74679529 ps |
| CPU time | 3.78 seconds |
| Started | Sep 18 07:57:29 PM UTC 24 |
| Finished | Sep 18 07:57:34 PM UTC 24 |
| Peak memory | 223552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62820200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keym gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.62820200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/30.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/36.keymgr_cfg_regwen.3334455721 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 233650479 ps |
| CPU time | 5.02 seconds |
| Started | Sep 18 07:58:01 PM UTC 24 |
| Finished | Sep 18 07:58:07 PM UTC 24 |
| Peak memory | 231684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334455721 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3334455721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/36.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/37.keymgr_cfg_regwen.727989972 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 45840202 ps |
| CPU time | 3.87 seconds |
| Started | Sep 18 07:58:06 PM UTC 24 |
| Finished | Sep 18 07:58:11 PM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727989972 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.727989972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/37.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_protect.3053613988 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 141389343 ps |
| CPU time | 7.24 seconds |
| Started | Sep 18 07:55:08 PM UTC 24 |
| Finished | Sep 18 07:55:17 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053613988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3053613988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/8.keymgr_hwsw_invalid_input.3045501789 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2656245698 ps |
| CPU time | 30.88 seconds |
| Started | Sep 18 07:55:18 PM UTC 24 |
| Finished | Sep 18 07:55:50 PM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045501789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3045501789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_aliasing.522731648 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 7069854662 ps |
| CPU time | 15.42 seconds |
| Started | Sep 18 07:59:22 PM UTC 24 |
| Finished | Sep 18 07:59:39 PM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522731648 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.522731648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_bit_bash.153127995 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 268875386 ps |
| CPU time | 11.37 seconds |
| Started | Sep 18 07:59:22 PM UTC 24 |
| Finished | Sep 18 07:59:35 PM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153127995 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.153127995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1040419991 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 50956623 ps |
| CPU time | 1.25 seconds |
| Started | Sep 18 07:59:22 PM UTC 24 |
| Finished | Sep 18 07:59:24 PM UTC 24 |
| Peak memory | 215324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040419991 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1040419991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1889870824 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 114850916 ps |
| CPU time | 1.33 seconds |
| Started | Sep 18 07:59:22 PM UTC 24 |
| Finished | Sep 18 07:59:25 PM UTC 24 |
| Peak memory | 225360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1889870824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_mem_rw_w ith_rand_reset.1889870824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_rw.1825713508 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 21712136 ps |
| CPU time | 1.11 seconds |
| Started | Sep 18 07:59:22 PM UTC 24 |
| Finished | Sep 18 07:59:24 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825713508 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1825713508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_intr_test.2264768315 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 18980830 ps |
| CPU time | 0.94 seconds |
| Started | Sep 18 07:59:22 PM UTC 24 |
| Finished | Sep 18 07:59:24 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264768315 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2264768315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3376670887 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 123606470 ps |
| CPU time | 4.83 seconds |
| Started | Sep 18 07:59:22 PM UTC 24 |
| Finished | Sep 18 07:59:28 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376670887 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_same_csr_outstanding.3376670887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_errors.3524199398 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 68507438 ps |
| CPU time | 2.63 seconds |
| Started | Sep 18 07:59:16 PM UTC 24 |
| Finished | Sep 18 07:59:20 PM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524199398 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3524199398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_aliasing.1981936106 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 1081012261 ps |
| CPU time | 5.69 seconds |
| Started | Sep 18 07:59:24 PM UTC 24 |
| Finished | Sep 18 07:59:31 PM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981936106 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1981936106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_bit_bash.625402192 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 1323597339 ps |
| CPU time | 8.65 seconds |
| Started | Sep 18 07:59:24 PM UTC 24 |
| Finished | Sep 18 07:59:34 PM UTC 24 |
| Peak memory | 215132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625402192 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.625402192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2046162429 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 17580286 ps |
| CPU time | 1.16 seconds |
| Started | Sep 18 07:59:24 PM UTC 24 |
| Finished | Sep 18 07:59:26 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046162429 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2046162429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3102345032 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 26760412 ps |
| CPU time | 2.09 seconds |
| Started | Sep 18 07:59:24 PM UTC 24 |
| Finished | Sep 18 07:59:27 PM UTC 24 |
| Peak memory | 225564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3102345032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_mem_rw_w ith_rand_reset.3102345032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_rw.1334703137 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 13258068 ps |
| CPU time | 1.49 seconds |
| Started | Sep 18 07:59:24 PM UTC 24 |
| Finished | Sep 18 07:59:26 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334703137 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1334703137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_intr_test.1962423009 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 10717531 ps |
| CPU time | 0.92 seconds |
| Started | Sep 18 07:59:24 PM UTC 24 |
| Finished | Sep 18 07:59:26 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962423009 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1962423009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.281096400 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 23538929 ps |
| CPU time | 2.12 seconds |
| Started | Sep 18 07:59:24 PM UTC 24 |
| Finished | Sep 18 07:59:27 PM UTC 24 |
| Peak memory | 215132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281096400 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_same_csr_outstanding.281096400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2236295958 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 198692216 ps |
| CPU time | 4.87 seconds |
| Started | Sep 18 07:59:23 PM UTC 24 |
| Finished | Sep 18 07:59:30 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236295958 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors.2236295958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.600503072 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 762107673 ps |
| CPU time | 6.01 seconds |
| Started | Sep 18 07:59:23 PM UTC 24 |
| Finished | Sep 18 07:59:31 PM UTC 24 |
| Peak memory | 225760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600503072 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors_with_csr_rw.600503072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_errors.2821126612 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 159093207 ps |
| CPU time | 2.85 seconds |
| Started | Sep 18 07:59:24 PM UTC 24 |
| Finished | Sep 18 07:59:28 PM UTC 24 |
| Peak memory | 225436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821126612 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2821126612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3521261683 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 31719040 ps |
| CPU time | 2.39 seconds |
| Started | Sep 18 07:59:41 PM UTC 24 |
| Finished | Sep 18 07:59:45 PM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3521261683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_mem_rw_ with_rand_reset.3521261683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_rw.2390594090 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 63460693 ps |
| CPU time | 1.1 seconds |
| Started | Sep 18 07:59:41 PM UTC 24 |
| Finished | Sep 18 07:59:43 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390594090 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2390594090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_intr_test.3421294495 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 77547639 ps |
| CPU time | 0.98 seconds |
| Started | Sep 18 07:59:41 PM UTC 24 |
| Finished | Sep 18 07:59:43 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421294495 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3421294495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2228033199 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 41124350 ps |
| CPU time | 1.97 seconds |
| Started | Sep 18 07:59:41 PM UTC 24 |
| Finished | Sep 18 07:59:44 PM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228033199 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_same_csr_outstanding.2228033199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2109485815 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 172054628 ps |
| CPU time | 5.23 seconds |
| Started | Sep 18 07:59:40 PM UTC 24 |
| Finished | Sep 18 07:59:46 PM UTC 24 |
| Peak memory | 225708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109485815 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors.2109485815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3836318831 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 113342226 ps |
| CPU time | 3.87 seconds |
| Started | Sep 18 07:59:40 PM UTC 24 |
| Finished | Sep 18 07:59:45 PM UTC 24 |
| Peak memory | 225896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836318831 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors_with_csr_rw.3836318831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_errors.3928424390 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 29446762 ps |
| CPU time | 1.6 seconds |
| Started | Sep 18 07:59:41 PM UTC 24 |
| Finished | Sep 18 07:59:44 PM UTC 24 |
| Peak memory | 223044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928424390 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3928424390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3792839246 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 55157148 ps |
| CPU time | 1.74 seconds |
| Started | Sep 18 07:59:43 PM UTC 24 |
| Finished | Sep 18 07:59:46 PM UTC 24 |
| Peak memory | 223040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3792839246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_mem_rw_ with_rand_reset.3792839246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_rw.2989733824 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 19073402 ps |
| CPU time | 1.36 seconds |
| Started | Sep 18 07:59:43 PM UTC 24 |
| Finished | Sep 18 07:59:45 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989733824 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2989733824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_intr_test.3859370345 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 34358631 ps |
| CPU time | 1.07 seconds |
| Started | Sep 18 07:59:43 PM UTC 24 |
| Finished | Sep 18 07:59:45 PM UTC 24 |
| Peak memory | 212336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859370345 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3859370345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.109004552 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 55302524 ps |
| CPU time | 2.54 seconds |
| Started | Sep 18 07:59:43 PM UTC 24 |
| Finished | Sep 18 07:59:46 PM UTC 24 |
| Peak memory | 215576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109004552 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_same_csr_outstanding.109004552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.432882746 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 96406452 ps |
| CPU time | 3.04 seconds |
| Started | Sep 18 07:59:41 PM UTC 24 |
| Finished | Sep 18 07:59:45 PM UTC 24 |
| Peak memory | 225796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432882746 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors.432882746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3880573621 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 604313817 ps |
| CPU time | 7.56 seconds |
| Started | Sep 18 07:59:42 PM UTC 24 |
| Finished | Sep 18 07:59:51 PM UTC 24 |
| Peak memory | 225760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880573621 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors_with_csr_rw.3880573621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_errors.3665580559 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 71091060 ps |
| CPU time | 1.96 seconds |
| Started | Sep 18 07:59:42 PM UTC 24 |
| Finished | Sep 18 07:59:45 PM UTC 24 |
| Peak memory | 223044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665580559 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3665580559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1921456321 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 32783512 ps |
| CPU time | 2.47 seconds |
| Started | Sep 18 07:59:44 PM UTC 24 |
| Finished | Sep 18 07:59:48 PM UTC 24 |
| Peak memory | 225844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1921456321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_mem_rw_ with_rand_reset.1921456321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_rw.3237681490 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 29446720 ps |
| CPU time | 1.31 seconds |
| Started | Sep 18 07:59:44 PM UTC 24 |
| Finished | Sep 18 07:59:46 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237681490 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3237681490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_intr_test.3814907008 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 14957320 ps |
| CPU time | 1.02 seconds |
| Started | Sep 18 07:59:43 PM UTC 24 |
| Finished | Sep 18 07:59:45 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814907008 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3814907008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.259292183 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 21097691 ps |
| CPU time | 1.73 seconds |
| Started | Sep 18 07:59:44 PM UTC 24 |
| Finished | Sep 18 07:59:47 PM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259292183 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_same_csr_outstanding.259292183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1041066513 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 701833709 ps |
| CPU time | 2.21 seconds |
| Started | Sep 18 07:59:43 PM UTC 24 |
| Finished | Sep 18 07:59:46 PM UTC 24 |
| Peak memory | 225632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041066513 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors.1041066513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.457908961 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 787141695 ps |
| CPU time | 7 seconds |
| Started | Sep 18 07:59:43 PM UTC 24 |
| Finished | Sep 18 07:59:51 PM UTC 24 |
| Peak memory | 225960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457908961 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors_with_csr_rw.457908961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_errors.471317660 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 33488335 ps |
| CPU time | 2.53 seconds |
| Started | Sep 18 07:59:43 PM UTC 24 |
| Finished | Sep 18 07:59:46 PM UTC 24 |
| Peak memory | 225488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471317660 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.471317660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_intg_err.1688160608 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 107407307 ps |
| CPU time | 2.96 seconds |
| Started | Sep 18 07:59:43 PM UTC 24 |
| Finished | Sep 18 07:59:47 PM UTC 24 |
| Peak memory | 225440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688160608 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err.1688160608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.4134757632 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 479829416 ps |
| CPU time | 1.7 seconds |
| Started | Sep 18 07:59:45 PM UTC 24 |
| Finished | Sep 18 07:59:47 PM UTC 24 |
| Peak memory | 223040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4134757632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_mem_rw_ with_rand_reset.4134757632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_rw.2090687341 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 52112383 ps |
| CPU time | 0.97 seconds |
| Started | Sep 18 07:59:44 PM UTC 24 |
| Finished | Sep 18 07:59:47 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090687341 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2090687341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_intr_test.1290328604 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 47524576 ps |
| CPU time | 1 seconds |
| Started | Sep 18 07:59:44 PM UTC 24 |
| Finished | Sep 18 07:59:46 PM UTC 24 |
| Peak memory | 212336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290328604 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1290328604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.625630625 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 237373020 ps |
| CPU time | 4.52 seconds |
| Started | Sep 18 07:59:44 PM UTC 24 |
| Finished | Sep 18 07:59:50 PM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625630625 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_same_csr_outstanding.625630625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.4061468618 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 159914453 ps |
| CPU time | 4.32 seconds |
| Started | Sep 18 07:59:44 PM UTC 24 |
| Finished | Sep 18 07:59:50 PM UTC 24 |
| Peak memory | 225756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061468618 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors.4061468618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3504098204 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 351688538 ps |
| CPU time | 6.06 seconds |
| Started | Sep 18 07:59:44 PM UTC 24 |
| Finished | Sep 18 07:59:51 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504098204 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors_with_csr_rw.3504098204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_errors.940464249 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 246345962 ps |
| CPU time | 2.17 seconds |
| Started | Sep 18 07:59:44 PM UTC 24 |
| Finished | Sep 18 07:59:48 PM UTC 24 |
| Peak memory | 225460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940464249 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.940464249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1538432934 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 497047177 ps |
| CPU time | 1.96 seconds |
| Started | Sep 18 07:59:46 PM UTC 24 |
| Finished | Sep 18 07:59:49 PM UTC 24 |
| Peak memory | 223028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1538432934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_mem_rw_ with_rand_reset.1538432934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.1417886651 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 58595393 ps |
| CPU time | 1.32 seconds |
| Started | Sep 18 07:59:46 PM UTC 24 |
| Finished | Sep 18 07:59:48 PM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417886651 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1417886651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.1635777132 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 39649135 ps |
| CPU time | 0.79 seconds |
| Started | Sep 18 07:59:46 PM UTC 24 |
| Finished | Sep 18 07:59:48 PM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635777132 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1635777132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2551050134 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 96025810 ps |
| CPU time | 1.81 seconds |
| Started | Sep 18 07:59:46 PM UTC 24 |
| Finished | Sep 18 07:59:49 PM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551050134 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_same_csr_outstanding.2551050134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2353740692 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 361773839 ps |
| CPU time | 3.8 seconds |
| Started | Sep 18 07:59:46 PM UTC 24 |
| Finished | Sep 18 07:59:51 PM UTC 24 |
| Peak memory | 226084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353740692 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors.2353740692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.4160729815 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 341914690 ps |
| CPU time | 4.03 seconds |
| Started | Sep 18 07:59:46 PM UTC 24 |
| Finished | Sep 18 07:59:51 PM UTC 24 |
| Peak memory | 232192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160729815 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors_with_csr_rw.4160729815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.1310185805 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 231290871 ps |
| CPU time | 2.9 seconds |
| Started | Sep 18 07:59:46 PM UTC 24 |
| Finished | Sep 18 07:59:50 PM UTC 24 |
| Peak memory | 225440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310185805 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1310185805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1836189982 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 21602017 ps |
| CPU time | 1.85 seconds |
| Started | Sep 18 07:59:47 PM UTC 24 |
| Finished | Sep 18 07:59:50 PM UTC 24 |
| Peak memory | 223040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1836189982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_mem_rw_ with_rand_reset.1836189982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.1060474767 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 32434536 ps |
| CPU time | 1.64 seconds |
| Started | Sep 18 07:59:47 PM UTC 24 |
| Finished | Sep 18 07:59:50 PM UTC 24 |
| Peak memory | 215292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060474767 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1060474767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.1412682031 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 11280760 ps |
| CPU time | 0.91 seconds |
| Started | Sep 18 07:59:47 PM UTC 24 |
| Finished | Sep 18 07:59:49 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412682031 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1412682031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2460156057 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 227651596 ps |
| CPU time | 3.09 seconds |
| Started | Sep 18 07:59:47 PM UTC 24 |
| Finished | Sep 18 07:59:51 PM UTC 24 |
| Peak memory | 215228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460156057 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_same_csr_outstanding.2460156057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2756925433 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 274861547 ps |
| CPU time | 3.38 seconds |
| Started | Sep 18 07:59:46 PM UTC 24 |
| Finished | Sep 18 07:59:51 PM UTC 24 |
| Peak memory | 225708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756925433 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors.2756925433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3180868549 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 803456389 ps |
| CPU time | 5.83 seconds |
| Started | Sep 18 07:59:47 PM UTC 24 |
| Finished | Sep 18 07:59:54 PM UTC 24 |
| Peak memory | 225960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180868549 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors_with_csr_rw.3180868549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.4271089292 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 202985796 ps |
| CPU time | 2.47 seconds |
| Started | Sep 18 07:59:47 PM UTC 24 |
| Finished | Sep 18 07:59:51 PM UTC 24 |
| Peak memory | 225560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271089292 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.4271089292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.2788721005 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 163506395 ps |
| CPU time | 3.55 seconds |
| Started | Sep 18 07:59:47 PM UTC 24 |
| Finished | Sep 18 07:59:52 PM UTC 24 |
| Peak memory | 225440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788721005 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err.2788721005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2221437502 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 145297430 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 07:59:49 PM UTC 24 |
| Finished | Sep 18 07:59:51 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2221437502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_mem_rw_ with_rand_reset.2221437502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.766704383 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 22888002 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 07:59:49 PM UTC 24 |
| Finished | Sep 18 07:59:51 PM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766704383 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.766704383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.3636945756 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 16633415 ps |
| CPU time | 1.06 seconds |
| Started | Sep 18 07:59:48 PM UTC 24 |
| Finished | Sep 18 07:59:50 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636945756 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3636945756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2377911116 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 134612043 ps |
| CPU time | 2.9 seconds |
| Started | Sep 18 07:59:49 PM UTC 24 |
| Finished | Sep 18 07:59:53 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377911116 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_same_csr_outstanding.2377911116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2306844319 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 158420381 ps |
| CPU time | 4.75 seconds |
| Started | Sep 18 07:59:47 PM UTC 24 |
| Finished | Sep 18 07:59:53 PM UTC 24 |
| Peak memory | 231324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306844319 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors.2306844319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3693228256 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 201063314 ps |
| CPU time | 5.56 seconds |
| Started | Sep 18 07:59:47 PM UTC 24 |
| Finished | Sep 18 07:59:54 PM UTC 24 |
| Peak memory | 225760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693228256 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors_with_csr_rw.3693228256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.3070133298 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 131093016 ps |
| CPU time | 4.9 seconds |
| Started | Sep 18 07:59:47 PM UTC 24 |
| Finished | Sep 18 07:59:53 PM UTC 24 |
| Peak memory | 225368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070133298 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3070133298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.1187593074 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 397450776 ps |
| CPU time | 4.4 seconds |
| Started | Sep 18 07:59:48 PM UTC 24 |
| Finished | Sep 18 07:59:53 PM UTC 24 |
| Peak memory | 225560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187593074 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err.1187593074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1677970497 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 37668610 ps |
| CPU time | 1.53 seconds |
| Started | Sep 18 07:59:50 PM UTC 24 |
| Finished | Sep 18 07:59:53 PM UTC 24 |
| Peak memory | 223040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1677970497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_mem_rw_ with_rand_reset.1677970497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.1024121875 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 16584143 ps |
| CPU time | 1.14 seconds |
| Started | Sep 18 07:59:50 PM UTC 24 |
| Finished | Sep 18 07:59:53 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024121875 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1024121875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.2244299423 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 25745708 ps |
| CPU time | 1.07 seconds |
| Started | Sep 18 07:59:50 PM UTC 24 |
| Finished | Sep 18 07:59:52 PM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244299423 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2244299423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.4125547148 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 109500868 ps |
| CPU time | 2.47 seconds |
| Started | Sep 18 07:59:50 PM UTC 24 |
| Finished | Sep 18 07:59:54 PM UTC 24 |
| Peak memory | 225444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125547148 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_same_csr_outstanding.4125547148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3256596970 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 35435632 ps |
| CPU time | 1.71 seconds |
| Started | Sep 18 07:59:49 PM UTC 24 |
| Finished | Sep 18 07:59:52 PM UTC 24 |
| Peak memory | 225868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256596970 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors.3256596970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2989510683 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 93764301 ps |
| CPU time | 4.79 seconds |
| Started | Sep 18 07:59:49 PM UTC 24 |
| Finished | Sep 18 07:59:55 PM UTC 24 |
| Peak memory | 226024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989510683 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors_with_csr_rw.2989510683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.158624699 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 827549868 ps |
| CPU time | 2.41 seconds |
| Started | Sep 18 07:59:49 PM UTC 24 |
| Finished | Sep 18 07:59:52 PM UTC 24 |
| Peak memory | 231772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158624699 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.158624699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.2563924263 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 179723092 ps |
| CPU time | 3.06 seconds |
| Started | Sep 18 07:59:49 PM UTC 24 |
| Finished | Sep 18 07:59:53 PM UTC 24 |
| Peak memory | 225436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563924263 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err.2563924263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2149214564 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 136813438 ps |
| CPU time | 1.39 seconds |
| Started | Sep 18 07:59:52 PM UTC 24 |
| Finished | Sep 18 07:59:54 PM UTC 24 |
| Peak memory | 223040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2149214564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_mem_rw_ with_rand_reset.2149214564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.2326428085 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 47909880 ps |
| CPU time | 1.37 seconds |
| Started | Sep 18 07:59:52 PM UTC 24 |
| Finished | Sep 18 07:59:54 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326428085 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2326428085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.3020378455 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 22312666 ps |
| CPU time | 0.66 seconds |
| Started | Sep 18 07:59:52 PM UTC 24 |
| Finished | Sep 18 07:59:53 PM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020378455 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3020378455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1528465559 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 270746786 ps |
| CPU time | 3.28 seconds |
| Started | Sep 18 07:59:52 PM UTC 24 |
| Finished | Sep 18 07:59:56 PM UTC 24 |
| Peak memory | 215252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528465559 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_same_csr_outstanding.1528465559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.4205349400 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 178258766 ps |
| CPU time | 3.46 seconds |
| Started | Sep 18 07:59:50 PM UTC 24 |
| Finished | Sep 18 07:59:55 PM UTC 24 |
| Peak memory | 225708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205349400 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors.4205349400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.162421353 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 1290682629 ps |
| CPU time | 7.91 seconds |
| Started | Sep 18 07:59:50 PM UTC 24 |
| Finished | Sep 18 08:00:00 PM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162421353 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors_with_csr_rw.162421353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.3407179436 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 325271130 ps |
| CPU time | 3.73 seconds |
| Started | Sep 18 07:59:50 PM UTC 24 |
| Finished | Sep 18 07:59:55 PM UTC 24 |
| Peak memory | 225528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407179436 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3407179436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1275691542 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 58601453 ps |
| CPU time | 2.44 seconds |
| Started | Sep 18 07:59:52 PM UTC 24 |
| Finished | Sep 18 07:59:56 PM UTC 24 |
| Peak memory | 229524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1275691542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_mem_rw_ with_rand_reset.1275691542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.794317087 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 29592557 ps |
| CPU time | 1.64 seconds |
| Started | Sep 18 07:59:52 PM UTC 24 |
| Finished | Sep 18 07:59:55 PM UTC 24 |
| Peak memory | 212796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794317087 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.794317087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.3648990953 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 38385401 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 07:59:52 PM UTC 24 |
| Finished | Sep 18 07:59:54 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648990953 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3648990953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3133226015 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 39273565 ps |
| CPU time | 1.73 seconds |
| Started | Sep 18 07:59:52 PM UTC 24 |
| Finished | Sep 18 07:59:55 PM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133226015 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_same_csr_outstanding.3133226015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1947619333 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 85423876 ps |
| CPU time | 1.7 seconds |
| Started | Sep 18 07:59:52 PM UTC 24 |
| Finished | Sep 18 07:59:54 PM UTC 24 |
| Peak memory | 225924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947619333 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors.1947619333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.556148891 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 208399223 ps |
| CPU time | 7.4 seconds |
| Started | Sep 18 07:59:52 PM UTC 24 |
| Finished | Sep 18 08:00:00 PM UTC 24 |
| Peak memory | 232192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556148891 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors_with_csr_rw.556148891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.655136137 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 374012410 ps |
| CPU time | 2.6 seconds |
| Started | Sep 18 07:59:52 PM UTC 24 |
| Finished | Sep 18 07:59:56 PM UTC 24 |
| Peak memory | 225460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655136137 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.655136137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.2263004468 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 437325376 ps |
| CPU time | 8.86 seconds |
| Started | Sep 18 07:59:52 PM UTC 24 |
| Finished | Sep 18 08:00:02 PM UTC 24 |
| Peak memory | 225696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263004468 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err.2263004468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_aliasing.2104846063 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 4608386035 ps |
| CPU time | 14.94 seconds |
| Started | Sep 18 07:59:25 PM UTC 24 |
| Finished | Sep 18 07:59:41 PM UTC 24 |
| Peak memory | 215584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104846063 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2104846063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1740364842 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 679583294 ps |
| CPU time | 7.07 seconds |
| Started | Sep 18 07:59:25 PM UTC 24 |
| Finished | Sep 18 07:59:33 PM UTC 24 |
| Peak memory | 215384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740364842 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1740364842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1552658175 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 80078618 ps |
| CPU time | 1.59 seconds |
| Started | Sep 18 07:59:25 PM UTC 24 |
| Finished | Sep 18 07:59:28 PM UTC 24 |
| Peak memory | 212812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552658175 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1552658175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3207490945 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 68217013 ps |
| CPU time | 2.14 seconds |
| Started | Sep 18 07:59:26 PM UTC 24 |
| Finished | Sep 18 07:59:30 PM UTC 24 |
| Peak memory | 232040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3207490945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_mem_rw_w ith_rand_reset.3207490945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_rw.3048228280 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 73305318 ps |
| CPU time | 1.38 seconds |
| Started | Sep 18 07:59:25 PM UTC 24 |
| Finished | Sep 18 07:59:28 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048228280 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3048228280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_intr_test.162358042 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 123952729 ps |
| CPU time | 1.17 seconds |
| Started | Sep 18 07:59:25 PM UTC 24 |
| Finished | Sep 18 07:59:27 PM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162358042 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.162358042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3024352359 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 118663427 ps |
| CPU time | 4.98 seconds |
| Started | Sep 18 07:59:26 PM UTC 24 |
| Finished | Sep 18 07:59:32 PM UTC 24 |
| Peak memory | 215236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024352359 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_same_csr_outstanding.3024352359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1019082271 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 43228994 ps |
| CPU time | 2.46 seconds |
| Started | Sep 18 07:59:24 PM UTC 24 |
| Finished | Sep 18 07:59:28 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019082271 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors.1019082271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2914774005 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 501001673 ps |
| CPU time | 6.87 seconds |
| Started | Sep 18 07:59:24 PM UTC 24 |
| Finished | Sep 18 07:59:32 PM UTC 24 |
| Peak memory | 225580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914774005 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors_with_csr_rw.2914774005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_errors.248451409 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 176763457 ps |
| CPU time | 6.83 seconds |
| Started | Sep 18 07:59:24 PM UTC 24 |
| Finished | Sep 18 07:59:32 PM UTC 24 |
| Peak memory | 225480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248451409 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.248451409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.4016879225 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 13112236 ps |
| CPU time | 1.14 seconds |
| Started | Sep 18 07:59:53 PM UTC 24 |
| Finished | Sep 18 07:59:55 PM UTC 24 |
| Peak memory | 213052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016879225 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.4016879225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/20.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.3735932797 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 48679740 ps |
| CPU time | 1.16 seconds |
| Started | Sep 18 07:59:53 PM UTC 24 |
| Finished | Sep 18 07:59:55 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735932797 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3735932797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/21.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.1282298718 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 26417404 ps |
| CPU time | 0.9 seconds |
| Started | Sep 18 07:59:53 PM UTC 24 |
| Finished | Sep 18 07:59:55 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282298718 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1282298718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/22.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.3106256299 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 33071177 ps |
| CPU time | 0.97 seconds |
| Started | Sep 18 07:59:53 PM UTC 24 |
| Finished | Sep 18 07:59:55 PM UTC 24 |
| Peak memory | 213260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106256299 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3106256299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/23.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.2495033550 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 161303329 ps |
| CPU time | 0.87 seconds |
| Started | Sep 18 07:59:53 PM UTC 24 |
| Finished | Sep 18 07:59:55 PM UTC 24 |
| Peak memory | 212604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495033550 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2495033550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/24.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.1652691302 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 11613943 ps |
| CPU time | 0.98 seconds |
| Started | Sep 18 07:59:53 PM UTC 24 |
| Finished | Sep 18 07:59:55 PM UTC 24 |
| Peak memory | 212796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652691302 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1652691302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/25.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.4264407956 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 15165590 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 07:59:53 PM UTC 24 |
| Finished | Sep 18 07:59:55 PM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264407956 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.4264407956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/26.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.4107635804 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 26845984 ps |
| CPU time | 0.98 seconds |
| Started | Sep 18 07:59:53 PM UTC 24 |
| Finished | Sep 18 07:59:55 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107635804 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.4107635804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/27.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.1736159390 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 41480499 ps |
| CPU time | 0.87 seconds |
| Started | Sep 18 07:59:53 PM UTC 24 |
| Finished | Sep 18 07:59:55 PM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736159390 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1736159390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/28.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.2728343603 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 40723805 ps |
| CPU time | 0.94 seconds |
| Started | Sep 18 07:59:53 PM UTC 24 |
| Finished | Sep 18 07:59:56 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728343603 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2728343603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/29.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_aliasing.4278781865 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 945590325 ps |
| CPU time | 7.14 seconds |
| Started | Sep 18 07:59:29 PM UTC 24 |
| Finished | Sep 18 07:59:37 PM UTC 24 |
| Peak memory | 215000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278781865 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.4278781865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1667437311 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 434252021 ps |
| CPU time | 8.86 seconds |
| Started | Sep 18 07:59:29 PM UTC 24 |
| Finished | Sep 18 07:59:39 PM UTC 24 |
| Peak memory | 215064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667437311 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1667437311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2456446091 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 39430119 ps |
| CPU time | 1.45 seconds |
| Started | Sep 18 07:59:29 PM UTC 24 |
| Finished | Sep 18 07:59:31 PM UTC 24 |
| Peak memory | 212812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456446091 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2456446091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3905952682 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 68135191 ps |
| CPU time | 2.96 seconds |
| Started | Sep 18 07:59:29 PM UTC 24 |
| Finished | Sep 18 07:59:33 PM UTC 24 |
| Peak memory | 225508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3905952682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_mem_rw_w ith_rand_reset.3905952682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_rw.3655901603 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 16283762 ps |
| CPU time | 1.48 seconds |
| Started | Sep 18 07:59:29 PM UTC 24 |
| Finished | Sep 18 07:59:31 PM UTC 24 |
| Peak memory | 212732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655901603 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3655901603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_intr_test.765836285 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 26319256 ps |
| CPU time | 0.99 seconds |
| Started | Sep 18 07:59:29 PM UTC 24 |
| Finished | Sep 18 07:59:31 PM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765836285 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.765836285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2846365793 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 317406848 ps |
| CPU time | 2.53 seconds |
| Started | Sep 18 07:59:29 PM UTC 24 |
| Finished | Sep 18 07:59:33 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846365793 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_same_csr_outstanding.2846365793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3459423691 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 78787174 ps |
| CPU time | 1.77 seconds |
| Started | Sep 18 07:59:26 PM UTC 24 |
| Finished | Sep 18 07:59:29 PM UTC 24 |
| Peak memory | 225964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459423691 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors.3459423691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_errors.3183067115 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 495407257 ps |
| CPU time | 3.33 seconds |
| Started | Sep 18 07:59:29 PM UTC 24 |
| Finished | Sep 18 07:59:33 PM UTC 24 |
| Peak memory | 225432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183067115 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3183067115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_intg_err.1761472602 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 112059957 ps |
| CPU time | 4.74 seconds |
| Started | Sep 18 07:59:29 PM UTC 24 |
| Finished | Sep 18 07:59:35 PM UTC 24 |
| Peak memory | 225364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761472602 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.1761472602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.1227185845 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 125742309 ps |
| CPU time | 0.81 seconds |
| Started | Sep 18 07:59:55 PM UTC 24 |
| Finished | Sep 18 07:59:57 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227185845 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1227185845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/30.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.104147624 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 35234344 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 07:59:55 PM UTC 24 |
| Finished | Sep 18 07:59:57 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104147624 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.104147624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/31.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.2819446797 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 14460084 ps |
| CPU time | 0.87 seconds |
| Started | Sep 18 07:59:55 PM UTC 24 |
| Finished | Sep 18 07:59:57 PM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819446797 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2819446797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/32.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.815597940 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 46175949 ps |
| CPU time | 0.79 seconds |
| Started | Sep 18 07:59:55 PM UTC 24 |
| Finished | Sep 18 07:59:57 PM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815597940 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.815597940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/33.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.1577252664 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 43510554 ps |
| CPU time | 1.09 seconds |
| Started | Sep 18 07:59:55 PM UTC 24 |
| Finished | Sep 18 07:59:57 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577252664 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1577252664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/34.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.1642612139 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 11178182 ps |
| CPU time | 0.88 seconds |
| Started | Sep 18 07:59:55 PM UTC 24 |
| Finished | Sep 18 07:59:57 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642612139 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1642612139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/35.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.2731522346 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 11068079 ps |
| CPU time | 0.87 seconds |
| Started | Sep 18 07:59:55 PM UTC 24 |
| Finished | Sep 18 07:59:57 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731522346 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2731522346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/36.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.16092939 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 24941206 ps |
| CPU time | 0.99 seconds |
| Started | Sep 18 07:59:55 PM UTC 24 |
| Finished | Sep 18 07:59:57 PM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16092939 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.16092939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/37.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.3029785789 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 27594899 ps |
| CPU time | 0.82 seconds |
| Started | Sep 18 07:59:55 PM UTC 24 |
| Finished | Sep 18 07:59:57 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029785789 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3029785789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/38.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.3867216486 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 36563193 ps |
| CPU time | 0.72 seconds |
| Started | Sep 18 07:59:55 PM UTC 24 |
| Finished | Sep 18 07:59:57 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867216486 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3867216486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/39.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_aliasing.3623683437 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 237210154 ps |
| CPU time | 7.97 seconds |
| Started | Sep 18 07:59:32 PM UTC 24 |
| Finished | Sep 18 07:59:41 PM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623683437 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3623683437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1017664954 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 903837526 ps |
| CPU time | 24.62 seconds |
| Started | Sep 18 07:59:32 PM UTC 24 |
| Finished | Sep 18 07:59:58 PM UTC 24 |
| Peak memory | 214292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017664954 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1017664954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3574121402 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 480268271 ps |
| CPU time | 1.72 seconds |
| Started | Sep 18 07:59:32 PM UTC 24 |
| Finished | Sep 18 07:59:35 PM UTC 24 |
| Peak memory | 212812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574121402 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3574121402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3558007399 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 24170563 ps |
| CPU time | 1.59 seconds |
| Started | Sep 18 07:59:32 PM UTC 24 |
| Finished | Sep 18 07:59:35 PM UTC 24 |
| Peak memory | 223044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3558007399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_mem_rw_w ith_rand_reset.3558007399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_rw.847857664 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 30429265 ps |
| CPU time | 1.68 seconds |
| Started | Sep 18 07:59:32 PM UTC 24 |
| Finished | Sep 18 07:59:35 PM UTC 24 |
| Peak memory | 215252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847857664 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.847857664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_intr_test.4087395513 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 28125513 ps |
| CPU time | 1.1 seconds |
| Started | Sep 18 07:59:32 PM UTC 24 |
| Finished | Sep 18 07:59:34 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087395513 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.4087395513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.4219055159 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 24536633 ps |
| CPU time | 1.9 seconds |
| Started | Sep 18 07:59:32 PM UTC 24 |
| Finished | Sep 18 07:59:35 PM UTC 24 |
| Peak memory | 215292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219055159 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_same_csr_outstanding.4219055159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1885159584 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 294609518 ps |
| CPU time | 4.21 seconds |
| Started | Sep 18 07:59:32 PM UTC 24 |
| Finished | Sep 18 07:59:37 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885159584 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors.1885159584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.345376507 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 116465915 ps |
| CPU time | 4.91 seconds |
| Started | Sep 18 07:59:32 PM UTC 24 |
| Finished | Sep 18 07:59:38 PM UTC 24 |
| Peak memory | 225964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345376507 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors_with_csr_rw.345376507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_errors.2810258184 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 190748544 ps |
| CPU time | 4.36 seconds |
| Started | Sep 18 07:59:32 PM UTC 24 |
| Finished | Sep 18 07:59:37 PM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810258184 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2810258184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_intg_err.1216929929 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 52396273 ps |
| CPU time | 2.79 seconds |
| Started | Sep 18 07:59:32 PM UTC 24 |
| Finished | Sep 18 07:59:36 PM UTC 24 |
| Peak memory | 225364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216929929 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.1216929929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.1372902256 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 8336012 ps |
| CPU time | 0.78 seconds |
| Started | Sep 18 07:59:55 PM UTC 24 |
| Finished | Sep 18 07:59:57 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372902256 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1372902256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/40.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.2631039647 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 11186560 ps |
| CPU time | 0.99 seconds |
| Started | Sep 18 07:59:55 PM UTC 24 |
| Finished | Sep 18 07:59:57 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631039647 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2631039647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/41.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.1895762997 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 27160674 ps |
| CPU time | 0.75 seconds |
| Started | Sep 18 07:59:56 PM UTC 24 |
| Finished | Sep 18 07:59:58 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895762997 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1895762997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/42.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.2788274745 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 8961990 ps |
| CPU time | 0.72 seconds |
| Started | Sep 18 07:59:56 PM UTC 24 |
| Finished | Sep 18 07:59:58 PM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788274745 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2788274745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/43.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.3858962010 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 12667212 ps |
| CPU time | 0.8 seconds |
| Started | Sep 18 07:59:56 PM UTC 24 |
| Finished | Sep 18 07:59:58 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858962010 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3858962010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/44.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.3797046419 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 37604516 ps |
| CPU time | 1 seconds |
| Started | Sep 18 07:59:56 PM UTC 24 |
| Finished | Sep 18 07:59:58 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797046419 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3797046419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/45.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.1330931195 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 38480149 ps |
| CPU time | 0.91 seconds |
| Started | Sep 18 07:59:56 PM UTC 24 |
| Finished | Sep 18 07:59:58 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330931195 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1330931195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/46.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.3521632703 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 15432064 ps |
| CPU time | 0.97 seconds |
| Started | Sep 18 07:59:56 PM UTC 24 |
| Finished | Sep 18 07:59:58 PM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521632703 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3521632703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/47.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.1444962065 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 17803374 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 07:59:56 PM UTC 24 |
| Finished | Sep 18 07:59:58 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444962065 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1444962065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/48.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.1474235112 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 7597023 ps |
| CPU time | 0.78 seconds |
| Started | Sep 18 07:59:56 PM UTC 24 |
| Finished | Sep 18 07:59:58 PM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474235112 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1474235112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/49.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3549458427 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 32008379 ps |
| CPU time | 1.43 seconds |
| Started | Sep 18 07:59:34 PM UTC 24 |
| Finished | Sep 18 07:59:36 PM UTC 24 |
| Peak memory | 215260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3549458427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_mem_rw_w ith_rand_reset.3549458427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_rw.586183946 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 156322680 ps |
| CPU time | 1.11 seconds |
| Started | Sep 18 07:59:34 PM UTC 24 |
| Finished | Sep 18 07:59:36 PM UTC 24 |
| Peak memory | 212796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586183946 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.586183946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_intr_test.3206517457 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 18884563 ps |
| CPU time | 0.86 seconds |
| Started | Sep 18 07:59:34 PM UTC 24 |
| Finished | Sep 18 07:59:36 PM UTC 24 |
| Peak memory | 212316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206517457 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3206517457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1742036166 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 20005449 ps |
| CPU time | 1.73 seconds |
| Started | Sep 18 07:59:34 PM UTC 24 |
| Finished | Sep 18 07:59:37 PM UTC 24 |
| Peak memory | 212744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742036166 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_same_csr_outstanding.1742036166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2732242496 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 137145097 ps |
| CPU time | 4.08 seconds |
| Started | Sep 18 07:59:32 PM UTC 24 |
| Finished | Sep 18 07:59:38 PM UTC 24 |
| Peak memory | 225796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732242496 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors.2732242496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.814887837 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 158002829 ps |
| CPU time | 6.48 seconds |
| Started | Sep 18 07:59:32 PM UTC 24 |
| Finished | Sep 18 07:59:40 PM UTC 24 |
| Peak memory | 225716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814887837 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors_with_csr_rw.814887837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_errors.1235387328 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 31236907 ps |
| CPU time | 2.88 seconds |
| Started | Sep 18 07:59:34 PM UTC 24 |
| Finished | Sep 18 07:59:38 PM UTC 24 |
| Peak memory | 227856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235387328 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1235387328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_intg_err.3675795145 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 220540309 ps |
| CPU time | 4.75 seconds |
| Started | Sep 18 07:59:34 PM UTC 24 |
| Finished | Sep 18 07:59:39 PM UTC 24 |
| Peak memory | 225356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675795145 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.3675795145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.192144383 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 47154848 ps |
| CPU time | 1.73 seconds |
| Started | Sep 18 07:59:35 PM UTC 24 |
| Finished | Sep 18 07:59:38 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=192144383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_mem_rw_wi th_rand_reset.192144383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_rw.541966142 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 32141137 ps |
| CPU time | 1.37 seconds |
| Started | Sep 18 07:59:35 PM UTC 24 |
| Finished | Sep 18 07:59:38 PM UTC 24 |
| Peak memory | 212692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541966142 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.541966142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_intr_test.1609004136 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 34300180 ps |
| CPU time | 1.02 seconds |
| Started | Sep 18 07:59:35 PM UTC 24 |
| Finished | Sep 18 07:59:37 PM UTC 24 |
| Peak memory | 212724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609004136 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1609004136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3914665703 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 131569006 ps |
| CPU time | 2.62 seconds |
| Started | Sep 18 07:59:35 PM UTC 24 |
| Finished | Sep 18 07:59:39 PM UTC 24 |
| Peak memory | 215252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914665703 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_same_csr_outstanding.3914665703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.647803058 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 103966866 ps |
| CPU time | 3 seconds |
| Started | Sep 18 07:59:34 PM UTC 24 |
| Finished | Sep 18 07:59:38 PM UTC 24 |
| Peak memory | 225684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647803058 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors.647803058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3211166793 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 323413411 ps |
| CPU time | 8.66 seconds |
| Started | Sep 18 07:59:34 PM UTC 24 |
| Finished | Sep 18 07:59:44 PM UTC 24 |
| Peak memory | 225888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211166793 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors_with_csr_rw.3211166793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_errors.3905624847 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 27169412 ps |
| CPU time | 1.82 seconds |
| Started | Sep 18 07:59:34 PM UTC 24 |
| Finished | Sep 18 07:59:37 PM UTC 24 |
| Peak memory | 223040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905624847 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3905624847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_intg_err.2923078560 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 163327733 ps |
| CPU time | 3.59 seconds |
| Started | Sep 18 07:59:35 PM UTC 24 |
| Finished | Sep 18 07:59:40 PM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923078560 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.2923078560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.4211552702 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 43879107 ps |
| CPU time | 2.17 seconds |
| Started | Sep 18 07:59:37 PM UTC 24 |
| Finished | Sep 18 07:59:40 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4211552702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_mem_rw_w ith_rand_reset.4211552702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_rw.2298114120 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 70796033 ps |
| CPU time | 1.48 seconds |
| Started | Sep 18 07:59:37 PM UTC 24 |
| Finished | Sep 18 07:59:39 PM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298114120 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2298114120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_intr_test.1149180057 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 19152329 ps |
| CPU time | 0.95 seconds |
| Started | Sep 18 07:59:37 PM UTC 24 |
| Finished | Sep 18 07:59:39 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149180057 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1149180057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2575109757 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 127014399 ps |
| CPU time | 2.83 seconds |
| Started | Sep 18 07:59:37 PM UTC 24 |
| Finished | Sep 18 07:59:41 PM UTC 24 |
| Peak memory | 215132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575109757 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_same_csr_outstanding.2575109757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1929314351 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 728175796 ps |
| CPU time | 5.82 seconds |
| Started | Sep 18 07:59:35 PM UTC 24 |
| Finished | Sep 18 07:59:42 PM UTC 24 |
| Peak memory | 225964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929314351 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors.1929314351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.984655511 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 275594133 ps |
| CPU time | 3.94 seconds |
| Started | Sep 18 07:59:37 PM UTC 24 |
| Finished | Sep 18 07:59:42 PM UTC 24 |
| Peak memory | 225616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984655511 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors_with_csr_rw.984655511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_errors.1760094806 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 501469188 ps |
| CPU time | 3 seconds |
| Started | Sep 18 07:59:37 PM UTC 24 |
| Finished | Sep 18 07:59:41 PM UTC 24 |
| Peak memory | 227800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760094806 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1760094806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_intg_err.1371374673 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 55498018 ps |
| CPU time | 3.28 seconds |
| Started | Sep 18 07:59:37 PM UTC 24 |
| Finished | Sep 18 07:59:41 PM UTC 24 |
| Peak memory | 225336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371374673 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.1371374673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2757457889 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 25749411 ps |
| CPU time | 1.41 seconds |
| Started | Sep 18 07:59:38 PM UTC 24 |
| Finished | Sep 18 07:59:41 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2757457889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_mem_rw_w ith_rand_reset.2757457889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_rw.2955525620 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 70688720 ps |
| CPU time | 1.29 seconds |
| Started | Sep 18 07:59:38 PM UTC 24 |
| Finished | Sep 18 07:59:40 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955525620 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2955525620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_intr_test.2902982777 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 32131671 ps |
| CPU time | 0.89 seconds |
| Started | Sep 18 07:59:38 PM UTC 24 |
| Finished | Sep 18 07:59:40 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902982777 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2902982777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.90175205 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 106534460 ps |
| CPU time | 3.78 seconds |
| Started | Sep 18 07:59:38 PM UTC 24 |
| Finished | Sep 18 07:59:43 PM UTC 24 |
| Peak memory | 215616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90175205 -assert nopostproc +UV M_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_same_csr_outstanding.90175205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1073469471 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 248266322 ps |
| CPU time | 2.41 seconds |
| Started | Sep 18 07:59:38 PM UTC 24 |
| Finished | Sep 18 07:59:41 PM UTC 24 |
| Peak memory | 225708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073469471 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors.1073469471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2904495831 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 854925504 ps |
| CPU time | 5.43 seconds |
| Started | Sep 18 07:59:38 PM UTC 24 |
| Finished | Sep 18 07:59:45 PM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904495831 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors_with_csr_rw.2904495831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_errors.126899355 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 150135534 ps |
| CPU time | 2.89 seconds |
| Started | Sep 18 07:59:38 PM UTC 24 |
| Finished | Sep 18 07:59:42 PM UTC 24 |
| Peak memory | 227576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126899355 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.126899355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_intg_err.819788756 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 1420022938 ps |
| CPU time | 4.06 seconds |
| Started | Sep 18 07:59:38 PM UTC 24 |
| Finished | Sep 18 07:59:43 PM UTC 24 |
| Peak memory | 225688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819788756 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.819788756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.796310009 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 47091631 ps |
| CPU time | 2.48 seconds |
| Started | Sep 18 07:59:40 PM UTC 24 |
| Finished | Sep 18 07:59:43 PM UTC 24 |
| Peak memory | 225428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=796310009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_mem_rw_wi th_rand_reset.796310009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_rw.2981890584 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 13989413 ps |
| CPU time | 1.06 seconds |
| Started | Sep 18 07:59:40 PM UTC 24 |
| Finished | Sep 18 07:59:42 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981890584 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2981890584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_intr_test.2621427067 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 8736967 ps |
| CPU time | 1.01 seconds |
| Started | Sep 18 07:59:40 PM UTC 24 |
| Finished | Sep 18 07:59:42 PM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621427067 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2621427067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.879762309 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 46212275 ps |
| CPU time | 2.52 seconds |
| Started | Sep 18 07:59:40 PM UTC 24 |
| Finished | Sep 18 07:59:43 PM UTC 24 |
| Peak memory | 215252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879762309 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_same_csr_outstanding.879762309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3363668759 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 124925195 ps |
| CPU time | 1.95 seconds |
| Started | Sep 18 07:59:38 PM UTC 24 |
| Finished | Sep 18 07:59:41 PM UTC 24 |
| Peak memory | 225924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363668759 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors.3363668759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2401249216 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 339185513 ps |
| CPU time | 6.08 seconds |
| Started | Sep 18 07:59:38 PM UTC 24 |
| Finished | Sep 18 07:59:46 PM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401249216 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors_with_csr_rw.2401249216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_errors.1510447677 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 44612571 ps |
| CPU time | 2.91 seconds |
| Started | Sep 18 07:59:38 PM UTC 24 |
| Finished | Sep 18 07:59:42 PM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510447677 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1510447677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/0.keymgr_direct_to_disabled.4075181725 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 144713342 ps |
| CPU time | 2.3 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:54:25 PM UTC 24 |
| Peak memory | 217344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075181725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.4075181725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/0.keymgr_lc_disable.339264601 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 148086325 ps |
| CPU time | 2.59 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:54:25 PM UTC 24 |
| Peak memory | 225324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339264601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.339264601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/0.keymgr_random.1014435514 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 218590954 ps |
| CPU time | 5.85 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:54:28 PM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014435514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1014435514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/0.keymgr_sideload.1000906071 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 653110008 ps |
| CPU time | 18.47 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:54:41 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000906071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1000906071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_aes.3810593390 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 511865792 ps |
| CPU time | 3.41 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:54:26 PM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810593390 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3810593390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_otbn.4042320177 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 625269383 ps |
| CPU time | 19.51 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:54:42 PM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042320177 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.4042320177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_protect.1214326231 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 39452447 ps |
| CPU time | 2.06 seconds |
| Started | Sep 18 07:54:26 PM UTC 24 |
| Finished | Sep 18 07:54:29 PM UTC 24 |
| Peak memory | 217428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214326231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1214326231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/0.keymgr_smoke.451767339 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 118477087 ps |
| CPU time | 3.04 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:54:25 PM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451767339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.451767339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/0.keymgr_sw_invalid_input.2378356912 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 88743005 ps |
| CPU time | 2.48 seconds |
| Started | Sep 18 07:54:21 PM UTC 24 |
| Finished | Sep 18 07:54:25 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378356912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2378356912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/0.keymgr_sync_async_fault_cross.3670961049 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 508248780 ps |
| CPU time | 2.3 seconds |
| Started | Sep 18 07:54:26 PM UTC 24 |
| Finished | Sep 18 07:54:30 PM UTC 24 |
| Peak memory | 217144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670961049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3670961049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/0.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/1.keymgr_alert_test.797337668 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 58445185 ps |
| CPU time | 0.93 seconds |
| Started | Sep 18 07:54:31 PM UTC 24 |
| Finished | Sep 18 07:54:34 PM UTC 24 |
| Peak memory | 212772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797337668 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.797337668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/1.keymgr_custom_cm.4150804324 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 314758535 ps |
| CPU time | 3.39 seconds |
| Started | Sep 18 07:54:27 PM UTC 24 |
| Finished | Sep 18 07:54:31 PM UTC 24 |
| Peak memory | 217404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150804324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.4150804324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/1.keymgr_direct_to_disabled.92279959 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 432296232 ps |
| CPU time | 2.72 seconds |
| Started | Sep 18 07:54:26 PM UTC 24 |
| Finished | Sep 18 07:54:31 PM UTC 24 |
| Peak memory | 223396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92279959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.92279959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/1.keymgr_hwsw_invalid_input.3543693052 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1253700291 ps |
| CPU time | 3.51 seconds |
| Started | Sep 18 07:54:27 PM UTC 24 |
| Finished | Sep 18 07:54:31 PM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543693052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3543693052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/1.keymgr_kmac_rsp_err.4170559285 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 64447817 ps |
| CPU time | 3.35 seconds |
| Started | Sep 18 07:54:27 PM UTC 24 |
| Finished | Sep 18 07:54:31 PM UTC 24 |
| Peak memory | 231560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170559285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.4170559285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/1.keymgr_random.3257443711 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 167679023 ps |
| CPU time | 6.51 seconds |
| Started | Sep 18 07:54:26 PM UTC 24 |
| Finished | Sep 18 07:54:34 PM UTC 24 |
| Peak memory | 223492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257443711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3257443711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/1.keymgr_sec_cm.2524864671 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1349128276 ps |
| CPU time | 13.06 seconds |
| Started | Sep 18 07:54:29 PM UTC 24 |
| Finished | Sep 18 07:54:47 PM UTC 24 |
| Peak memory | 259340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524864671 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2524864671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/1.keymgr_sideload.3479150460 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 59266193 ps |
| CPU time | 3.83 seconds |
| Started | Sep 18 07:54:26 PM UTC 24 |
| Finished | Sep 18 07:54:31 PM UTC 24 |
| Peak memory | 215552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479150460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3479150460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_aes.2375712493 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 33628364 ps |
| CPU time | 2.25 seconds |
| Started | Sep 18 07:54:26 PM UTC 24 |
| Finished | Sep 18 07:54:30 PM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375712493 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2375712493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_kmac.3641899962 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 460423764 ps |
| CPU time | 4.69 seconds |
| Started | Sep 18 07:54:26 PM UTC 24 |
| Finished | Sep 18 07:54:32 PM UTC 24 |
| Peak memory | 217636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641899962 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3641899962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_protect.3297648924 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 346941396 ps |
| CPU time | 2.24 seconds |
| Started | Sep 18 07:54:27 PM UTC 24 |
| Finished | Sep 18 07:54:38 PM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297648924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3297648924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/1.keymgr_smoke.3346701268 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 409532107 ps |
| CPU time | 4.9 seconds |
| Started | Sep 18 07:54:26 PM UTC 24 |
| Finished | Sep 18 07:54:32 PM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346701268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3346701268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/1.keymgr_sw_invalid_input.2750006261 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1100792774 ps |
| CPU time | 26.02 seconds |
| Started | Sep 18 07:54:27 PM UTC 24 |
| Finished | Sep 18 07:54:54 PM UTC 24 |
| Peak memory | 227496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750006261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2750006261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/1.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/10.keymgr_alert_test.2075510763 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 22623204 ps |
| CPU time | 0.9 seconds |
| Started | Sep 18 07:55:29 PM UTC 24 |
| Finished | Sep 18 07:55:32 PM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075510763 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2075510763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/10.keymgr_custom_cm.3886861638 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 68513574 ps |
| CPU time | 3.07 seconds |
| Started | Sep 18 07:55:27 PM UTC 24 |
| Finished | Sep 18 07:55:31 PM UTC 24 |
| Peak memory | 217536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886861638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3886861638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/10.keymgr_direct_to_disabled.1414988762 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 264812056 ps |
| CPU time | 4.81 seconds |
| Started | Sep 18 07:55:26 PM UTC 24 |
| Finished | Sep 18 07:55:32 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414988762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1414988762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/10.keymgr_kmac_rsp_err.2625549946 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 289480168 ps |
| CPU time | 4.16 seconds |
| Started | Sep 18 07:55:27 PM UTC 24 |
| Finished | Sep 18 07:55:32 PM UTC 24 |
| Peak memory | 223680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625549946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2625549946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/10.keymgr_lc_disable.2988140857 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 171888754 ps |
| CPU time | 4.43 seconds |
| Started | Sep 18 07:55:26 PM UTC 24 |
| Finished | Sep 18 07:55:32 PM UTC 24 |
| Peak memory | 217280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988140857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2988140857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/10.keymgr_random.229063304 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 74155766 ps |
| CPU time | 4.98 seconds |
| Started | Sep 18 07:55:26 PM UTC 24 |
| Finished | Sep 18 07:55:32 PM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229063304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.229063304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/10.keymgr_sideload.41478378 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 23668043 ps |
| CPU time | 2.48 seconds |
| Started | Sep 18 07:55:24 PM UTC 24 |
| Finished | Sep 18 07:55:28 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41478378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.41478378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_aes.4090545886 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 132457014 ps |
| CPU time | 2.71 seconds |
| Started | Sep 18 07:55:24 PM UTC 24 |
| Finished | Sep 18 07:55:28 PM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090545886 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.4090545886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_kmac.4029748478 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 3766740933 ps |
| CPU time | 36.16 seconds |
| Started | Sep 18 07:55:24 PM UTC 24 |
| Finished | Sep 18 07:56:02 PM UTC 24 |
| Peak memory | 217464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029748478 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.4029748478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_protect.3876763502 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 69027036 ps |
| CPU time | 2.85 seconds |
| Started | Sep 18 07:55:27 PM UTC 24 |
| Finished | Sep 18 07:55:31 PM UTC 24 |
| Peak memory | 223616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876763502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3876763502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/10.keymgr_smoke.3240674941 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 173101670 ps |
| CPU time | 3.81 seconds |
| Started | Sep 18 07:55:24 PM UTC 24 |
| Finished | Sep 18 07:55:29 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240674941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3240674941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all.3378543117 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 1695419535 ps |
| CPU time | 17.33 seconds |
| Started | Sep 18 07:55:28 PM UTC 24 |
| Finished | Sep 18 07:55:47 PM UTC 24 |
| Peak memory | 229620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378543117 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3378543117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/10.keymgr_sw_invalid_input.2356943859 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 354437027 ps |
| CPU time | 4.83 seconds |
| Started | Sep 18 07:55:26 PM UTC 24 |
| Finished | Sep 18 07:55:32 PM UTC 24 |
| Peak memory | 217508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356943859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2356943859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/11.keymgr_alert_test.2062863168 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 55941110 ps |
| CPU time | 1.1 seconds |
| Started | Sep 18 07:55:34 PM UTC 24 |
| Finished | Sep 18 07:55:36 PM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062863168 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2062863168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/11.keymgr_direct_to_disabled.824249237 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 351481904 ps |
| CPU time | 5.48 seconds |
| Started | Sep 18 07:55:31 PM UTC 24 |
| Finished | Sep 18 07:55:38 PM UTC 24 |
| Peak memory | 223396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824249237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.824249237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/11.keymgr_kmac_rsp_err.1850168572 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 358740151 ps |
| CPU time | 4.98 seconds |
| Started | Sep 18 07:55:32 PM UTC 24 |
| Finished | Sep 18 07:55:38 PM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850168572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1850168572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/11.keymgr_random.2907067238 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 627033588 ps |
| CPU time | 7.14 seconds |
| Started | Sep 18 07:55:31 PM UTC 24 |
| Finished | Sep 18 07:55:39 PM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907067238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2907067238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/11.keymgr_sideload.52141844 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 38506511 ps |
| CPU time | 2.93 seconds |
| Started | Sep 18 07:55:30 PM UTC 24 |
| Finished | Sep 18 07:55:34 PM UTC 24 |
| Peak memory | 215404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52141844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.52141844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_aes.1035025224 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 294238719 ps |
| CPU time | 3.9 seconds |
| Started | Sep 18 07:55:31 PM UTC 24 |
| Finished | Sep 18 07:55:36 PM UTC 24 |
| Peak memory | 217320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035025224 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1035025224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_kmac.4065094201 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 33179840208 ps |
| CPU time | 47.65 seconds |
| Started | Sep 18 07:55:30 PM UTC 24 |
| Finished | Sep 18 07:56:19 PM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065094201 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.4065094201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_otbn.1362125881 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 74675762 ps |
| CPU time | 5 seconds |
| Started | Sep 18 07:55:31 PM UTC 24 |
| Finished | Sep 18 07:55:37 PM UTC 24 |
| Peak memory | 217596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362125881 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1362125881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_protect.2469183196 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 127769081 ps |
| CPU time | 3.44 seconds |
| Started | Sep 18 07:55:32 PM UTC 24 |
| Finished | Sep 18 07:55:37 PM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469183196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2469183196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/11.keymgr_smoke.1847873594 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2652439897 ps |
| CPU time | 21.62 seconds |
| Started | Sep 18 07:55:30 PM UTC 24 |
| Finished | Sep 18 07:55:53 PM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847873594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1847873594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all.3307674792 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 839849334 ps |
| CPU time | 12.03 seconds |
| Started | Sep 18 07:55:34 PM UTC 24 |
| Finished | Sep 18 07:55:47 PM UTC 24 |
| Peak memory | 227568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307674792 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3307674792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all_with_rand_reset.3528674409 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 155287776 ps |
| CPU time | 12.06 seconds |
| Started | Sep 18 07:55:34 PM UTC 24 |
| Finished | Sep 18 07:55:47 PM UTC 24 |
| Peak memory | 231660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3528674409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymg r_stress_all_with_rand_reset.3528674409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/11.keymgr_sw_invalid_input.2388853590 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 90034508 ps |
| CPU time | 5.5 seconds |
| Started | Sep 18 07:55:32 PM UTC 24 |
| Finished | Sep 18 07:55:39 PM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388853590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2388853590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/11.keymgr_sync_async_fault_cross.2207716667 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 576416281 ps |
| CPU time | 7.13 seconds |
| Started | Sep 18 07:55:32 PM UTC 24 |
| Finished | Sep 18 07:55:41 PM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207716667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2207716667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/11.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/12.keymgr_alert_test.1176140087 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 50650042 ps |
| CPU time | 1.42 seconds |
| Started | Sep 18 07:55:41 PM UTC 24 |
| Finished | Sep 18 07:55:44 PM UTC 24 |
| Peak memory | 212796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176140087 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1176140087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/12.keymgr_cfg_regwen.1232691512 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 92237790 ps |
| CPU time | 5.08 seconds |
| Started | Sep 18 07:55:41 PM UTC 24 |
| Finished | Sep 18 07:55:47 PM UTC 24 |
| Peak memory | 225736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232691512 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1232691512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/12.keymgr_direct_to_disabled.1311059958 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 7004708714 ps |
| CPU time | 41.01 seconds |
| Started | Sep 18 07:55:41 PM UTC 24 |
| Finished | Sep 18 07:56:23 PM UTC 24 |
| Peak memory | 223784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311059958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1311059958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/12.keymgr_kmac_rsp_err.2656857114 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 287048561 ps |
| CPU time | 4.44 seconds |
| Started | Sep 18 07:55:41 PM UTC 24 |
| Finished | Sep 18 07:55:47 PM UTC 24 |
| Peak memory | 231476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656857114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2656857114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/12.keymgr_lc_disable.3728499990 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 46974335 ps |
| CPU time | 3.73 seconds |
| Started | Sep 18 07:55:41 PM UTC 24 |
| Finished | Sep 18 07:55:46 PM UTC 24 |
| Peak memory | 217268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728499990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3728499990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/12.keymgr_random.2814610622 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 183841808 ps |
| CPU time | 8.76 seconds |
| Started | Sep 18 07:55:41 PM UTC 24 |
| Finished | Sep 18 07:55:51 PM UTC 24 |
| Peak memory | 227564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814610622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2814610622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/12.keymgr_sideload.2898982764 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 1219715124 ps |
| CPU time | 5.84 seconds |
| Started | Sep 18 07:55:35 PM UTC 24 |
| Finished | Sep 18 07:55:42 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898982764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2898982764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_aes.553350396 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 791272831 ps |
| CPU time | 7.62 seconds |
| Started | Sep 18 07:55:41 PM UTC 24 |
| Finished | Sep 18 07:55:50 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553350396 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.553350396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_kmac.373399017 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 155682255 ps |
| CPU time | 3.23 seconds |
| Started | Sep 18 07:55:40 PM UTC 24 |
| Finished | Sep 18 07:55:44 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373399017 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.373399017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_otbn.2512013017 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 199271536 ps |
| CPU time | 4.2 seconds |
| Started | Sep 18 07:55:41 PM UTC 24 |
| Finished | Sep 18 07:55:46 PM UTC 24 |
| Peak memory | 215496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512013017 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2512013017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_protect.4151973977 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 109487976 ps |
| CPU time | 2.44 seconds |
| Started | Sep 18 07:55:41 PM UTC 24 |
| Finished | Sep 18 07:55:45 PM UTC 24 |
| Peak memory | 223488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151973977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.4151973977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/12.keymgr_smoke.455808065 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 278348292 ps |
| CPU time | 3.91 seconds |
| Started | Sep 18 07:55:35 PM UTC 24 |
| Finished | Sep 18 07:55:40 PM UTC 24 |
| Peak memory | 217264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455808065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.455808065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/12.keymgr_stress_all.3883380661 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 116996808 ps |
| CPU time | 7.02 seconds |
| Started | Sep 18 07:55:41 PM UTC 24 |
| Finished | Sep 18 07:55:50 PM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883380661 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3883380661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/12.keymgr_sw_invalid_input.4127151192 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 20855754017 ps |
| CPU time | 87.31 seconds |
| Started | Sep 18 07:55:41 PM UTC 24 |
| Finished | Sep 18 07:57:10 PM UTC 24 |
| Peak memory | 229872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127151192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.4127151192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/12.keymgr_sync_async_fault_cross.1538151940 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 44438168 ps |
| CPU time | 2.97 seconds |
| Started | Sep 18 07:55:41 PM UTC 24 |
| Finished | Sep 18 07:55:45 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538151940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1538151940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/12.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/13.keymgr_alert_test.2470142999 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 16950968 ps |
| CPU time | 1.26 seconds |
| Started | Sep 18 07:55:48 PM UTC 24 |
| Finished | Sep 18 07:55:50 PM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470142999 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2470142999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/13.keymgr_cfg_regwen.512844714 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 388815122 ps |
| CPU time | 3.31 seconds |
| Started | Sep 18 07:55:45 PM UTC 24 |
| Finished | Sep 18 07:55:49 PM UTC 24 |
| Peak memory | 225784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512844714 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.512844714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/13.keymgr_custom_cm.2791573118 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 42562649 ps |
| CPU time | 2.5 seconds |
| Started | Sep 18 07:55:47 PM UTC 24 |
| Finished | Sep 18 07:55:51 PM UTC 24 |
| Peak memory | 217272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791573118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2791573118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/13.keymgr_direct_to_disabled.1004254630 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 67918479 ps |
| CPU time | 2.05 seconds |
| Started | Sep 18 07:55:46 PM UTC 24 |
| Finished | Sep 18 07:55:49 PM UTC 24 |
| Peak memory | 215052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004254630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1004254630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/13.keymgr_hwsw_invalid_input.4044023858 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 112780994 ps |
| CPU time | 3.64 seconds |
| Started | Sep 18 07:55:47 PM UTC 24 |
| Finished | Sep 18 07:55:52 PM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044023858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.4044023858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/13.keymgr_kmac_rsp_err.3328746907 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 348695467 ps |
| CPU time | 5.41 seconds |
| Started | Sep 18 07:55:47 PM UTC 24 |
| Finished | Sep 18 07:55:54 PM UTC 24 |
| Peak memory | 223428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328746907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3328746907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/13.keymgr_lc_disable.2736997450 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 106891885 ps |
| CPU time | 5.07 seconds |
| Started | Sep 18 07:55:46 PM UTC 24 |
| Finished | Sep 18 07:55:52 PM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736997450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2736997450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/13.keymgr_random.2074734262 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 482853642 ps |
| CPU time | 9.06 seconds |
| Started | Sep 18 07:55:45 PM UTC 24 |
| Finished | Sep 18 07:55:55 PM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074734262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2074734262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/13.keymgr_sideload.1809248543 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 328900334 ps |
| CPU time | 2.58 seconds |
| Started | Sep 18 07:55:43 PM UTC 24 |
| Finished | Sep 18 07:55:46 PM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809248543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1809248543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_aes.3688047124 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 117183119 ps |
| CPU time | 4.82 seconds |
| Started | Sep 18 07:55:43 PM UTC 24 |
| Finished | Sep 18 07:55:49 PM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688047124 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3688047124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_kmac.931861799 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 379760629 ps |
| CPU time | 8 seconds |
| Started | Sep 18 07:55:43 PM UTC 24 |
| Finished | Sep 18 07:55:52 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931861799 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.931861799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_otbn.4165388157 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 126326346 ps |
| CPU time | 5.18 seconds |
| Started | Sep 18 07:55:43 PM UTC 24 |
| Finished | Sep 18 07:55:49 PM UTC 24 |
| Peak memory | 217468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165388157 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.4165388157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_protect.1863135700 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 321328930 ps |
| CPU time | 4.39 seconds |
| Started | Sep 18 07:55:47 PM UTC 24 |
| Finished | Sep 18 07:55:53 PM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863135700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1863135700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/13.keymgr_smoke.1864303598 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 22630665 ps |
| CPU time | 2.81 seconds |
| Started | Sep 18 07:55:43 PM UTC 24 |
| Finished | Sep 18 07:55:46 PM UTC 24 |
| Peak memory | 217456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864303598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1864303598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all.1595565289 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 243557850 ps |
| CPU time | 5.81 seconds |
| Started | Sep 18 07:55:47 PM UTC 24 |
| Finished | Sep 18 07:55:54 PM UTC 24 |
| Peak memory | 217628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595565289 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1595565289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/13.keymgr_sw_invalid_input.2420125576 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 293557742 ps |
| CPU time | 9.82 seconds |
| Started | Sep 18 07:55:46 PM UTC 24 |
| Finished | Sep 18 07:55:57 PM UTC 24 |
| Peak memory | 223220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420125576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2420125576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/13.keymgr_sync_async_fault_cross.3619769155 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 59500252 ps |
| CPU time | 1.63 seconds |
| Started | Sep 18 07:55:47 PM UTC 24 |
| Finished | Sep 18 07:55:50 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619769155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3619769155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/13.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/14.keymgr_alert_test.1526795875 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 103229139 ps |
| CPU time | 1.45 seconds |
| Started | Sep 18 07:55:54 PM UTC 24 |
| Finished | Sep 18 07:55:56 PM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526795875 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1526795875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/14.keymgr_cfg_regwen.2493552316 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 1660904391 ps |
| CPU time | 71.6 seconds |
| Started | Sep 18 07:55:51 PM UTC 24 |
| Finished | Sep 18 07:57:05 PM UTC 24 |
| Peak memory | 225848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493552316 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2493552316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/14.keymgr_custom_cm.3055541719 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 244161691 ps |
| CPU time | 3.66 seconds |
| Started | Sep 18 07:55:52 PM UTC 24 |
| Finished | Sep 18 07:55:57 PM UTC 24 |
| Peak memory | 217416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055541719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3055541719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/14.keymgr_direct_to_disabled.1031338641 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 62367318 ps |
| CPU time | 2.01 seconds |
| Started | Sep 18 07:55:51 PM UTC 24 |
| Finished | Sep 18 07:55:54 PM UTC 24 |
| Peak memory | 214816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031338641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1031338641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/14.keymgr_kmac_rsp_err.1134620112 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 54893718 ps |
| CPU time | 2.71 seconds |
| Started | Sep 18 07:55:52 PM UTC 24 |
| Finished | Sep 18 07:55:56 PM UTC 24 |
| Peak memory | 223428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134620112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1134620112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/14.keymgr_lc_disable.4058438585 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 143741470 ps |
| CPU time | 2.76 seconds |
| Started | Sep 18 07:55:51 PM UTC 24 |
| Finished | Sep 18 07:55:55 PM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058438585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.4058438585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/14.keymgr_random.1302925270 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 1769655811 ps |
| CPU time | 18.29 seconds |
| Started | Sep 18 07:55:50 PM UTC 24 |
| Finished | Sep 18 07:56:09 PM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302925270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1302925270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/14.keymgr_sideload.2343820950 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 99738497 ps |
| CPU time | 2.84 seconds |
| Started | Sep 18 07:55:49 PM UTC 24 |
| Finished | Sep 18 07:55:53 PM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343820950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2343820950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_aes.3997679310 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 123638490 ps |
| CPU time | 3.94 seconds |
| Started | Sep 18 07:55:50 PM UTC 24 |
| Finished | Sep 18 07:55:55 PM UTC 24 |
| Peak memory | 217200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997679310 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3997679310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_kmac.2444988824 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 99314988 ps |
| CPU time | 4.1 seconds |
| Started | Sep 18 07:55:50 PM UTC 24 |
| Finished | Sep 18 07:55:55 PM UTC 24 |
| Peak memory | 215316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444988824 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2444988824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_otbn.761588001 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 89764815 ps |
| CPU time | 3.09 seconds |
| Started | Sep 18 07:55:50 PM UTC 24 |
| Finished | Sep 18 07:55:54 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761588001 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.761588001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_protect.3607448378 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 271584056 ps |
| CPU time | 4.07 seconds |
| Started | Sep 18 07:55:53 PM UTC 24 |
| Finished | Sep 18 07:55:58 PM UTC 24 |
| Peak memory | 217420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607448378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3607448378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/14.keymgr_smoke.2131612321 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 237548743 ps |
| CPU time | 3.24 seconds |
| Started | Sep 18 07:55:49 PM UTC 24 |
| Finished | Sep 18 07:55:53 PM UTC 24 |
| Peak memory | 217264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131612321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2131612321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all_with_rand_reset.196723585 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1196449328 ps |
| CPU time | 23.91 seconds |
| Started | Sep 18 07:55:54 PM UTC 24 |
| Finished | Sep 18 07:56:19 PM UTC 24 |
| Peak memory | 231600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=196723585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr _stress_all_with_rand_reset.196723585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/14.keymgr_sw_invalid_input.753274692 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 2317115642 ps |
| CPU time | 21.27 seconds |
| Started | Sep 18 07:55:51 PM UTC 24 |
| Finished | Sep 18 07:56:14 PM UTC 24 |
| Peak memory | 215340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753274692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.753274692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/14.keymgr_sync_async_fault_cross.3546400219 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 71118322 ps |
| CPU time | 2.83 seconds |
| Started | Sep 18 07:55:53 PM UTC 24 |
| Finished | Sep 18 07:55:56 PM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546400219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3546400219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/14.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/15.keymgr_alert_test.3729828961 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 52013679 ps |
| CPU time | 0.81 seconds |
| Started | Sep 18 07:56:06 PM UTC 24 |
| Finished | Sep 18 07:56:08 PM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729828961 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3729828961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/15.keymgr_cfg_regwen.2605525588 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 243957437 ps |
| CPU time | 4.32 seconds |
| Started | Sep 18 07:55:55 PM UTC 24 |
| Finished | Sep 18 07:56:01 PM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605525588 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2605525588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/15.keymgr_custom_cm.1743753956 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 80330436 ps |
| CPU time | 3.73 seconds |
| Started | Sep 18 07:55:57 PM UTC 24 |
| Finished | Sep 18 07:56:02 PM UTC 24 |
| Peak memory | 217292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743753956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1743753956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/15.keymgr_direct_to_disabled.184213727 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 149828685 ps |
| CPU time | 1.93 seconds |
| Started | Sep 18 07:55:55 PM UTC 24 |
| Finished | Sep 18 07:55:58 PM UTC 24 |
| Peak memory | 215416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184213727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.184213727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/15.keymgr_hwsw_invalid_input.1852950334 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 132590086 ps |
| CPU time | 5.69 seconds |
| Started | Sep 18 07:55:57 PM UTC 24 |
| Finished | Sep 18 07:56:04 PM UTC 24 |
| Peak memory | 229964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852950334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1852950334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/15.keymgr_kmac_rsp_err.2628342711 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 427063000 ps |
| CPU time | 2.64 seconds |
| Started | Sep 18 07:55:57 PM UTC 24 |
| Finished | Sep 18 07:56:01 PM UTC 24 |
| Peak memory | 223488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628342711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2628342711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/15.keymgr_lc_disable.3693295890 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 88190968 ps |
| CPU time | 3.71 seconds |
| Started | Sep 18 07:55:55 PM UTC 24 |
| Finished | Sep 18 07:56:00 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693295890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3693295890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/15.keymgr_random.4111567664 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 232662043 ps |
| CPU time | 6.82 seconds |
| Started | Sep 18 07:55:55 PM UTC 24 |
| Finished | Sep 18 07:56:03 PM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111567664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.4111567664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/15.keymgr_sideload.825765269 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 1125539809 ps |
| CPU time | 8.69 seconds |
| Started | Sep 18 07:55:54 PM UTC 24 |
| Finished | Sep 18 07:56:04 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825765269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.825765269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_aes.2850116072 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 35244159 ps |
| CPU time | 3.45 seconds |
| Started | Sep 18 07:55:54 PM UTC 24 |
| Finished | Sep 18 07:55:59 PM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850116072 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2850116072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_kmac.3494076982 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 925641670 ps |
| CPU time | 23.28 seconds |
| Started | Sep 18 07:55:54 PM UTC 24 |
| Finished | Sep 18 07:56:19 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494076982 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3494076982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_otbn.438309478 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 229330504 ps |
| CPU time | 4.53 seconds |
| Started | Sep 18 07:55:55 PM UTC 24 |
| Finished | Sep 18 07:56:01 PM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438309478 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.438309478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/15.keymgr_smoke.396646553 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 82775460 ps |
| CPU time | 2.86 seconds |
| Started | Sep 18 07:55:54 PM UTC 24 |
| Finished | Sep 18 07:55:58 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396646553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.396646553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all.2001195783 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 511947622 ps |
| CPU time | 8.33 seconds |
| Started | Sep 18 07:56:06 PM UTC 24 |
| Finished | Sep 18 07:56:15 PM UTC 24 |
| Peak memory | 225784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001195783 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2001195783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/15.keymgr_sw_invalid_input.673431662 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 135891594 ps |
| CPU time | 3.82 seconds |
| Started | Sep 18 07:55:57 PM UTC 24 |
| Finished | Sep 18 07:56:02 PM UTC 24 |
| Peak memory | 215196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673431662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.673431662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/15.keymgr_sync_async_fault_cross.2388476817 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 499592382 ps |
| CPU time | 4.56 seconds |
| Started | Sep 18 07:56:06 PM UTC 24 |
| Finished | Sep 18 07:56:12 PM UTC 24 |
| Peak memory | 217276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388476817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2388476817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/15.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/16.keymgr_alert_test.1641844066 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 270795682 ps |
| CPU time | 1.42 seconds |
| Started | Sep 18 07:56:08 PM UTC 24 |
| Finished | Sep 18 07:56:10 PM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641844066 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1641844066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/16.keymgr_custom_cm.1074015594 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 533792710 ps |
| CPU time | 6.7 seconds |
| Started | Sep 18 07:56:07 PM UTC 24 |
| Finished | Sep 18 07:56:15 PM UTC 24 |
| Peak memory | 217264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074015594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1074015594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/16.keymgr_direct_to_disabled.4009789238 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 239635835 ps |
| CPU time | 2.48 seconds |
| Started | Sep 18 07:56:07 PM UTC 24 |
| Finished | Sep 18 07:56:11 PM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009789238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.4009789238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/16.keymgr_kmac_rsp_err.1308471713 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 199181485 ps |
| CPU time | 3.77 seconds |
| Started | Sep 18 07:56:07 PM UTC 24 |
| Finished | Sep 18 07:56:13 PM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308471713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1308471713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/16.keymgr_lc_disable.818209376 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 282475199 ps |
| CPU time | 4.47 seconds |
| Started | Sep 18 07:56:07 PM UTC 24 |
| Finished | Sep 18 07:56:13 PM UTC 24 |
| Peak memory | 223568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818209376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.818209376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/16.keymgr_random.2457170331 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 293735779 ps |
| CPU time | 9.91 seconds |
| Started | Sep 18 07:56:07 PM UTC 24 |
| Finished | Sep 18 07:56:19 PM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457170331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2457170331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/16.keymgr_sideload.1131573186 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 289458872 ps |
| CPU time | 3.53 seconds |
| Started | Sep 18 07:56:06 PM UTC 24 |
| Finished | Sep 18 07:56:11 PM UTC 24 |
| Peak memory | 217408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131573186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1131573186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_aes.947571999 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 478341182 ps |
| CPU time | 7.53 seconds |
| Started | Sep 18 07:56:07 PM UTC 24 |
| Finished | Sep 18 07:56:16 PM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947571999 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.947571999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_kmac.996678554 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 166107627 ps |
| CPU time | 3.16 seconds |
| Started | Sep 18 07:56:07 PM UTC 24 |
| Finished | Sep 18 07:56:12 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996678554 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.996678554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_otbn.621428535 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 395856356 ps |
| CPU time | 5.38 seconds |
| Started | Sep 18 07:56:07 PM UTC 24 |
| Finished | Sep 18 07:56:14 PM UTC 24 |
| Peak memory | 217660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621428535 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.621428535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_protect.2645926859 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 62675017 ps |
| CPU time | 2.3 seconds |
| Started | Sep 18 07:56:07 PM UTC 24 |
| Finished | Sep 18 07:56:11 PM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645926859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2645926859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/16.keymgr_smoke.4091409825 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 174469933 ps |
| CPU time | 3.01 seconds |
| Started | Sep 18 07:56:06 PM UTC 24 |
| Finished | Sep 18 07:56:10 PM UTC 24 |
| Peak memory | 217188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091409825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.4091409825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/16.keymgr_stress_all.3811911894 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 2367594101 ps |
| CPU time | 40.34 seconds |
| Started | Sep 18 07:56:08 PM UTC 24 |
| Finished | Sep 18 07:56:50 PM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811911894 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3811911894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/16.keymgr_sw_invalid_input.502988733 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 126529306 ps |
| CPU time | 4.79 seconds |
| Started | Sep 18 07:56:07 PM UTC 24 |
| Finished | Sep 18 07:56:13 PM UTC 24 |
| Peak memory | 223388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502988733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.502988733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/16.keymgr_sync_async_fault_cross.675577251 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 1774976460 ps |
| CPU time | 5.8 seconds |
| Started | Sep 18 07:56:07 PM UTC 24 |
| Finished | Sep 18 07:56:15 PM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675577251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.675577251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/16.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/17.keymgr_alert_test.4186745156 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 33198763 ps |
| CPU time | 1.25 seconds |
| Started | Sep 18 07:56:16 PM UTC 24 |
| Finished | Sep 18 07:56:18 PM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186745156 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.4186745156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/17.keymgr_custom_cm.2946154238 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 109913379 ps |
| CPU time | 3.34 seconds |
| Started | Sep 18 07:56:14 PM UTC 24 |
| Finished | Sep 18 07:56:19 PM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946154238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2946154238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/17.keymgr_hwsw_invalid_input.3263818004 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1511641803 ps |
| CPU time | 5.53 seconds |
| Started | Sep 18 07:56:14 PM UTC 24 |
| Finished | Sep 18 07:56:21 PM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263818004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3263818004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/17.keymgr_kmac_rsp_err.2707005535 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 153509587 ps |
| CPU time | 6.56 seconds |
| Started | Sep 18 07:56:14 PM UTC 24 |
| Finished | Sep 18 07:56:22 PM UTC 24 |
| Peak memory | 223340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707005535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2707005535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/17.keymgr_lc_disable.3681262765 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 162178835 ps |
| CPU time | 2.98 seconds |
| Started | Sep 18 07:56:12 PM UTC 24 |
| Finished | Sep 18 07:56:16 PM UTC 24 |
| Peak memory | 229620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681262765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3681262765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/17.keymgr_random.1716919091 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 103092192 ps |
| CPU time | 3.71 seconds |
| Started | Sep 18 07:56:12 PM UTC 24 |
| Finished | Sep 18 07:56:17 PM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716919091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1716919091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/17.keymgr_sideload.766709634 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 188273521 ps |
| CPU time | 3.32 seconds |
| Started | Sep 18 07:56:11 PM UTC 24 |
| Finished | Sep 18 07:56:15 PM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766709634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.766709634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_aes.1464049581 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 58849480 ps |
| CPU time | 3.29 seconds |
| Started | Sep 18 07:56:11 PM UTC 24 |
| Finished | Sep 18 07:56:15 PM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464049581 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1464049581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_kmac.4262765529 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 50079778 ps |
| CPU time | 2.95 seconds |
| Started | Sep 18 07:56:11 PM UTC 24 |
| Finished | Sep 18 07:56:15 PM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262765529 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.4262765529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_otbn.3359949477 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 171764653 ps |
| CPU time | 4.74 seconds |
| Started | Sep 18 07:56:12 PM UTC 24 |
| Finished | Sep 18 07:56:18 PM UTC 24 |
| Peak memory | 215404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359949477 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3359949477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_protect.814762149 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 405458428 ps |
| CPU time | 10.44 seconds |
| Started | Sep 18 07:56:15 PM UTC 24 |
| Finished | Sep 18 07:56:26 PM UTC 24 |
| Peak memory | 217248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814762149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.814762149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/17.keymgr_smoke.1210127112 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 1676876728 ps |
| CPU time | 27.09 seconds |
| Started | Sep 18 07:56:09 PM UTC 24 |
| Finished | Sep 18 07:56:37 PM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210127112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1210127112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all.1730200013 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 481313548 ps |
| CPU time | 18.58 seconds |
| Started | Sep 18 07:56:16 PM UTC 24 |
| Finished | Sep 18 07:56:36 PM UTC 24 |
| Peak memory | 229636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730200013 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1730200013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/17.keymgr_sw_invalid_input.608138335 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 150529749 ps |
| CPU time | 6.26 seconds |
| Started | Sep 18 07:56:13 PM UTC 24 |
| Finished | Sep 18 07:56:21 PM UTC 24 |
| Peak memory | 217384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608138335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.608138335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/17.keymgr_sync_async_fault_cross.2975776898 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 37700461 ps |
| CPU time | 2.04 seconds |
| Started | Sep 18 07:56:16 PM UTC 24 |
| Finished | Sep 18 07:56:19 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975776898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2975776898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/17.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/18.keymgr_alert_test.2545682850 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 42005480 ps |
| CPU time | 1.23 seconds |
| Started | Sep 18 07:56:20 PM UTC 24 |
| Finished | Sep 18 07:56:22 PM UTC 24 |
| Peak memory | 212832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545682850 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2545682850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/18.keymgr_cfg_regwen.4222879385 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 38084794 ps |
| CPU time | 2.98 seconds |
| Started | Sep 18 07:56:17 PM UTC 24 |
| Finished | Sep 18 07:56:21 PM UTC 24 |
| Peak memory | 225396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222879385 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.4222879385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/18.keymgr_custom_cm.1032573548 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 47688850 ps |
| CPU time | 3.31 seconds |
| Started | Sep 18 07:56:20 PM UTC 24 |
| Finished | Sep 18 07:56:24 PM UTC 24 |
| Peak memory | 217416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032573548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1032573548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/18.keymgr_direct_to_disabled.1413085341 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 60732470 ps |
| CPU time | 3.64 seconds |
| Started | Sep 18 07:56:17 PM UTC 24 |
| Finished | Sep 18 07:56:22 PM UTC 24 |
| Peak memory | 219452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413085341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1413085341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/18.keymgr_hwsw_invalid_input.4245671272 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 461754562 ps |
| CPU time | 3.88 seconds |
| Started | Sep 18 07:56:19 PM UTC 24 |
| Finished | Sep 18 07:56:24 PM UTC 24 |
| Peak memory | 225536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245671272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.4245671272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/18.keymgr_lc_disable.3006053272 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 111301559 ps |
| CPU time | 5.9 seconds |
| Started | Sep 18 07:56:18 PM UTC 24 |
| Finished | Sep 18 07:56:26 PM UTC 24 |
| Peak memory | 231816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006053272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3006053272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/18.keymgr_random.3349127855 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1353374579 ps |
| CPU time | 7.51 seconds |
| Started | Sep 18 07:56:17 PM UTC 24 |
| Finished | Sep 18 07:56:26 PM UTC 24 |
| Peak memory | 227264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349127855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3349127855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/18.keymgr_sideload.3722991624 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 424961026 ps |
| CPU time | 2.74 seconds |
| Started | Sep 18 07:56:16 PM UTC 24 |
| Finished | Sep 18 07:56:20 PM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722991624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3722991624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_aes.695988333 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 349089596 ps |
| CPU time | 5.48 seconds |
| Started | Sep 18 07:56:17 PM UTC 24 |
| Finished | Sep 18 07:56:24 PM UTC 24 |
| Peak memory | 214820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695988333 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.695988333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_kmac.1610581350 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 159078467 ps |
| CPU time | 3.84 seconds |
| Started | Sep 18 07:56:16 PM UTC 24 |
| Finished | Sep 18 07:56:21 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610581350 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1610581350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_otbn.316692021 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 3001604953 ps |
| CPU time | 21.07 seconds |
| Started | Sep 18 07:56:17 PM UTC 24 |
| Finished | Sep 18 07:56:40 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316692021 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.316692021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_protect.378392898 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 5532447140 ps |
| CPU time | 21.94 seconds |
| Started | Sep 18 07:56:20 PM UTC 24 |
| Finished | Sep 18 07:56:43 PM UTC 24 |
| Peak memory | 227696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378392898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.378392898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/18.keymgr_smoke.1893893577 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 540495181 ps |
| CPU time | 3.82 seconds |
| Started | Sep 18 07:56:16 PM UTC 24 |
| Finished | Sep 18 07:56:21 PM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893893577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1893893577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all_with_rand_reset.1718088983 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 598684298 ps |
| CPU time | 23.46 seconds |
| Started | Sep 18 07:56:20 PM UTC 24 |
| Finished | Sep 18 07:56:45 PM UTC 24 |
| Peak memory | 231456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1718088983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymg r_stress_all_with_rand_reset.1718088983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/18.keymgr_sw_invalid_input.3570680491 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 359955300 ps |
| CPU time | 5.96 seconds |
| Started | Sep 18 07:56:18 PM UTC 24 |
| Finished | Sep 18 07:56:26 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570680491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3570680491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/18.keymgr_sync_async_fault_cross.2756634872 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 67289217 ps |
| CPU time | 2.36 seconds |
| Started | Sep 18 07:56:20 PM UTC 24 |
| Finished | Sep 18 07:56:23 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756634872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2756634872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/18.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/19.keymgr_alert_test.642688137 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 133670713 ps |
| CPU time | 1.15 seconds |
| Started | Sep 18 07:56:32 PM UTC 24 |
| Finished | Sep 18 07:56:35 PM UTC 24 |
| Peak memory | 212892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642688137 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.642688137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/19.keymgr_direct_to_disabled.119107199 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 232154167 ps |
| CPU time | 3.53 seconds |
| Started | Sep 18 07:56:24 PM UTC 24 |
| Finished | Sep 18 07:56:28 PM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119107199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.119107199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/19.keymgr_hwsw_invalid_input.3297950493 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 119043493 ps |
| CPU time | 6.2 seconds |
| Started | Sep 18 07:56:25 PM UTC 24 |
| Finished | Sep 18 07:56:32 PM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297950493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3297950493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/19.keymgr_kmac_rsp_err.4244211976 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 229571740 ps |
| CPU time | 6.4 seconds |
| Started | Sep 18 07:56:25 PM UTC 24 |
| Finished | Sep 18 07:56:32 PM UTC 24 |
| Peak memory | 225388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244211976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.4244211976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/19.keymgr_lc_disable.726861336 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 439352756 ps |
| CPU time | 3.11 seconds |
| Started | Sep 18 07:56:24 PM UTC 24 |
| Finished | Sep 18 07:56:28 PM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726861336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.726861336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/19.keymgr_random.1400163297 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 152378172 ps |
| CPU time | 6.25 seconds |
| Started | Sep 18 07:56:22 PM UTC 24 |
| Finished | Sep 18 07:56:30 PM UTC 24 |
| Peak memory | 223428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400163297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1400163297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/19.keymgr_sideload.1839426581 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 133383509 ps |
| CPU time | 4.49 seconds |
| Started | Sep 18 07:56:21 PM UTC 24 |
| Finished | Sep 18 07:56:27 PM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839426581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1839426581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_aes.2400268277 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 57982267 ps |
| CPU time | 2.92 seconds |
| Started | Sep 18 07:56:22 PM UTC 24 |
| Finished | Sep 18 07:56:26 PM UTC 24 |
| Peak memory | 217384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400268277 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2400268277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_kmac.3386973199 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 153372532 ps |
| CPU time | 5.41 seconds |
| Started | Sep 18 07:56:21 PM UTC 24 |
| Finished | Sep 18 07:56:28 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386973199 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3386973199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_otbn.3641218212 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 116181634 ps |
| CPU time | 3.21 seconds |
| Started | Sep 18 07:56:22 PM UTC 24 |
| Finished | Sep 18 07:56:27 PM UTC 24 |
| Peak memory | 217404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641218212 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3641218212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_protect.3167260080 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 116830969 ps |
| CPU time | 3.8 seconds |
| Started | Sep 18 07:56:25 PM UTC 24 |
| Finished | Sep 18 07:56:30 PM UTC 24 |
| Peak memory | 223500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167260080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3167260080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/19.keymgr_smoke.807619620 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 72641922 ps |
| CPU time | 3.41 seconds |
| Started | Sep 18 07:56:20 PM UTC 24 |
| Finished | Sep 18 07:56:25 PM UTC 24 |
| Peak memory | 215292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807619620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.807619620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/19.keymgr_stress_all.2632992082 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 102101878 ps |
| CPU time | 4.28 seconds |
| Started | Sep 18 07:56:25 PM UTC 24 |
| Finished | Sep 18 07:56:30 PM UTC 24 |
| Peak memory | 217264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632992082 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2632992082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/19.keymgr_stress_all_with_rand_reset.3321134653 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1117058410 ps |
| CPU time | 11.27 seconds |
| Started | Sep 18 07:56:25 PM UTC 24 |
| Finished | Sep 18 07:56:38 PM UTC 24 |
| Peak memory | 231856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3321134653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymg r_stress_all_with_rand_reset.3321134653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/19.keymgr_sw_invalid_input.1941226249 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 38404301 ps |
| CPU time | 2.49 seconds |
| Started | Sep 18 07:56:24 PM UTC 24 |
| Finished | Sep 18 07:56:27 PM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941226249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1941226249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/19.keymgr_sync_async_fault_cross.3833282877 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 88028205 ps |
| CPU time | 2.81 seconds |
| Started | Sep 18 07:56:25 PM UTC 24 |
| Finished | Sep 18 07:56:29 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833282877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3833282877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/19.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/2.keymgr_alert_test.273225643 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 72799329 ps |
| CPU time | 1.25 seconds |
| Started | Sep 18 07:54:37 PM UTC 24 |
| Finished | Sep 18 07:54:39 PM UTC 24 |
| Peak memory | 212772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273225643 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.273225643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/2.keymgr_custom_cm.3500230901 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 80954014 ps |
| CPU time | 3.85 seconds |
| Started | Sep 18 07:54:32 PM UTC 24 |
| Finished | Sep 18 07:54:38 PM UTC 24 |
| Peak memory | 223888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500230901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3500230901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/2.keymgr_direct_to_disabled.3556163442 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 128230904 ps |
| CPU time | 2.05 seconds |
| Started | Sep 18 07:54:32 PM UTC 24 |
| Finished | Sep 18 07:54:35 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556163442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3556163442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/2.keymgr_hwsw_invalid_input.2800676794 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 106136384 ps |
| CPU time | 4.66 seconds |
| Started | Sep 18 07:54:32 PM UTC 24 |
| Finished | Sep 18 07:54:38 PM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800676794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2800676794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/2.keymgr_kmac_rsp_err.682583606 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 104539877 ps |
| CPU time | 2.89 seconds |
| Started | Sep 18 07:54:32 PM UTC 24 |
| Finished | Sep 18 07:54:36 PM UTC 24 |
| Peak memory | 230768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682583606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.682583606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/2.keymgr_lc_disable.3518152698 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 340586540 ps |
| CPU time | 17.32 seconds |
| Started | Sep 18 07:54:32 PM UTC 24 |
| Finished | Sep 18 07:54:51 PM UTC 24 |
| Peak memory | 231644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518152698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3518152698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/2.keymgr_random.3934827673 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 155482777 ps |
| CPU time | 3.31 seconds |
| Started | Sep 18 07:54:32 PM UTC 24 |
| Finished | Sep 18 07:54:37 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934827673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3934827673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/2.keymgr_sec_cm.2156721057 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1500875992 ps |
| CPU time | 9.67 seconds |
| Started | Sep 18 07:54:37 PM UTC 24 |
| Finished | Sep 18 07:54:48 PM UTC 24 |
| Peak memory | 259332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156721057 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2156721057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/2.keymgr_sideload.991062022 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 30541060 ps |
| CPU time | 1.83 seconds |
| Started | Sep 18 07:54:31 PM UTC 24 |
| Finished | Sep 18 07:54:35 PM UTC 24 |
| Peak memory | 214820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991062022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.991062022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_aes.3344959242 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 55457049 ps |
| CPU time | 2.29 seconds |
| Started | Sep 18 07:54:32 PM UTC 24 |
| Finished | Sep 18 07:54:35 PM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344959242 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3344959242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_kmac.1964994120 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 40476462 ps |
| CPU time | 2.35 seconds |
| Started | Sep 18 07:54:31 PM UTC 24 |
| Finished | Sep 18 07:54:35 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964994120 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1964994120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_otbn.1827014967 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 189305806 ps |
| CPU time | 3.76 seconds |
| Started | Sep 18 07:54:32 PM UTC 24 |
| Finished | Sep 18 07:54:37 PM UTC 24 |
| Peak memory | 217596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827014967 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1827014967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_protect.483973411 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 277168020 ps |
| CPU time | 2.96 seconds |
| Started | Sep 18 07:54:34 PM UTC 24 |
| Finished | Sep 18 07:54:39 PM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483973411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.483973411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/2.keymgr_smoke.4157395456 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 223297274 ps |
| CPU time | 2.9 seconds |
| Started | Sep 18 07:54:31 PM UTC 24 |
| Finished | Sep 18 07:54:36 PM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157395456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.4157395456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/2.keymgr_sw_invalid_input.4059514541 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 30401822 ps |
| CPU time | 2.73 seconds |
| Started | Sep 18 07:54:32 PM UTC 24 |
| Finished | Sep 18 07:54:36 PM UTC 24 |
| Peak memory | 215612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059514541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.4059514541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/2.keymgr_sync_async_fault_cross.3699115463 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 41329581 ps |
| CPU time | 1.86 seconds |
| Started | Sep 18 07:54:34 PM UTC 24 |
| Finished | Sep 18 07:54:38 PM UTC 24 |
| Peak memory | 215420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699115463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3699115463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/2.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/20.keymgr_alert_test.39173811 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 14755818 ps |
| CPU time | 1.12 seconds |
| Started | Sep 18 07:56:34 PM UTC 24 |
| Finished | Sep 18 07:56:36 PM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39173811 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.39173811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/20.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/20.keymgr_cfg_regwen.285235819 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 305679512 ps |
| CPU time | 2.59 seconds |
| Started | Sep 18 07:56:34 PM UTC 24 |
| Finished | Sep 18 07:56:37 PM UTC 24 |
| Peak memory | 223724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285235819 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.285235819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/20.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/20.keymgr_custom_cm.2133502333 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 209677550 ps |
| CPU time | 3.33 seconds |
| Started | Sep 18 07:56:34 PM UTC 24 |
| Finished | Sep 18 07:56:38 PM UTC 24 |
| Peak memory | 227772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133502333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2133502333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/20.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/20.keymgr_direct_to_disabled.2863598096 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 79283337 ps |
| CPU time | 1.54 seconds |
| Started | Sep 18 07:56:34 PM UTC 24 |
| Finished | Sep 18 07:56:36 PM UTC 24 |
| Peak memory | 213364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863598096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2863598096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/20.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/20.keymgr_hwsw_invalid_input.25938177 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 116615397 ps |
| CPU time | 3.08 seconds |
| Started | Sep 18 07:56:34 PM UTC 24 |
| Finished | Sep 18 07:56:38 PM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25938177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.25938177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/20.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/20.keymgr_kmac_rsp_err.1471413964 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 121517568 ps |
| CPU time | 6.71 seconds |
| Started | Sep 18 07:56:34 PM UTC 24 |
| Finished | Sep 18 07:56:42 PM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471413964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.1471413964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/20.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/20.keymgr_random.1346727304 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 581353129 ps |
| CPU time | 5.36 seconds |
| Started | Sep 18 07:56:34 PM UTC 24 |
| Finished | Sep 18 07:56:40 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346727304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1346727304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/20.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/20.keymgr_sideload.1387656619 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 1802728851 ps |
| CPU time | 16.68 seconds |
| Started | Sep 18 07:56:32 PM UTC 24 |
| Finished | Sep 18 07:56:50 PM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387656619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1387656619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/20.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_aes.1162157339 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 194486336 ps |
| CPU time | 2.73 seconds |
| Started | Sep 18 07:56:33 PM UTC 24 |
| Finished | Sep 18 07:56:36 PM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162157339 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1162157339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/20.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_kmac.4024523182 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 87380062 ps |
| CPU time | 2.84 seconds |
| Started | Sep 18 07:56:32 PM UTC 24 |
| Finished | Sep 18 07:56:36 PM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024523182 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.4024523182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/20.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_otbn.3925219083 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 533500759 ps |
| CPU time | 3.76 seconds |
| Started | Sep 18 07:56:34 PM UTC 24 |
| Finished | Sep 18 07:56:39 PM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925219083 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3925219083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/20.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_protect.817718170 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1163524123 ps |
| CPU time | 6.02 seconds |
| Started | Sep 18 07:56:34 PM UTC 24 |
| Finished | Sep 18 07:56:41 PM UTC 24 |
| Peak memory | 223544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817718170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.817718170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/20.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/20.keymgr_smoke.1389717714 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 97622048 ps |
| CPU time | 3.69 seconds |
| Started | Sep 18 07:56:32 PM UTC 24 |
| Finished | Sep 18 07:56:37 PM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389717714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1389717714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/20.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all.2693946108 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 64339934 ps |
| CPU time | 3.81 seconds |
| Started | Sep 18 07:56:34 PM UTC 24 |
| Finished | Sep 18 07:56:39 PM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693946108 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2693946108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/20.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/20.keymgr_sw_invalid_input.2234638790 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 3101639000 ps |
| CPU time | 17.71 seconds |
| Started | Sep 18 07:56:34 PM UTC 24 |
| Finished | Sep 18 07:56:53 PM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234638790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2234638790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/20.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/20.keymgr_sync_async_fault_cross.2985892108 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 834315462 ps |
| CPU time | 14.52 seconds |
| Started | Sep 18 07:56:34 PM UTC 24 |
| Finished | Sep 18 07:56:50 PM UTC 24 |
| Peak memory | 219648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985892108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2985892108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/20.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/21.keymgr_alert_test.3877202560 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 74733417 ps |
| CPU time | 1.41 seconds |
| Started | Sep 18 07:56:39 PM UTC 24 |
| Finished | Sep 18 07:56:42 PM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877202560 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3877202560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/21.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/21.keymgr_cfg_regwen.1520327227 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 70622240 ps |
| CPU time | 5.44 seconds |
| Started | Sep 18 07:56:38 PM UTC 24 |
| Finished | Sep 18 07:56:44 PM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520327227 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1520327227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/21.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/21.keymgr_custom_cm.1254373303 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 258812312 ps |
| CPU time | 4.67 seconds |
| Started | Sep 18 07:56:39 PM UTC 24 |
| Finished | Sep 18 07:56:45 PM UTC 24 |
| Peak memory | 231032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254373303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1254373303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/21.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/21.keymgr_direct_to_disabled.762992840 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 93461061 ps |
| CPU time | 2.59 seconds |
| Started | Sep 18 07:56:38 PM UTC 24 |
| Finished | Sep 18 07:56:41 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762992840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.762992840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/21.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/21.keymgr_hwsw_invalid_input.2441241959 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 507683927 ps |
| CPU time | 12.1 seconds |
| Started | Sep 18 07:56:38 PM UTC 24 |
| Finished | Sep 18 07:56:51 PM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441241959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2441241959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/21.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/21.keymgr_kmac_rsp_err.532891927 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 190718367 ps |
| CPU time | 3.08 seconds |
| Started | Sep 18 07:56:38 PM UTC 24 |
| Finished | Sep 18 07:56:42 PM UTC 24 |
| Peak memory | 231556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532891927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.532891927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/21.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/21.keymgr_lc_disable.18495878 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 143658839 ps |
| CPU time | 5.39 seconds |
| Started | Sep 18 07:56:38 PM UTC 24 |
| Finished | Sep 18 07:56:44 PM UTC 24 |
| Peak memory | 219388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18495878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.18495878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/21.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/21.keymgr_random.1551803676 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 72659183 ps |
| CPU time | 3.87 seconds |
| Started | Sep 18 07:56:37 PM UTC 24 |
| Finished | Sep 18 07:56:42 PM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551803676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1551803676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/21.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/21.keymgr_sideload.3209502335 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 32357441 ps |
| CPU time | 2.82 seconds |
| Started | Sep 18 07:56:34 PM UTC 24 |
| Finished | Sep 18 07:56:38 PM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209502335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3209502335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/21.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_aes.791881309 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 331530898 ps |
| CPU time | 5.16 seconds |
| Started | Sep 18 07:56:35 PM UTC 24 |
| Finished | Sep 18 07:56:42 PM UTC 24 |
| Peak memory | 215340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791881309 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.791881309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/21.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_kmac.587683103 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 134769364 ps |
| CPU time | 4.58 seconds |
| Started | Sep 18 07:56:34 PM UTC 24 |
| Finished | Sep 18 07:56:40 PM UTC 24 |
| Peak memory | 215384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587683103 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.587683103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/21.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_protect.199878443 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 6967937101 ps |
| CPU time | 36.52 seconds |
| Started | Sep 18 07:56:39 PM UTC 24 |
| Finished | Sep 18 07:57:17 PM UTC 24 |
| Peak memory | 223596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199878443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.199878443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/21.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/21.keymgr_smoke.3676725246 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 448733462 ps |
| CPU time | 4.48 seconds |
| Started | Sep 18 07:56:34 PM UTC 24 |
| Finished | Sep 18 07:56:40 PM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676725246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3676725246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/21.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/21.keymgr_sw_invalid_input.1087422677 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 844261482 ps |
| CPU time | 22.68 seconds |
| Started | Sep 18 07:56:38 PM UTC 24 |
| Finished | Sep 18 07:57:02 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087422677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1087422677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/21.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/21.keymgr_sync_async_fault_cross.754942198 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 48188252 ps |
| CPU time | 2.89 seconds |
| Started | Sep 18 07:56:39 PM UTC 24 |
| Finished | Sep 18 07:56:43 PM UTC 24 |
| Peak memory | 217472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754942198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.754942198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/21.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/22.keymgr_alert_test.3777638070 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 29386025 ps |
| CPU time | 1.39 seconds |
| Started | Sep 18 07:56:45 PM UTC 24 |
| Finished | Sep 18 07:56:48 PM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777638070 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3777638070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/22.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/22.keymgr_custom_cm.3150669089 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 94391540 ps |
| CPU time | 3.25 seconds |
| Started | Sep 18 07:56:44 PM UTC 24 |
| Finished | Sep 18 07:56:48 PM UTC 24 |
| Peak memory | 228104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150669089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3150669089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/22.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/22.keymgr_direct_to_disabled.3998182312 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 111129249 ps |
| CPU time | 3.01 seconds |
| Started | Sep 18 07:56:44 PM UTC 24 |
| Finished | Sep 18 07:56:48 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998182312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3998182312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/22.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/22.keymgr_hwsw_invalid_input.1206158990 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 83864114 ps |
| CPU time | 4.86 seconds |
| Started | Sep 18 07:56:44 PM UTC 24 |
| Finished | Sep 18 07:56:50 PM UTC 24 |
| Peak memory | 229744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206158990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1206158990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/22.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/22.keymgr_kmac_rsp_err.1444316226 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 34717357 ps |
| CPU time | 2.33 seconds |
| Started | Sep 18 07:56:44 PM UTC 24 |
| Finished | Sep 18 07:56:47 PM UTC 24 |
| Peak memory | 223436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444316226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1444316226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/22.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/22.keymgr_lc_disable.2124490469 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 52316182 ps |
| CPU time | 3.57 seconds |
| Started | Sep 18 07:56:44 PM UTC 24 |
| Finished | Sep 18 07:56:48 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124490469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2124490469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/22.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/22.keymgr_random.1698826243 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 949828559 ps |
| CPU time | 6.83 seconds |
| Started | Sep 18 07:56:41 PM UTC 24 |
| Finished | Sep 18 07:56:49 PM UTC 24 |
| Peak memory | 215352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698826243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1698826243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/22.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/22.keymgr_sideload.1173737364 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 3024453029 ps |
| CPU time | 36.68 seconds |
| Started | Sep 18 07:56:40 PM UTC 24 |
| Finished | Sep 18 07:57:19 PM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173737364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1173737364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/22.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_aes.1057414858 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 44483845 ps |
| CPU time | 3.53 seconds |
| Started | Sep 18 07:56:41 PM UTC 24 |
| Finished | Sep 18 07:56:45 PM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057414858 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1057414858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/22.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_kmac.1380831146 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 120134610 ps |
| CPU time | 3.81 seconds |
| Started | Sep 18 07:56:41 PM UTC 24 |
| Finished | Sep 18 07:56:45 PM UTC 24 |
| Peak memory | 215432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380831146 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1380831146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/22.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_otbn.905749523 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 187796284 ps |
| CPU time | 2.41 seconds |
| Started | Sep 18 07:56:41 PM UTC 24 |
| Finished | Sep 18 07:56:44 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905749523 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.905749523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/22.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_protect.3328728871 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1670087210 ps |
| CPU time | 11.57 seconds |
| Started | Sep 18 07:56:44 PM UTC 24 |
| Finished | Sep 18 07:56:57 PM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328728871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3328728871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/22.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/22.keymgr_smoke.2638667218 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 999413196 ps |
| CPU time | 5.73 seconds |
| Started | Sep 18 07:56:40 PM UTC 24 |
| Finished | Sep 18 07:56:47 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638667218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2638667218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/22.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/22.keymgr_sw_invalid_input.416602332 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 193696926 ps |
| CPU time | 4.75 seconds |
| Started | Sep 18 07:56:44 PM UTC 24 |
| Finished | Sep 18 07:56:50 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416602332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.416602332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/22.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/22.keymgr_sync_async_fault_cross.1451464963 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 98041725 ps |
| CPU time | 2.87 seconds |
| Started | Sep 18 07:56:44 PM UTC 24 |
| Finished | Sep 18 07:56:48 PM UTC 24 |
| Peak memory | 217264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451464963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1451464963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/22.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/23.keymgr_alert_test.1713692618 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 54787209 ps |
| CPU time | 1.36 seconds |
| Started | Sep 18 07:56:51 PM UTC 24 |
| Finished | Sep 18 07:56:53 PM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713692618 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1713692618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/23.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/23.keymgr_cfg_regwen.1630683457 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 240833564 ps |
| CPU time | 5.4 seconds |
| Started | Sep 18 07:56:47 PM UTC 24 |
| Finished | Sep 18 07:56:53 PM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630683457 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1630683457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/23.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/23.keymgr_custom_cm.390245572 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 180372238 ps |
| CPU time | 3.35 seconds |
| Started | Sep 18 07:56:49 PM UTC 24 |
| Finished | Sep 18 07:56:54 PM UTC 24 |
| Peak memory | 229816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390245572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.390245572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/23.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/23.keymgr_direct_to_disabled.579808927 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 51297271 ps |
| CPU time | 2.61 seconds |
| Started | Sep 18 07:56:48 PM UTC 24 |
| Finished | Sep 18 07:56:52 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579808927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.579808927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/23.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/23.keymgr_kmac_rsp_err.4214436922 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 202087724 ps |
| CPU time | 7.34 seconds |
| Started | Sep 18 07:56:49 PM UTC 24 |
| Finished | Sep 18 07:56:58 PM UTC 24 |
| Peak memory | 231464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214436922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.4214436922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/23.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/23.keymgr_lc_disable.1424230738 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 146977782 ps |
| CPU time | 6.58 seconds |
| Started | Sep 18 07:56:48 PM UTC 24 |
| Finished | Sep 18 07:56:56 PM UTC 24 |
| Peak memory | 231812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424230738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1424230738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/23.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/23.keymgr_random.2614747473 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 209453018 ps |
| CPU time | 4.8 seconds |
| Started | Sep 18 07:56:47 PM UTC 24 |
| Finished | Sep 18 07:56:53 PM UTC 24 |
| Peak memory | 219372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614747473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2614747473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/23.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/23.keymgr_sideload.184080179 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 28258570 ps |
| CPU time | 2.7 seconds |
| Started | Sep 18 07:56:46 PM UTC 24 |
| Finished | Sep 18 07:56:49 PM UTC 24 |
| Peak memory | 217640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184080179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.184080179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/23.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_aes.2645313442 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 109429110 ps |
| CPU time | 3.86 seconds |
| Started | Sep 18 07:56:46 PM UTC 24 |
| Finished | Sep 18 07:56:51 PM UTC 24 |
| Peak memory | 217512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645313442 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2645313442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/23.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_kmac.829052250 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 206505038 ps |
| CPU time | 5.9 seconds |
| Started | Sep 18 07:56:46 PM UTC 24 |
| Finished | Sep 18 07:56:53 PM UTC 24 |
| Peak memory | 217404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829052250 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.829052250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/23.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_otbn.717943845 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 102555786 ps |
| CPU time | 2.64 seconds |
| Started | Sep 18 07:56:46 PM UTC 24 |
| Finished | Sep 18 07:56:49 PM UTC 24 |
| Peak memory | 217660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717943845 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.717943845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/23.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_protect.4294557466 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 409483801 ps |
| CPU time | 6.91 seconds |
| Started | Sep 18 07:56:49 PM UTC 24 |
| Finished | Sep 18 07:56:57 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294557466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.4294557466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/23.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/23.keymgr_smoke.2523306770 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 54211440 ps |
| CPU time | 3.3 seconds |
| Started | Sep 18 07:56:45 PM UTC 24 |
| Finished | Sep 18 07:56:50 PM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523306770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2523306770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/23.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all.3157509237 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 360883164 ps |
| CPU time | 4.65 seconds |
| Started | Sep 18 07:56:51 PM UTC 24 |
| Finished | Sep 18 07:56:56 PM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157509237 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3157509237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/23.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/23.keymgr_sw_invalid_input.2250900744 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 497004402 ps |
| CPU time | 5.85 seconds |
| Started | Sep 18 07:56:49 PM UTC 24 |
| Finished | Sep 18 07:56:56 PM UTC 24 |
| Peak memory | 227632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250900744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2250900744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/23.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/23.keymgr_sync_async_fault_cross.2837484068 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 54803111 ps |
| CPU time | 2.16 seconds |
| Started | Sep 18 07:56:49 PM UTC 24 |
| Finished | Sep 18 07:56:53 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837484068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2837484068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/23.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/24.keymgr_alert_test.3374462137 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 17920369 ps |
| CPU time | 1.07 seconds |
| Started | Sep 18 07:57:01 PM UTC 24 |
| Finished | Sep 18 07:57:04 PM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374462137 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3374462137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/24.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/24.keymgr_cfg_regwen.229705454 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 95694451 ps |
| CPU time | 5.49 seconds |
| Started | Sep 18 07:56:52 PM UTC 24 |
| Finished | Sep 18 07:56:58 PM UTC 24 |
| Peak memory | 225656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229705454 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.229705454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/24.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/24.keymgr_custom_cm.617941515 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 610509707 ps |
| CPU time | 5.43 seconds |
| Started | Sep 18 07:57:00 PM UTC 24 |
| Finished | Sep 18 07:57:07 PM UTC 24 |
| Peak memory | 230640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617941515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.617941515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/24.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/24.keymgr_direct_to_disabled.2244873169 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 466492780 ps |
| CPU time | 2.76 seconds |
| Started | Sep 18 07:56:52 PM UTC 24 |
| Finished | Sep 18 07:56:56 PM UTC 24 |
| Peak memory | 217248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244873169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2244873169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/24.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/24.keymgr_hwsw_invalid_input.1496986664 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 388675800 ps |
| CPU time | 4.56 seconds |
| Started | Sep 18 07:57:00 PM UTC 24 |
| Finished | Sep 18 07:57:06 PM UTC 24 |
| Peak memory | 230572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496986664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1496986664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/24.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/24.keymgr_lc_disable.1725112936 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 172963081 ps |
| CPU time | 3 seconds |
| Started | Sep 18 07:56:52 PM UTC 24 |
| Finished | Sep 18 07:56:56 PM UTC 24 |
| Peak memory | 229544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725112936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1725112936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/24.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/24.keymgr_random.950770443 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 2119305969 ps |
| CPU time | 29.16 seconds |
| Started | Sep 18 07:56:52 PM UTC 24 |
| Finished | Sep 18 07:57:22 PM UTC 24 |
| Peak memory | 229540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950770443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.950770443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/24.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/24.keymgr_sideload.4145777675 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 52467743 ps |
| CPU time | 2.84 seconds |
| Started | Sep 18 07:56:51 PM UTC 24 |
| Finished | Sep 18 07:56:55 PM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145777675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.4145777675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/24.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_aes.4174558895 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 253539158 ps |
| CPU time | 3.37 seconds |
| Started | Sep 18 07:56:51 PM UTC 24 |
| Finished | Sep 18 07:56:55 PM UTC 24 |
| Peak memory | 217248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174558895 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.4174558895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/24.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_kmac.2945199247 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 1412229716 ps |
| CPU time | 10.25 seconds |
| Started | Sep 18 07:56:51 PM UTC 24 |
| Finished | Sep 18 07:57:02 PM UTC 24 |
| Peak memory | 215104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945199247 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2945199247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/24.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_otbn.2800125736 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 36157259 ps |
| CPU time | 2.48 seconds |
| Started | Sep 18 07:56:52 PM UTC 24 |
| Finished | Sep 18 07:56:55 PM UTC 24 |
| Peak memory | 215536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800125736 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2800125736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/24.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_protect.763135619 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 236232546 ps |
| CPU time | 1.86 seconds |
| Started | Sep 18 07:57:00 PM UTC 24 |
| Finished | Sep 18 07:57:03 PM UTC 24 |
| Peak memory | 224920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763135619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.763135619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/24.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/24.keymgr_smoke.2742745694 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 36149922 ps |
| CPU time | 2.29 seconds |
| Started | Sep 18 07:56:51 PM UTC 24 |
| Finished | Sep 18 07:56:54 PM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742745694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2742745694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/24.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all.1164194927 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 13353073235 ps |
| CPU time | 51.47 seconds |
| Started | Sep 18 07:57:01 PM UTC 24 |
| Finished | Sep 18 07:57:54 PM UTC 24 |
| Peak memory | 225708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164194927 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1164194927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/24.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/24.keymgr_sw_invalid_input.1110428360 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 5599775265 ps |
| CPU time | 28.49 seconds |
| Started | Sep 18 07:57:00 PM UTC 24 |
| Finished | Sep 18 07:57:30 PM UTC 24 |
| Peak memory | 217384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110428360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1110428360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/24.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/24.keymgr_sync_async_fault_cross.2254206934 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 121810124 ps |
| CPU time | 2.36 seconds |
| Started | Sep 18 07:57:00 PM UTC 24 |
| Finished | Sep 18 07:57:04 PM UTC 24 |
| Peak memory | 219520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254206934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2254206934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/24.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/25.keymgr_alert_test.1874299335 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 53450528 ps |
| CPU time | 1.21 seconds |
| Started | Sep 18 07:57:03 PM UTC 24 |
| Finished | Sep 18 07:57:05 PM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874299335 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1874299335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/25.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/25.keymgr_cfg_regwen.1588564895 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 1911514226 ps |
| CPU time | 96.08 seconds |
| Started | Sep 18 07:57:02 PM UTC 24 |
| Finished | Sep 18 07:58:40 PM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588564895 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1588564895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/25.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/25.keymgr_custom_cm.2831203978 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 49116924 ps |
| CPU time | 3.71 seconds |
| Started | Sep 18 07:57:02 PM UTC 24 |
| Finished | Sep 18 07:57:07 PM UTC 24 |
| Peak memory | 217236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831203978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2831203978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/25.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/25.keymgr_direct_to_disabled.1697994605 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 56439643 ps |
| CPU time | 3.29 seconds |
| Started | Sep 18 07:57:02 PM UTC 24 |
| Finished | Sep 18 07:57:06 PM UTC 24 |
| Peak memory | 227568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697994605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1697994605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/25.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/25.keymgr_hwsw_invalid_input.481743005 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 18830592675 ps |
| CPU time | 44.35 seconds |
| Started | Sep 18 07:57:02 PM UTC 24 |
| Finished | Sep 18 07:57:48 PM UTC 24 |
| Peak memory | 223528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481743005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.481743005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/25.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/25.keymgr_kmac_rsp_err.3927918498 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 60500005 ps |
| CPU time | 2.92 seconds |
| Started | Sep 18 07:57:02 PM UTC 24 |
| Finished | Sep 18 07:57:06 PM UTC 24 |
| Peak memory | 223340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927918498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3927918498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/25.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/25.keymgr_lc_disable.3518992332 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 165219398 ps |
| CPU time | 3.59 seconds |
| Started | Sep 18 07:57:02 PM UTC 24 |
| Finished | Sep 18 07:57:07 PM UTC 24 |
| Peak memory | 225448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518992332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3518992332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/25.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/25.keymgr_random.18617244 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 1179485004 ps |
| CPU time | 10.88 seconds |
| Started | Sep 18 07:57:02 PM UTC 24 |
| Finished | Sep 18 07:57:14 PM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18617244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.18617244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/25.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/25.keymgr_sideload.3520204836 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 2967656810 ps |
| CPU time | 24.34 seconds |
| Started | Sep 18 07:57:02 PM UTC 24 |
| Finished | Sep 18 07:57:27 PM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520204836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3520204836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/25.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_aes.4156820619 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 1927869130 ps |
| CPU time | 31.9 seconds |
| Started | Sep 18 07:57:02 PM UTC 24 |
| Finished | Sep 18 07:57:35 PM UTC 24 |
| Peak memory | 217292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156820619 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.4156820619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/25.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_kmac.2321739118 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 211776416 ps |
| CPU time | 9.66 seconds |
| Started | Sep 18 07:57:02 PM UTC 24 |
| Finished | Sep 18 07:57:13 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321739118 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2321739118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/25.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_otbn.1127878891 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 7633280666 ps |
| CPU time | 43.78 seconds |
| Started | Sep 18 07:57:02 PM UTC 24 |
| Finished | Sep 18 07:57:47 PM UTC 24 |
| Peak memory | 217456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127878891 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1127878891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/25.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_protect.3010448145 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 228962274 ps |
| CPU time | 7.13 seconds |
| Started | Sep 18 07:57:02 PM UTC 24 |
| Finished | Sep 18 07:57:10 PM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010448145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3010448145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/25.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/25.keymgr_smoke.3748773061 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 158495091 ps |
| CPU time | 5.39 seconds |
| Started | Sep 18 07:57:02 PM UTC 24 |
| Finished | Sep 18 07:57:08 PM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748773061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3748773061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/25.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/25.keymgr_sw_invalid_input.3537336337 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 211255236 ps |
| CPU time | 10.17 seconds |
| Started | Sep 18 07:57:02 PM UTC 24 |
| Finished | Sep 18 07:57:13 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537336337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3537336337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/25.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/25.keymgr_sync_async_fault_cross.3720765113 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 4255574086 ps |
| CPU time | 25.8 seconds |
| Started | Sep 18 07:57:02 PM UTC 24 |
| Finished | Sep 18 07:57:29 PM UTC 24 |
| Peak memory | 219304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720765113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3720765113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/25.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/26.keymgr_alert_test.3144041248 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 11357386 ps |
| CPU time | 1.34 seconds |
| Started | Sep 18 07:57:09 PM UTC 24 |
| Finished | Sep 18 07:57:12 PM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144041248 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3144041248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/26.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/26.keymgr_custom_cm.161783045 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 430625069 ps |
| CPU time | 5.3 seconds |
| Started | Sep 18 07:57:08 PM UTC 24 |
| Finished | Sep 18 07:57:14 PM UTC 24 |
| Peak memory | 223812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161783045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.161783045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/26.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/26.keymgr_direct_to_disabled.3754848059 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 146962278 ps |
| CPU time | 5.08 seconds |
| Started | Sep 18 07:57:07 PM UTC 24 |
| Finished | Sep 18 07:57:13 PM UTC 24 |
| Peak memory | 227488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754848059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3754848059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/26.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/26.keymgr_hwsw_invalid_input.3636037435 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 358823582 ps |
| CPU time | 5.62 seconds |
| Started | Sep 18 07:57:07 PM UTC 24 |
| Finished | Sep 18 07:57:14 PM UTC 24 |
| Peak memory | 223732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636037435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3636037435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/26.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/26.keymgr_kmac_rsp_err.2677801814 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 112283779 ps |
| CPU time | 4.75 seconds |
| Started | Sep 18 07:57:08 PM UTC 24 |
| Finished | Sep 18 07:57:14 PM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677801814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2677801814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/26.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/26.keymgr_lc_disable.2579407474 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 323995726 ps |
| CPU time | 4.37 seconds |
| Started | Sep 18 07:57:07 PM UTC 24 |
| Finished | Sep 18 07:57:12 PM UTC 24 |
| Peak memory | 229544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579407474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2579407474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/26.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/26.keymgr_random.2656880488 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 637505087 ps |
| CPU time | 4.8 seconds |
| Started | Sep 18 07:57:07 PM UTC 24 |
| Finished | Sep 18 07:57:13 PM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656880488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2656880488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/26.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/26.keymgr_sideload.3112468851 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 5216425534 ps |
| CPU time | 13.13 seconds |
| Started | Sep 18 07:57:04 PM UTC 24 |
| Finished | Sep 18 07:57:19 PM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112468851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3112468851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/26.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_aes.3707089814 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 120079441 ps |
| CPU time | 2.51 seconds |
| Started | Sep 18 07:57:04 PM UTC 24 |
| Finished | Sep 18 07:57:08 PM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707089814 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3707089814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/26.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_kmac.2610578526 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 303016576 ps |
| CPU time | 3.75 seconds |
| Started | Sep 18 07:57:04 PM UTC 24 |
| Finished | Sep 18 07:57:09 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610578526 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2610578526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/26.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_otbn.4233321956 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 201038179 ps |
| CPU time | 6.93 seconds |
| Started | Sep 18 07:57:05 PM UTC 24 |
| Finished | Sep 18 07:57:14 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233321956 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.4233321956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/26.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_protect.24723744 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 118739570 ps |
| CPU time | 3.76 seconds |
| Started | Sep 18 07:57:08 PM UTC 24 |
| Finished | Sep 18 07:57:13 PM UTC 24 |
| Peak memory | 215224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24723744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.24723744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/26.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/26.keymgr_smoke.460113082 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 436348704 ps |
| CPU time | 3.76 seconds |
| Started | Sep 18 07:57:03 PM UTC 24 |
| Finished | Sep 18 07:57:08 PM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460113082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.460113082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/26.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/26.keymgr_sw_invalid_input.480343381 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 198642531 ps |
| CPU time | 6.54 seconds |
| Started | Sep 18 07:57:07 PM UTC 24 |
| Finished | Sep 18 07:57:15 PM UTC 24 |
| Peak memory | 223392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480343381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.480343381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/26.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/26.keymgr_sync_async_fault_cross.2970118880 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 112530955 ps |
| CPU time | 2.63 seconds |
| Started | Sep 18 07:57:08 PM UTC 24 |
| Finished | Sep 18 07:57:12 PM UTC 24 |
| Peak memory | 217660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970118880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2970118880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/26.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/27.keymgr_alert_test.2540280228 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 13532519 ps |
| CPU time | 1.31 seconds |
| Started | Sep 18 07:57:16 PM UTC 24 |
| Finished | Sep 18 07:57:18 PM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540280228 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2540280228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/27.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/27.keymgr_direct_to_disabled.2976155561 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 851465785 ps |
| CPU time | 25.17 seconds |
| Started | Sep 18 07:57:14 PM UTC 24 |
| Finished | Sep 18 07:57:40 PM UTC 24 |
| Peak memory | 217320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976155561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2976155561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/27.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/27.keymgr_hwsw_invalid_input.1679256942 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 107114481 ps |
| CPU time | 2.67 seconds |
| Started | Sep 18 07:57:14 PM UTC 24 |
| Finished | Sep 18 07:57:18 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679256942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1679256942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/27.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/27.keymgr_kmac_rsp_err.2349489446 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 210296935 ps |
| CPU time | 7.38 seconds |
| Started | Sep 18 07:57:14 PM UTC 24 |
| Finished | Sep 18 07:57:23 PM UTC 24 |
| Peak memory | 231380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349489446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2349489446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/27.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/27.keymgr_lc_disable.1606314823 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 198908955 ps |
| CPU time | 2.87 seconds |
| Started | Sep 18 07:57:14 PM UTC 24 |
| Finished | Sep 18 07:57:18 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606314823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1606314823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/27.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/27.keymgr_random.296269894 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 199007186 ps |
| CPU time | 4.69 seconds |
| Started | Sep 18 07:57:13 PM UTC 24 |
| Finished | Sep 18 07:57:19 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296269894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.296269894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/27.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/27.keymgr_sideload.2893106778 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 308086838 ps |
| CPU time | 4.62 seconds |
| Started | Sep 18 07:57:10 PM UTC 24 |
| Finished | Sep 18 07:57:16 PM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893106778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2893106778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/27.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_aes.1019487582 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 281957799 ps |
| CPU time | 2.93 seconds |
| Started | Sep 18 07:57:12 PM UTC 24 |
| Finished | Sep 18 07:57:16 PM UTC 24 |
| Peak memory | 215192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019487582 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1019487582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/27.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_kmac.1139162007 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 35042411 ps |
| CPU time | 2.8 seconds |
| Started | Sep 18 07:57:12 PM UTC 24 |
| Finished | Sep 18 07:57:16 PM UTC 24 |
| Peak memory | 217372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139162007 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1139162007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/27.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_otbn.767606220 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 316390265 ps |
| CPU time | 4.86 seconds |
| Started | Sep 18 07:57:13 PM UTC 24 |
| Finished | Sep 18 07:57:19 PM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767606220 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.767606220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/27.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_protect.3691876980 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 158140418 ps |
| CPU time | 2.64 seconds |
| Started | Sep 18 07:57:14 PM UTC 24 |
| Finished | Sep 18 07:57:18 PM UTC 24 |
| Peak memory | 225448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691876980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3691876980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/27.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/27.keymgr_smoke.1216906311 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 132574257 ps |
| CPU time | 2.76 seconds |
| Started | Sep 18 07:57:09 PM UTC 24 |
| Finished | Sep 18 07:57:13 PM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216906311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1216906311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/27.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/27.keymgr_sw_invalid_input.3190447694 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 222336017 ps |
| CPU time | 7.96 seconds |
| Started | Sep 18 07:57:14 PM UTC 24 |
| Finished | Sep 18 07:57:23 PM UTC 24 |
| Peak memory | 215536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190447694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3190447694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/27.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/27.keymgr_sync_async_fault_cross.83773496 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 329931522 ps |
| CPU time | 3.11 seconds |
| Started | Sep 18 07:57:15 PM UTC 24 |
| Finished | Sep 18 07:57:20 PM UTC 24 |
| Peak memory | 217472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83773496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.83773496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/27.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/28.keymgr_alert_test.2967397381 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 18345370 ps |
| CPU time | 1.05 seconds |
| Started | Sep 18 07:57:21 PM UTC 24 |
| Finished | Sep 18 07:57:23 PM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967397381 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2967397381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/28.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/28.keymgr_custom_cm.3793413826 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 47560754 ps |
| CPU time | 3.39 seconds |
| Started | Sep 18 07:57:19 PM UTC 24 |
| Finished | Sep 18 07:57:24 PM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793413826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3793413826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/28.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/28.keymgr_direct_to_disabled.3164169186 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 150688775 ps |
| CPU time | 1.77 seconds |
| Started | Sep 18 07:57:18 PM UTC 24 |
| Finished | Sep 18 07:57:21 PM UTC 24 |
| Peak memory | 216864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164169186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3164169186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/28.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/28.keymgr_hwsw_invalid_input.576623664 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 25238130 ps |
| CPU time | 2.73 seconds |
| Started | Sep 18 07:57:19 PM UTC 24 |
| Finished | Sep 18 07:57:23 PM UTC 24 |
| Peak memory | 223504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576623664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.576623664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/28.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/28.keymgr_kmac_rsp_err.1257871899 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 159859186 ps |
| CPU time | 5.62 seconds |
| Started | Sep 18 07:57:19 PM UTC 24 |
| Finished | Sep 18 07:57:26 PM UTC 24 |
| Peak memory | 225648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257871899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1257871899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/28.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/28.keymgr_lc_disable.3837710486 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 210514435 ps |
| CPU time | 5.02 seconds |
| Started | Sep 18 07:57:19 PM UTC 24 |
| Finished | Sep 18 07:57:25 PM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837710486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3837710486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/28.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/28.keymgr_random.3865964366 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 588168086 ps |
| CPU time | 7.09 seconds |
| Started | Sep 18 07:57:17 PM UTC 24 |
| Finished | Sep 18 07:57:25 PM UTC 24 |
| Peak memory | 219440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865964366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3865964366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/28.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/28.keymgr_sideload.3740821064 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 125044861 ps |
| CPU time | 3.48 seconds |
| Started | Sep 18 07:57:16 PM UTC 24 |
| Finished | Sep 18 07:57:20 PM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740821064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3740821064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/28.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_aes.651696253 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 248704202 ps |
| CPU time | 4 seconds |
| Started | Sep 18 07:57:17 PM UTC 24 |
| Finished | Sep 18 07:57:22 PM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651696253 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.651696253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/28.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_kmac.1364508555 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 173628874 ps |
| CPU time | 2.89 seconds |
| Started | Sep 18 07:57:16 PM UTC 24 |
| Finished | Sep 18 07:57:20 PM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364508555 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1364508555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/28.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_otbn.3558610494 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 244622949 ps |
| CPU time | 6.97 seconds |
| Started | Sep 18 07:57:17 PM UTC 24 |
| Finished | Sep 18 07:57:25 PM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558610494 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3558610494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/28.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_protect.3776349722 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 101727026 ps |
| CPU time | 5.62 seconds |
| Started | Sep 18 07:57:19 PM UTC 24 |
| Finished | Sep 18 07:57:26 PM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776349722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3776349722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/28.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/28.keymgr_smoke.2605110221 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 101235101 ps |
| CPU time | 4.02 seconds |
| Started | Sep 18 07:57:16 PM UTC 24 |
| Finished | Sep 18 07:57:21 PM UTC 24 |
| Peak memory | 217264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605110221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2605110221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/28.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all.3386573413 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 12766898440 ps |
| CPU time | 184.77 seconds |
| Started | Sep 18 07:57:19 PM UTC 24 |
| Finished | Sep 18 08:00:27 PM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386573413 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3386573413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/28.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all_with_rand_reset.2586382026 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 1395131730 ps |
| CPU time | 11.38 seconds |
| Started | Sep 18 07:57:21 PM UTC 24 |
| Finished | Sep 18 07:57:33 PM UTC 24 |
| Peak memory | 231856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2586382026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymg r_stress_all_with_rand_reset.2586382026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/28.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/28.keymgr_sw_invalid_input.1468056227 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 4705274082 ps |
| CPU time | 26.73 seconds |
| Started | Sep 18 07:57:19 PM UTC 24 |
| Finished | Sep 18 07:57:47 PM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468056227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1468056227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/28.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/28.keymgr_sync_async_fault_cross.1540182605 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 36165106 ps |
| CPU time | 2.76 seconds |
| Started | Sep 18 07:57:19 PM UTC 24 |
| Finished | Sep 18 07:57:23 PM UTC 24 |
| Peak memory | 217408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540182605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1540182605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/28.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/29.keymgr_alert_test.975587792 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 56232106 ps |
| CPU time | 1.12 seconds |
| Started | Sep 18 07:57:27 PM UTC 24 |
| Finished | Sep 18 07:57:29 PM UTC 24 |
| Peak memory | 212892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975587792 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.975587792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/29.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/29.keymgr_custom_cm.1084993571 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 114151156 ps |
| CPU time | 3.77 seconds |
| Started | Sep 18 07:57:26 PM UTC 24 |
| Finished | Sep 18 07:57:31 PM UTC 24 |
| Peak memory | 227888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084993571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1084993571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/29.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/29.keymgr_direct_to_disabled.2716074495 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 159101472 ps |
| CPU time | 2.18 seconds |
| Started | Sep 18 07:57:24 PM UTC 24 |
| Finished | Sep 18 07:57:28 PM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716074495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2716074495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/29.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/29.keymgr_hwsw_invalid_input.1658618333 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 270857934 ps |
| CPU time | 4.61 seconds |
| Started | Sep 18 07:57:24 PM UTC 24 |
| Finished | Sep 18 07:57:30 PM UTC 24 |
| Peak memory | 223732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658618333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1658618333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/29.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/29.keymgr_kmac_rsp_err.2671078370 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 114997338 ps |
| CPU time | 3.72 seconds |
| Started | Sep 18 07:57:24 PM UTC 24 |
| Finished | Sep 18 07:57:29 PM UTC 24 |
| Peak memory | 223680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671078370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2671078370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/29.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/29.keymgr_lc_disable.2147789708 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 35779346 ps |
| CPU time | 2.54 seconds |
| Started | Sep 18 07:57:24 PM UTC 24 |
| Finished | Sep 18 07:57:28 PM UTC 24 |
| Peak memory | 223668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147789708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2147789708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/29.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/29.keymgr_random.2325030363 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 375204751 ps |
| CPU time | 5.3 seconds |
| Started | Sep 18 07:57:23 PM UTC 24 |
| Finished | Sep 18 07:57:29 PM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325030363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2325030363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/29.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/29.keymgr_sideload.4015290278 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 192554143 ps |
| CPU time | 8.58 seconds |
| Started | Sep 18 07:57:21 PM UTC 24 |
| Finished | Sep 18 07:57:30 PM UTC 24 |
| Peak memory | 215224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015290278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.4015290278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/29.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_aes.3101449660 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 93836416 ps |
| CPU time | 4.72 seconds |
| Started | Sep 18 07:57:22 PM UTC 24 |
| Finished | Sep 18 07:57:28 PM UTC 24 |
| Peak memory | 217512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101449660 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3101449660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/29.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_kmac.3233474199 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 1286892777 ps |
| CPU time | 9.01 seconds |
| Started | Sep 18 07:57:22 PM UTC 24 |
| Finished | Sep 18 07:57:32 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233474199 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3233474199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/29.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_otbn.3254258724 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 45264217 ps |
| CPU time | 2.22 seconds |
| Started | Sep 18 07:57:23 PM UTC 24 |
| Finished | Sep 18 07:57:26 PM UTC 24 |
| Peak memory | 217404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254258724 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3254258724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/29.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_protect.3376173984 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 71072121 ps |
| CPU time | 2.39 seconds |
| Started | Sep 18 07:57:26 PM UTC 24 |
| Finished | Sep 18 07:57:30 PM UTC 24 |
| Peak memory | 215420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376173984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3376173984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/29.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/29.keymgr_smoke.3748916838 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 134695444 ps |
| CPU time | 3.13 seconds |
| Started | Sep 18 07:57:21 PM UTC 24 |
| Finished | Sep 18 07:57:25 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748916838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3748916838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/29.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all.3885298606 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 215321510 ps |
| CPU time | 10.72 seconds |
| Started | Sep 18 07:57:26 PM UTC 24 |
| Finished | Sep 18 07:57:38 PM UTC 24 |
| Peak memory | 231908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885298606 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3885298606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/29.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all_with_rand_reset.3497223635 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 542971006 ps |
| CPU time | 5.49 seconds |
| Started | Sep 18 07:57:27 PM UTC 24 |
| Finished | Sep 18 07:57:33 PM UTC 24 |
| Peak memory | 231596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3497223635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymg r_stress_all_with_rand_reset.3497223635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/29.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/29.keymgr_sw_invalid_input.2750427786 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 58709036 ps |
| CPU time | 3.87 seconds |
| Started | Sep 18 07:57:24 PM UTC 24 |
| Finished | Sep 18 07:57:29 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750427786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2750427786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/29.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/29.keymgr_sync_async_fault_cross.3151604141 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 56438040 ps |
| CPU time | 3.23 seconds |
| Started | Sep 18 07:57:26 PM UTC 24 |
| Finished | Sep 18 07:57:30 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151604141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3151604141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/29.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/3.keymgr_alert_test.908682184 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 20135580 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 07:54:42 PM UTC 24 |
| Finished | Sep 18 07:54:44 PM UTC 24 |
| Peak memory | 212772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908682184 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.908682184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/3.keymgr_direct_to_disabled.2260408508 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 30941238 ps |
| CPU time | 3.2 seconds |
| Started | Sep 18 07:54:39 PM UTC 24 |
| Finished | Sep 18 07:54:43 PM UTC 24 |
| Peak memory | 223364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260408508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2260408508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/3.keymgr_hwsw_invalid_input.3546635581 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 328110108 ps |
| CPU time | 4.59 seconds |
| Started | Sep 18 07:54:39 PM UTC 24 |
| Finished | Sep 18 07:54:45 PM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546635581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3546635581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/3.keymgr_lc_disable.1584516027 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 73848768 ps |
| CPU time | 3.87 seconds |
| Started | Sep 18 07:54:39 PM UTC 24 |
| Finished | Sep 18 07:54:44 PM UTC 24 |
| Peak memory | 213096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584516027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1584516027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/3.keymgr_random.619695152 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 119201665 ps |
| CPU time | 4.43 seconds |
| Started | Sep 18 07:54:39 PM UTC 24 |
| Finished | Sep 18 07:54:45 PM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619695152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.619695152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/3.keymgr_sec_cm.3181304196 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 599963741 ps |
| CPU time | 6.5 seconds |
| Started | Sep 18 07:54:42 PM UTC 24 |
| Finished | Sep 18 07:54:49 PM UTC 24 |
| Peak memory | 251552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181304196 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3181304196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/3.keymgr_sideload.3050780263 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 24692679 ps |
| CPU time | 2.24 seconds |
| Started | Sep 18 07:54:37 PM UTC 24 |
| Finished | Sep 18 07:54:40 PM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050780263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3050780263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_aes.3296054157 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 18667936542 ps |
| CPU time | 38.76 seconds |
| Started | Sep 18 07:54:37 PM UTC 24 |
| Finished | Sep 18 07:55:17 PM UTC 24 |
| Peak memory | 217380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296054157 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3296054157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_kmac.1476655900 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 72209405 ps |
| CPU time | 4.06 seconds |
| Started | Sep 18 07:54:37 PM UTC 24 |
| Finished | Sep 18 07:54:42 PM UTC 24 |
| Peak memory | 217416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476655900 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1476655900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_otbn.1969132988 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 140402389 ps |
| CPU time | 5.78 seconds |
| Started | Sep 18 07:54:37 PM UTC 24 |
| Finished | Sep 18 07:54:44 PM UTC 24 |
| Peak memory | 217404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969132988 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1969132988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_protect.3925656561 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 424934966 ps |
| CPU time | 4.03 seconds |
| Started | Sep 18 07:54:39 PM UTC 24 |
| Finished | Sep 18 07:54:45 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925656561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3925656561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/3.keymgr_smoke.4261110729 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 329631025 ps |
| CPU time | 4.91 seconds |
| Started | Sep 18 07:54:37 PM UTC 24 |
| Finished | Sep 18 07:54:43 PM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261110729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.4261110729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/3.keymgr_stress_all_with_rand_reset.84519068 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 509727583 ps |
| CPU time | 18.03 seconds |
| Started | Sep 18 07:54:42 PM UTC 24 |
| Finished | Sep 18 07:55:01 PM UTC 24 |
| Peak memory | 231596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=84519068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_s tress_all_with_rand_reset.84519068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/3.keymgr_sw_invalid_input.1751227045 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1228133894 ps |
| CPU time | 38.05 seconds |
| Started | Sep 18 07:54:39 PM UTC 24 |
| Finished | Sep 18 07:55:19 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751227045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1751227045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/30.keymgr_alert_test.1068325537 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 43867134 ps |
| CPU time | 1.14 seconds |
| Started | Sep 18 07:57:32 PM UTC 24 |
| Finished | Sep 18 07:57:35 PM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068325537 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1068325537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/30.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/30.keymgr_custom_cm.2002989228 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 128942400 ps |
| CPU time | 3.68 seconds |
| Started | Sep 18 07:57:31 PM UTC 24 |
| Finished | Sep 18 07:57:36 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002989228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2002989228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/30.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/30.keymgr_direct_to_disabled.1073467749 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 94006697 ps |
| CPU time | 2.54 seconds |
| Started | Sep 18 07:57:29 PM UTC 24 |
| Finished | Sep 18 07:57:33 PM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073467749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1073467749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/30.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/30.keymgr_kmac_rsp_err.2401368912 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 76018397 ps |
| CPU time | 2.79 seconds |
| Started | Sep 18 07:57:31 PM UTC 24 |
| Finished | Sep 18 07:57:35 PM UTC 24 |
| Peak memory | 223340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401368912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2401368912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/30.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/30.keymgr_lc_disable.3667694127 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 226656439 ps |
| CPU time | 4.24 seconds |
| Started | Sep 18 07:57:30 PM UTC 24 |
| Finished | Sep 18 07:57:37 PM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667694127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3667694127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/30.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/30.keymgr_random.2231822458 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 136823536 ps |
| CPU time | 6.17 seconds |
| Started | Sep 18 07:57:29 PM UTC 24 |
| Finished | Sep 18 07:57:37 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231822458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2231822458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/30.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/30.keymgr_sideload.2398029578 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 203702671 ps |
| CPU time | 6.54 seconds |
| Started | Sep 18 07:57:27 PM UTC 24 |
| Finished | Sep 18 07:57:35 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398029578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2398029578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/30.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_aes.265296062 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 113747120 ps |
| CPU time | 2.91 seconds |
| Started | Sep 18 07:57:28 PM UTC 24 |
| Finished | Sep 18 07:57:32 PM UTC 24 |
| Peak memory | 215536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265296062 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.265296062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/30.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_kmac.3234798210 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 1539319257 ps |
| CPU time | 40.07 seconds |
| Started | Sep 18 07:57:28 PM UTC 24 |
| Finished | Sep 18 07:58:10 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234798210 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3234798210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/30.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_otbn.2035515690 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 83298726 ps |
| CPU time | 2.69 seconds |
| Started | Sep 18 07:57:28 PM UTC 24 |
| Finished | Sep 18 07:57:32 PM UTC 24 |
| Peak memory | 217392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035515690 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2035515690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/30.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_protect.3686554023 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 62606515 ps |
| CPU time | 3.19 seconds |
| Started | Sep 18 07:57:31 PM UTC 24 |
| Finished | Sep 18 07:57:36 PM UTC 24 |
| Peak memory | 217612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686554023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3686554023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/30.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/30.keymgr_smoke.364376410 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 158678595 ps |
| CPU time | 2.34 seconds |
| Started | Sep 18 07:57:27 PM UTC 24 |
| Finished | Sep 18 07:57:30 PM UTC 24 |
| Peak memory | 217456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364376410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.364376410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/30.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all.2880490045 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 49148056566 ps |
| CPU time | 245.08 seconds |
| Started | Sep 18 07:57:31 PM UTC 24 |
| Finished | Sep 18 08:01:41 PM UTC 24 |
| Peak memory | 225644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880490045 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2880490045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/30.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all_with_rand_reset.4024747520 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 70755181 ps |
| CPU time | 5.59 seconds |
| Started | Sep 18 07:57:32 PM UTC 24 |
| Finished | Sep 18 07:57:40 PM UTC 24 |
| Peak memory | 231664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4024747520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymg r_stress_all_with_rand_reset.4024747520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/30.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/30.keymgr_sw_invalid_input.2355934645 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 15104557865 ps |
| CPU time | 84.07 seconds |
| Started | Sep 18 07:57:31 PM UTC 24 |
| Finished | Sep 18 07:58:57 PM UTC 24 |
| Peak memory | 219696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355934645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2355934645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/30.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/30.keymgr_sync_async_fault_cross.589525293 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 32090388 ps |
| CPU time | 2.25 seconds |
| Started | Sep 18 07:57:31 PM UTC 24 |
| Finished | Sep 18 07:57:35 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589525293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.589525293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/30.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/31.keymgr_alert_test.413154591 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 17862351 ps |
| CPU time | 0.81 seconds |
| Started | Sep 18 07:57:36 PM UTC 24 |
| Finished | Sep 18 07:57:38 PM UTC 24 |
| Peak memory | 212892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413154591 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.413154591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/31.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/31.keymgr_cfg_regwen.2414843630 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 1094827429 ps |
| CPU time | 52.03 seconds |
| Started | Sep 18 07:57:34 PM UTC 24 |
| Finished | Sep 18 07:58:28 PM UTC 24 |
| Peak memory | 225736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414843630 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2414843630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/31.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/31.keymgr_direct_to_disabled.759245285 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 642595768 ps |
| CPU time | 6.28 seconds |
| Started | Sep 18 07:57:35 PM UTC 24 |
| Finished | Sep 18 07:57:42 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759245285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.759245285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/31.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/31.keymgr_hwsw_invalid_input.1350920911 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 748808182 ps |
| CPU time | 6.32 seconds |
| Started | Sep 18 07:57:36 PM UTC 24 |
| Finished | Sep 18 07:57:43 PM UTC 24 |
| Peak memory | 231440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350920911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1350920911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/31.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/31.keymgr_lc_disable.3409917718 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 97089138 ps |
| CPU time | 4.38 seconds |
| Started | Sep 18 07:57:35 PM UTC 24 |
| Finished | Sep 18 07:57:41 PM UTC 24 |
| Peak memory | 217660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409917718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3409917718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/31.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/31.keymgr_random.989717341 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 160796524 ps |
| CPU time | 3.89 seconds |
| Started | Sep 18 07:57:33 PM UTC 24 |
| Finished | Sep 18 07:57:39 PM UTC 24 |
| Peak memory | 227516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989717341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.989717341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/31.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/31.keymgr_sideload.2425391221 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 31564154 ps |
| CPU time | 2.37 seconds |
| Started | Sep 18 07:57:32 PM UTC 24 |
| Finished | Sep 18 07:57:36 PM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425391221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2425391221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/31.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_aes.3647887404 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 169820222 ps |
| CPU time | 2.8 seconds |
| Started | Sep 18 07:57:33 PM UTC 24 |
| Finished | Sep 18 07:57:38 PM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647887404 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3647887404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/31.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_kmac.160779238 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 298698931 ps |
| CPU time | 3.32 seconds |
| Started | Sep 18 07:57:32 PM UTC 24 |
| Finished | Sep 18 07:57:37 PM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160779238 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.160779238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/31.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_otbn.3956202469 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 137124388 ps |
| CPU time | 4.58 seconds |
| Started | Sep 18 07:57:33 PM UTC 24 |
| Finished | Sep 18 07:57:40 PM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956202469 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3956202469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/31.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_protect.3812831389 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 68486478 ps |
| CPU time | 2.9 seconds |
| Started | Sep 18 07:57:36 PM UTC 24 |
| Finished | Sep 18 07:57:40 PM UTC 24 |
| Peak memory | 217220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812831389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3812831389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/31.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/31.keymgr_smoke.3645600997 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 1160184902 ps |
| CPU time | 21.7 seconds |
| Started | Sep 18 07:57:32 PM UTC 24 |
| Finished | Sep 18 07:57:56 PM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645600997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3645600997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/31.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/31.keymgr_stress_all.1714227076 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 2041713459 ps |
| CPU time | 17.12 seconds |
| Started | Sep 18 07:57:36 PM UTC 24 |
| Finished | Sep 18 07:57:55 PM UTC 24 |
| Peak memory | 227584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714227076 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1714227076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/31.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/31.keymgr_sw_invalid_input.355827300 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 205864937 ps |
| CPU time | 3.06 seconds |
| Started | Sep 18 07:57:35 PM UTC 24 |
| Finished | Sep 18 07:57:39 PM UTC 24 |
| Peak memory | 217320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355827300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.355827300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/31.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/31.keymgr_sync_async_fault_cross.2717041251 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 94287476 ps |
| CPU time | 2.26 seconds |
| Started | Sep 18 07:57:36 PM UTC 24 |
| Finished | Sep 18 07:57:40 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717041251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2717041251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/31.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/32.keymgr_alert_test.1825605049 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 13847237 ps |
| CPU time | 1.05 seconds |
| Started | Sep 18 07:57:42 PM UTC 24 |
| Finished | Sep 18 07:57:44 PM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825605049 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1825605049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/32.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/32.keymgr_cfg_regwen.679004386 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 146735378 ps |
| CPU time | 2.84 seconds |
| Started | Sep 18 07:57:41 PM UTC 24 |
| Finished | Sep 18 07:57:45 PM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679004386 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.679004386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/32.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/32.keymgr_direct_to_disabled.2541689207 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 586325558 ps |
| CPU time | 5.18 seconds |
| Started | Sep 18 07:57:42 PM UTC 24 |
| Finished | Sep 18 07:57:48 PM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541689207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2541689207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/32.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/32.keymgr_hwsw_invalid_input.2902667938 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 266378515 ps |
| CPU time | 3.66 seconds |
| Started | Sep 18 07:57:42 PM UTC 24 |
| Finished | Sep 18 07:57:47 PM UTC 24 |
| Peak memory | 225452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902667938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2902667938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/32.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/32.keymgr_kmac_rsp_err.3589252632 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 287730280 ps |
| CPU time | 4.93 seconds |
| Started | Sep 18 07:57:42 PM UTC 24 |
| Finished | Sep 18 07:57:48 PM UTC 24 |
| Peak memory | 223372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589252632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3589252632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/32.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/32.keymgr_lc_disable.3488704073 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 138668377 ps |
| CPU time | 3.98 seconds |
| Started | Sep 18 07:57:42 PM UTC 24 |
| Finished | Sep 18 07:57:47 PM UTC 24 |
| Peak memory | 223396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488704073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3488704073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/32.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/32.keymgr_random.619554353 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 31950135 ps |
| CPU time | 2.77 seconds |
| Started | Sep 18 07:57:40 PM UTC 24 |
| Finished | Sep 18 07:57:44 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619554353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.619554353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/32.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/32.keymgr_sideload.3149513482 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 47936955 ps |
| CPU time | 2.11 seconds |
| Started | Sep 18 07:57:40 PM UTC 24 |
| Finished | Sep 18 07:57:44 PM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149513482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3149513482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/32.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_aes.1237670275 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 785315097 ps |
| CPU time | 3.32 seconds |
| Started | Sep 18 07:57:40 PM UTC 24 |
| Finished | Sep 18 07:57:45 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237670275 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1237670275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/32.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_kmac.3666094964 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 251957162 ps |
| CPU time | 4.35 seconds |
| Started | Sep 18 07:57:40 PM UTC 24 |
| Finished | Sep 18 07:57:46 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666094964 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3666094964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/32.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_otbn.889996684 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 330444914 ps |
| CPU time | 4.54 seconds |
| Started | Sep 18 07:57:40 PM UTC 24 |
| Finished | Sep 18 07:57:46 PM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889996684 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.889996684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/32.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_protect.375574767 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 56291358 ps |
| CPU time | 3.64 seconds |
| Started | Sep 18 07:57:42 PM UTC 24 |
| Finished | Sep 18 07:57:47 PM UTC 24 |
| Peak memory | 217188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375574767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.375574767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/32.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/32.keymgr_smoke.2052128592 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 881809520 ps |
| CPU time | 17.73 seconds |
| Started | Sep 18 07:57:40 PM UTC 24 |
| Finished | Sep 18 07:57:59 PM UTC 24 |
| Peak memory | 217264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052128592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2052128592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/32.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/32.keymgr_stress_all.692911919 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 566682673 ps |
| CPU time | 29.61 seconds |
| Started | Sep 18 07:57:42 PM UTC 24 |
| Finished | Sep 18 07:58:13 PM UTC 24 |
| Peak memory | 231468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692911919 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.692911919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/32.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/32.keymgr_sw_invalid_input.3700871771 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 235261340 ps |
| CPU time | 5.66 seconds |
| Started | Sep 18 07:57:42 PM UTC 24 |
| Finished | Sep 18 07:57:49 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700871771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3700871771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/32.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/32.keymgr_sync_async_fault_cross.2558232715 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 256803379 ps |
| CPU time | 3.09 seconds |
| Started | Sep 18 07:57:42 PM UTC 24 |
| Finished | Sep 18 07:57:46 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558232715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2558232715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/32.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/33.keymgr_alert_test.570513225 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 17517635 ps |
| CPU time | 1.09 seconds |
| Started | Sep 18 07:57:47 PM UTC 24 |
| Finished | Sep 18 07:57:49 PM UTC 24 |
| Peak memory | 212892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570513225 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.570513225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/33.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/33.keymgr_cfg_regwen.3876417404 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 41973030 ps |
| CPU time | 4.12 seconds |
| Started | Sep 18 07:57:44 PM UTC 24 |
| Finished | Sep 18 07:57:50 PM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876417404 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3876417404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/33.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/33.keymgr_custom_cm.3343890459 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 119288060 ps |
| CPU time | 2.58 seconds |
| Started | Sep 18 07:57:47 PM UTC 24 |
| Finished | Sep 18 07:57:51 PM UTC 24 |
| Peak memory | 228028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343890459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3343890459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/33.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/33.keymgr_direct_to_disabled.3137243594 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 30039088 ps |
| CPU time | 2.58 seconds |
| Started | Sep 18 07:57:45 PM UTC 24 |
| Finished | Sep 18 07:57:48 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137243594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3137243594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/33.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/33.keymgr_hwsw_invalid_input.1226317751 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 36435083 ps |
| CPU time | 2.61 seconds |
| Started | Sep 18 07:57:46 PM UTC 24 |
| Finished | Sep 18 07:57:49 PM UTC 24 |
| Peak memory | 225452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226317751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1226317751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/33.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/33.keymgr_kmac_rsp_err.3133753554 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 146736623 ps |
| CPU time | 6.18 seconds |
| Started | Sep 18 07:57:46 PM UTC 24 |
| Finished | Sep 18 07:57:53 PM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133753554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3133753554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/33.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/33.keymgr_lc_disable.1666665022 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 74289199 ps |
| CPU time | 4.7 seconds |
| Started | Sep 18 07:57:46 PM UTC 24 |
| Finished | Sep 18 07:57:52 PM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666665022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1666665022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/33.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/33.keymgr_random.2670352610 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 544466317 ps |
| CPU time | 10.64 seconds |
| Started | Sep 18 07:57:43 PM UTC 24 |
| Finished | Sep 18 07:57:55 PM UTC 24 |
| Peak memory | 217424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670352610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2670352610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/33.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/33.keymgr_sideload.1134699032 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 52917577 ps |
| CPU time | 2.72 seconds |
| Started | Sep 18 07:57:42 PM UTC 24 |
| Finished | Sep 18 07:57:46 PM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134699032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1134699032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/33.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_aes.1413834040 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 712155148 ps |
| CPU time | 21.95 seconds |
| Started | Sep 18 07:57:42 PM UTC 24 |
| Finished | Sep 18 07:58:06 PM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413834040 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1413834040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/33.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_kmac.405935443 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 37402588 ps |
| CPU time | 2.86 seconds |
| Started | Sep 18 07:57:42 PM UTC 24 |
| Finished | Sep 18 07:57:46 PM UTC 24 |
| Peak memory | 217612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405935443 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.405935443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/33.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_otbn.1455672771 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 1893807462 ps |
| CPU time | 24.67 seconds |
| Started | Sep 18 07:57:43 PM UTC 24 |
| Finished | Sep 18 07:58:10 PM UTC 24 |
| Peak memory | 217180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455672771 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1455672771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/33.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_protect.3771416543 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 157624434 ps |
| CPU time | 3.93 seconds |
| Started | Sep 18 07:57:47 PM UTC 24 |
| Finished | Sep 18 07:57:52 PM UTC 24 |
| Peak memory | 225676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771416543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3771416543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/33.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/33.keymgr_smoke.1453924729 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 187387069 ps |
| CPU time | 6.16 seconds |
| Started | Sep 18 07:57:42 PM UTC 24 |
| Finished | Sep 18 07:57:49 PM UTC 24 |
| Peak memory | 217532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453924729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1453924729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/33.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all_with_rand_reset.671287342 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1520445144 ps |
| CPU time | 9.2 seconds |
| Started | Sep 18 07:57:47 PM UTC 24 |
| Finished | Sep 18 07:57:58 PM UTC 24 |
| Peak memory | 229744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=671287342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr _stress_all_with_rand_reset.671287342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/33.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/33.keymgr_sw_invalid_input.4056908485 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 5974551374 ps |
| CPU time | 60.24 seconds |
| Started | Sep 18 07:57:46 PM UTC 24 |
| Finished | Sep 18 07:58:48 PM UTC 24 |
| Peak memory | 231668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056908485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.4056908485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/33.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/33.keymgr_sync_async_fault_cross.3210447336 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 3880528942 ps |
| CPU time | 36.11 seconds |
| Started | Sep 18 07:57:47 PM UTC 24 |
| Finished | Sep 18 07:58:25 PM UTC 24 |
| Peak memory | 219444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210447336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3210447336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/33.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/34.keymgr_alert_test.2972752240 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 49072773 ps |
| CPU time | 1.08 seconds |
| Started | Sep 18 07:57:54 PM UTC 24 |
| Finished | Sep 18 07:57:56 PM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972752240 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2972752240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/34.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/34.keymgr_cfg_regwen.1920297017 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 110308465 ps |
| CPU time | 2.69 seconds |
| Started | Sep 18 07:57:50 PM UTC 24 |
| Finished | Sep 18 07:57:54 PM UTC 24 |
| Peak memory | 223392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920297017 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1920297017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/34.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/34.keymgr_direct_to_disabled.3683810324 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 184547958 ps |
| CPU time | 3.84 seconds |
| Started | Sep 18 07:57:50 PM UTC 24 |
| Finished | Sep 18 07:57:55 PM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683810324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3683810324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/34.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/34.keymgr_hwsw_invalid_input.2513644690 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 4394790331 ps |
| CPU time | 48.16 seconds |
| Started | Sep 18 07:57:50 PM UTC 24 |
| Finished | Sep 18 07:58:40 PM UTC 24 |
| Peak memory | 231600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513644690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2513644690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/34.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/34.keymgr_kmac_rsp_err.963958490 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 757955062 ps |
| CPU time | 4.43 seconds |
| Started | Sep 18 07:57:51 PM UTC 24 |
| Finished | Sep 18 07:57:57 PM UTC 24 |
| Peak memory | 229488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963958490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.963958490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/34.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/34.keymgr_lc_disable.1346147073 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 146760271 ps |
| CPU time | 5.38 seconds |
| Started | Sep 18 07:57:50 PM UTC 24 |
| Finished | Sep 18 07:57:56 PM UTC 24 |
| Peak memory | 217660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346147073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1346147073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/34.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/34.keymgr_random.1392376906 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 102489599 ps |
| CPU time | 5.49 seconds |
| Started | Sep 18 07:57:48 PM UTC 24 |
| Finished | Sep 18 07:57:55 PM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392376906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1392376906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/34.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/34.keymgr_sideload.3258127006 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 2862500281 ps |
| CPU time | 13.34 seconds |
| Started | Sep 18 07:57:48 PM UTC 24 |
| Finished | Sep 18 07:58:03 PM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258127006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3258127006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/34.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_aes.556252962 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 129239471 ps |
| CPU time | 6.16 seconds |
| Started | Sep 18 07:57:48 PM UTC 24 |
| Finished | Sep 18 07:57:56 PM UTC 24 |
| Peak memory | 215196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556252962 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.556252962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/34.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_kmac.393279731 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 294712152 ps |
| CPU time | 3.57 seconds |
| Started | Sep 18 07:57:48 PM UTC 24 |
| Finished | Sep 18 07:57:53 PM UTC 24 |
| Peak memory | 217512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393279731 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.393279731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/34.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_otbn.4216555479 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 350719197 ps |
| CPU time | 6.69 seconds |
| Started | Sep 18 07:57:48 PM UTC 24 |
| Finished | Sep 18 07:57:57 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216555479 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.4216555479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/34.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_protect.1933696864 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 1455207098 ps |
| CPU time | 9.76 seconds |
| Started | Sep 18 07:57:51 PM UTC 24 |
| Finished | Sep 18 07:58:02 PM UTC 24 |
| Peak memory | 229888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933696864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1933696864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/34.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/34.keymgr_smoke.2889386451 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 156501056 ps |
| CPU time | 5.47 seconds |
| Started | Sep 18 07:57:48 PM UTC 24 |
| Finished | Sep 18 07:57:55 PM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889386451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2889386451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/34.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all.1591623769 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 1307338499 ps |
| CPU time | 33.54 seconds |
| Started | Sep 18 07:57:53 PM UTC 24 |
| Finished | Sep 18 07:58:28 PM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591623769 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1591623769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/34.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/34.keymgr_sw_invalid_input.1182165146 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 602805153 ps |
| CPU time | 6.63 seconds |
| Started | Sep 18 07:57:50 PM UTC 24 |
| Finished | Sep 18 07:57:58 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182165146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1182165146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/34.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/34.keymgr_sync_async_fault_cross.4246376685 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 1131712033 ps |
| CPU time | 2.99 seconds |
| Started | Sep 18 07:57:52 PM UTC 24 |
| Finished | Sep 18 07:57:56 PM UTC 24 |
| Peak memory | 219380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246376685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.4246376685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/34.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/35.keymgr_alert_test.2961816760 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 15199057 ps |
| CPU time | 1.08 seconds |
| Started | Sep 18 07:57:58 PM UTC 24 |
| Finished | Sep 18 07:58:00 PM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961816760 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2961816760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/35.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/35.keymgr_custom_cm.1349009936 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 1854003820 ps |
| CPU time | 6.45 seconds |
| Started | Sep 18 07:57:57 PM UTC 24 |
| Finished | Sep 18 07:58:05 PM UTC 24 |
| Peak memory | 230528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349009936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1349009936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/35.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/35.keymgr_direct_to_disabled.873467597 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 1448764789 ps |
| CPU time | 3.3 seconds |
| Started | Sep 18 07:57:57 PM UTC 24 |
| Finished | Sep 18 07:58:01 PM UTC 24 |
| Peak memory | 227760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873467597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.873467597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/35.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/35.keymgr_hwsw_invalid_input.388754553 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 83512305 ps |
| CPU time | 2.27 seconds |
| Started | Sep 18 07:57:57 PM UTC 24 |
| Finished | Sep 18 07:58:00 PM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388754553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.388754553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/35.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/35.keymgr_kmac_rsp_err.1356543708 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 153478433 ps |
| CPU time | 3.68 seconds |
| Started | Sep 18 07:57:57 PM UTC 24 |
| Finished | Sep 18 07:58:02 PM UTC 24 |
| Peak memory | 225484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356543708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1356543708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/35.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/35.keymgr_lc_disable.3145346727 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 259695263 ps |
| CPU time | 3.51 seconds |
| Started | Sep 18 07:57:57 PM UTC 24 |
| Finished | Sep 18 07:58:01 PM UTC 24 |
| Peak memory | 217292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145346727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3145346727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/35.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/35.keymgr_random.1096661532 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 541779871 ps |
| CPU time | 5.91 seconds |
| Started | Sep 18 07:57:56 PM UTC 24 |
| Finished | Sep 18 07:58:03 PM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096661532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1096661532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/35.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/35.keymgr_sideload.101551424 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 140591957 ps |
| CPU time | 2.44 seconds |
| Started | Sep 18 07:57:54 PM UTC 24 |
| Finished | Sep 18 07:57:58 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101551424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.101551424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/35.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_aes.737194309 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 262567811 ps |
| CPU time | 6.4 seconds |
| Started | Sep 18 07:57:56 PM UTC 24 |
| Finished | Sep 18 07:58:03 PM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737194309 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.737194309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/35.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_kmac.4047180970 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 204025609 ps |
| CPU time | 2.68 seconds |
| Started | Sep 18 07:57:55 PM UTC 24 |
| Finished | Sep 18 07:57:59 PM UTC 24 |
| Peak memory | 215536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047180970 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.4047180970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/35.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_otbn.4256160513 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 87486824 ps |
| CPU time | 3.12 seconds |
| Started | Sep 18 07:57:56 PM UTC 24 |
| Finished | Sep 18 07:58:00 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256160513 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.4256160513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/35.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_protect.657966130 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 37939875 ps |
| CPU time | 2.1 seconds |
| Started | Sep 18 07:57:57 PM UTC 24 |
| Finished | Sep 18 07:58:00 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657966130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.657966130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/35.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/35.keymgr_smoke.759617384 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 225291322 ps |
| CPU time | 4.42 seconds |
| Started | Sep 18 07:57:54 PM UTC 24 |
| Finished | Sep 18 07:58:00 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759617384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.759617384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/35.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/35.keymgr_stress_all_with_rand_reset.3057654723 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 744558220 ps |
| CPU time | 13.96 seconds |
| Started | Sep 18 07:57:58 PM UTC 24 |
| Finished | Sep 18 07:58:13 PM UTC 24 |
| Peak memory | 231644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3057654723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymg r_stress_all_with_rand_reset.3057654723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/35.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/35.keymgr_sw_invalid_input.2982300102 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 143221583 ps |
| CPU time | 4.8 seconds |
| Started | Sep 18 07:57:57 PM UTC 24 |
| Finished | Sep 18 07:58:03 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982300102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2982300102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/35.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/35.keymgr_sync_async_fault_cross.4262089253 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 327510809 ps |
| CPU time | 3.58 seconds |
| Started | Sep 18 07:57:57 PM UTC 24 |
| Finished | Sep 18 07:58:02 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262089253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.4262089253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/35.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/36.keymgr_alert_test.2808343003 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 12425254 ps |
| CPU time | 1.06 seconds |
| Started | Sep 18 07:58:03 PM UTC 24 |
| Finished | Sep 18 07:58:05 PM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808343003 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2808343003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/36.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/36.keymgr_direct_to_disabled.3092959255 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 238260619 ps |
| CPU time | 3.34 seconds |
| Started | Sep 18 07:58:01 PM UTC 24 |
| Finished | Sep 18 07:58:05 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092959255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3092959255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/36.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/36.keymgr_hwsw_invalid_input.1286790722 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 183227728 ps |
| CPU time | 3.08 seconds |
| Started | Sep 18 07:58:01 PM UTC 24 |
| Finished | Sep 18 07:58:05 PM UTC 24 |
| Peak memory | 223396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286790722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1286790722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/36.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/36.keymgr_kmac_rsp_err.2751465867 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 228260058 ps |
| CPU time | 4.56 seconds |
| Started | Sep 18 07:58:02 PM UTC 24 |
| Finished | Sep 18 07:58:08 PM UTC 24 |
| Peak memory | 223364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751465867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2751465867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/36.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/36.keymgr_lc_disable.2998710406 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 159951859 ps |
| CPU time | 3.08 seconds |
| Started | Sep 18 07:58:01 PM UTC 24 |
| Finished | Sep 18 07:58:05 PM UTC 24 |
| Peak memory | 217192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998710406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2998710406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/36.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/36.keymgr_random.1850451381 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 70822755 ps |
| CPU time | 3.74 seconds |
| Started | Sep 18 07:58:01 PM UTC 24 |
| Finished | Sep 18 07:58:06 PM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850451381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1850451381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/36.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/36.keymgr_sideload.2904956319 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 172856795 ps |
| CPU time | 4.24 seconds |
| Started | Sep 18 07:57:58 PM UTC 24 |
| Finished | Sep 18 07:58:04 PM UTC 24 |
| Peak memory | 217420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904956319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2904956319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/36.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_aes.2921730257 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 246018254 ps |
| CPU time | 7.65 seconds |
| Started | Sep 18 07:58:00 PM UTC 24 |
| Finished | Sep 18 07:58:08 PM UTC 24 |
| Peak memory | 217460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921730257 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2921730257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/36.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_kmac.565339560 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 240612774 ps |
| CPU time | 6.15 seconds |
| Started | Sep 18 07:57:59 PM UTC 24 |
| Finished | Sep 18 07:58:07 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565339560 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.565339560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/36.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_otbn.951039195 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 5198542775 ps |
| CPU time | 40.08 seconds |
| Started | Sep 18 07:58:01 PM UTC 24 |
| Finished | Sep 18 07:58:42 PM UTC 24 |
| Peak memory | 215336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951039195 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.951039195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/36.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_protect.2906205934 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 32014504 ps |
| CPU time | 2.95 seconds |
| Started | Sep 18 07:58:02 PM UTC 24 |
| Finished | Sep 18 07:58:06 PM UTC 24 |
| Peak memory | 225448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906205934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2906205934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/36.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/36.keymgr_smoke.900553540 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 1514409786 ps |
| CPU time | 21.39 seconds |
| Started | Sep 18 07:57:58 PM UTC 24 |
| Finished | Sep 18 07:58:21 PM UTC 24 |
| Peak memory | 217480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900553540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.900553540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/36.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/36.keymgr_stress_all.3480373425 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 1234555186 ps |
| CPU time | 11.84 seconds |
| Started | Sep 18 07:58:03 PM UTC 24 |
| Finished | Sep 18 07:58:16 PM UTC 24 |
| Peak memory | 225440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480373425 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3480373425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/36.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/36.keymgr_stress_all_with_rand_reset.3939155454 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 466545482 ps |
| CPU time | 17.49 seconds |
| Started | Sep 18 07:58:03 PM UTC 24 |
| Finished | Sep 18 07:58:22 PM UTC 24 |
| Peak memory | 229816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3939155454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymg r_stress_all_with_rand_reset.3939155454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/36.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/36.keymgr_sw_invalid_input.3400736029 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 1456871930 ps |
| CPU time | 44.42 seconds |
| Started | Sep 18 07:58:01 PM UTC 24 |
| Finished | Sep 18 07:58:47 PM UTC 24 |
| Peak memory | 217392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400736029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3400736029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/36.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/36.keymgr_sync_async_fault_cross.4000518113 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 641388451 ps |
| CPU time | 4.68 seconds |
| Started | Sep 18 07:58:02 PM UTC 24 |
| Finished | Sep 18 07:58:08 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000518113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.4000518113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/36.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/37.keymgr_alert_test.284473216 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 27533081 ps |
| CPU time | 1.31 seconds |
| Started | Sep 18 07:58:09 PM UTC 24 |
| Finished | Sep 18 07:58:11 PM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284473216 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.284473216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/37.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/37.keymgr_custom_cm.2525903366 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 155829824 ps |
| CPU time | 3.32 seconds |
| Started | Sep 18 07:58:07 PM UTC 24 |
| Finished | Sep 18 07:58:12 PM UTC 24 |
| Peak memory | 230520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525903366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2525903366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/37.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/37.keymgr_direct_to_disabled.2363904484 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 135573075 ps |
| CPU time | 3.28 seconds |
| Started | Sep 18 07:58:06 PM UTC 24 |
| Finished | Sep 18 07:58:10 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363904484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2363904484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/37.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/37.keymgr_hwsw_invalid_input.2448449005 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 30916721 ps |
| CPU time | 3.36 seconds |
| Started | Sep 18 07:58:07 PM UTC 24 |
| Finished | Sep 18 07:58:11 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448449005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2448449005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/37.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/37.keymgr_kmac_rsp_err.3238399922 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 33558432 ps |
| CPU time | 2.97 seconds |
| Started | Sep 18 07:58:07 PM UTC 24 |
| Finished | Sep 18 07:58:11 PM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238399922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3238399922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/37.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/37.keymgr_lc_disable.727580833 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 264947066 ps |
| CPU time | 6.22 seconds |
| Started | Sep 18 07:58:06 PM UTC 24 |
| Finished | Sep 18 07:58:13 PM UTC 24 |
| Peak memory | 219460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727580833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.727580833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/37.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/37.keymgr_random.4038960360 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 169490288 ps |
| CPU time | 3.13 seconds |
| Started | Sep 18 07:58:06 PM UTC 24 |
| Finished | Sep 18 07:58:10 PM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038960360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.4038960360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/37.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/37.keymgr_sideload.2293599065 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 19835983 ps |
| CPU time | 2.38 seconds |
| Started | Sep 18 07:58:05 PM UTC 24 |
| Finished | Sep 18 07:58:08 PM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293599065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2293599065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/37.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_aes.281668156 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 174959255 ps |
| CPU time | 4.15 seconds |
| Started | Sep 18 07:58:05 PM UTC 24 |
| Finished | Sep 18 07:58:10 PM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281668156 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.281668156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/37.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_kmac.2436588598 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 414575517 ps |
| CPU time | 8.19 seconds |
| Started | Sep 18 07:58:05 PM UTC 24 |
| Finished | Sep 18 07:58:14 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436588598 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2436588598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/37.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_otbn.2664691774 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 200856087 ps |
| CPU time | 2.98 seconds |
| Started | Sep 18 07:58:06 PM UTC 24 |
| Finished | Sep 18 07:58:10 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664691774 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2664691774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/37.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_protect.3712456019 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 166111207 ps |
| CPU time | 4.16 seconds |
| Started | Sep 18 07:58:08 PM UTC 24 |
| Finished | Sep 18 07:58:14 PM UTC 24 |
| Peak memory | 225716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712456019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3712456019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/37.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/37.keymgr_smoke.3229060459 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 292533002 ps |
| CPU time | 2.83 seconds |
| Started | Sep 18 07:58:03 PM UTC 24 |
| Finished | Sep 18 07:58:07 PM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229060459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3229060459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/37.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all.769088522 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 21182793345 ps |
| CPU time | 315.42 seconds |
| Started | Sep 18 07:58:08 PM UTC 24 |
| Finished | Sep 18 08:03:28 PM UTC 24 |
| Peak memory | 227696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769088522 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.769088522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/37.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all_with_rand_reset.1565204918 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 575174864 ps |
| CPU time | 11.01 seconds |
| Started | Sep 18 07:58:08 PM UTC 24 |
| Finished | Sep 18 07:58:21 PM UTC 24 |
| Peak memory | 230852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1565204918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymg r_stress_all_with_rand_reset.1565204918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/37.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/37.keymgr_sw_invalid_input.1016001640 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 249113659 ps |
| CPU time | 7.59 seconds |
| Started | Sep 18 07:58:07 PM UTC 24 |
| Finished | Sep 18 07:58:16 PM UTC 24 |
| Peak memory | 223420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016001640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1016001640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/37.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/37.keymgr_sync_async_fault_cross.1869191669 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 84583741 ps |
| CPU time | 2.35 seconds |
| Started | Sep 18 07:58:08 PM UTC 24 |
| Finished | Sep 18 07:58:12 PM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869191669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1869191669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/37.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/38.keymgr_alert_test.3199258412 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 60395325 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 07:58:15 PM UTC 24 |
| Finished | Sep 18 07:58:17 PM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199258412 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3199258412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/38.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/38.keymgr_cfg_regwen.2461086467 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 457899782 ps |
| CPU time | 6.73 seconds |
| Started | Sep 18 07:58:11 PM UTC 24 |
| Finished | Sep 18 07:58:19 PM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461086467 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2461086467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/38.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/38.keymgr_direct_to_disabled.1786784875 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 723905891 ps |
| CPU time | 5.45 seconds |
| Started | Sep 18 07:58:11 PM UTC 24 |
| Finished | Sep 18 07:58:18 PM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786784875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1786784875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/38.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/38.keymgr_hwsw_invalid_input.2619320025 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 84202196 ps |
| CPU time | 4.56 seconds |
| Started | Sep 18 07:58:12 PM UTC 24 |
| Finished | Sep 18 07:58:18 PM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619320025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2619320025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/38.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/38.keymgr_kmac_rsp_err.748000141 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 373089354 ps |
| CPU time | 3.39 seconds |
| Started | Sep 18 07:58:12 PM UTC 24 |
| Finished | Sep 18 07:58:17 PM UTC 24 |
| Peak memory | 231816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748000141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.748000141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/38.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/38.keymgr_lc_disable.1053956881 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 280853397 ps |
| CPU time | 4.74 seconds |
| Started | Sep 18 07:58:12 PM UTC 24 |
| Finished | Sep 18 07:58:18 PM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053956881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1053956881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/38.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/38.keymgr_random.4101202255 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 210257321 ps |
| CPU time | 3.76 seconds |
| Started | Sep 18 07:58:11 PM UTC 24 |
| Finished | Sep 18 07:58:16 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101202255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.4101202255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/38.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/38.keymgr_sideload.3562231311 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 25753333 ps |
| CPU time | 2.84 seconds |
| Started | Sep 18 07:58:10 PM UTC 24 |
| Finished | Sep 18 07:58:14 PM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562231311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3562231311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/38.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_aes.2863303413 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 327284802 ps |
| CPU time | 5.52 seconds |
| Started | Sep 18 07:58:11 PM UTC 24 |
| Finished | Sep 18 07:58:17 PM UTC 24 |
| Peak memory | 217248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863303413 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2863303413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/38.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_kmac.263994289 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 16405644473 ps |
| CPU time | 23.35 seconds |
| Started | Sep 18 07:58:11 PM UTC 24 |
| Finished | Sep 18 07:58:35 PM UTC 24 |
| Peak memory | 215600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263994289 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.263994289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/38.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_otbn.568807948 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 2707757521 ps |
| CPU time | 33.75 seconds |
| Started | Sep 18 07:58:11 PM UTC 24 |
| Finished | Sep 18 07:58:46 PM UTC 24 |
| Peak memory | 215336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568807948 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.568807948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/38.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_protect.4280969535 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 372523200 ps |
| CPU time | 2.92 seconds |
| Started | Sep 18 07:58:12 PM UTC 24 |
| Finished | Sep 18 07:58:16 PM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280969535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.4280969535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/38.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/38.keymgr_smoke.322804755 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 852307136 ps |
| CPU time | 5.7 seconds |
| Started | Sep 18 07:58:10 PM UTC 24 |
| Finished | Sep 18 07:58:16 PM UTC 24 |
| Peak memory | 215300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322804755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.322804755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/38.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all.2960805418 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 16542516442 ps |
| CPU time | 90.47 seconds |
| Started | Sep 18 07:58:15 PM UTC 24 |
| Finished | Sep 18 07:59:47 PM UTC 24 |
| Peak memory | 231596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960805418 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2960805418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/38.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all_with_rand_reset.837904095 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 2035246875 ps |
| CPU time | 19.1 seconds |
| Started | Sep 18 07:58:15 PM UTC 24 |
| Finished | Sep 18 07:58:35 PM UTC 24 |
| Peak memory | 229744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=837904095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr _stress_all_with_rand_reset.837904095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/38.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/38.keymgr_sw_invalid_input.1090219239 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 160189336 ps |
| CPU time | 6.57 seconds |
| Started | Sep 18 07:58:12 PM UTC 24 |
| Finished | Sep 18 07:58:20 PM UTC 24 |
| Peak memory | 223560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090219239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1090219239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/38.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/38.keymgr_sync_async_fault_cross.1350194411 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 115184500 ps |
| CPU time | 2.16 seconds |
| Started | Sep 18 07:58:15 PM UTC 24 |
| Finished | Sep 18 07:58:18 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350194411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1350194411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/38.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/39.keymgr_alert_test.2183928302 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 11507415 ps |
| CPU time | 1.17 seconds |
| Started | Sep 18 07:58:20 PM UTC 24 |
| Finished | Sep 18 07:58:22 PM UTC 24 |
| Peak memory | 212500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183928302 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2183928302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/39.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/39.keymgr_custom_cm.1092287238 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 47881625 ps |
| CPU time | 3.53 seconds |
| Started | Sep 18 07:58:19 PM UTC 24 |
| Finished | Sep 18 07:58:23 PM UTC 24 |
| Peak memory | 217344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092287238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1092287238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/39.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/39.keymgr_direct_to_disabled.1917084806 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 26680537 ps |
| CPU time | 2.24 seconds |
| Started | Sep 18 07:58:17 PM UTC 24 |
| Finished | Sep 18 07:58:21 PM UTC 24 |
| Peak memory | 223548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917084806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1917084806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/39.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/39.keymgr_hwsw_invalid_input.570442956 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 127327043 ps |
| CPU time | 5.87 seconds |
| Started | Sep 18 07:58:19 PM UTC 24 |
| Finished | Sep 18 07:58:26 PM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570442956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.570442956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/39.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/39.keymgr_kmac_rsp_err.1024211261 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 46447052 ps |
| CPU time | 4.21 seconds |
| Started | Sep 18 07:58:19 PM UTC 24 |
| Finished | Sep 18 07:58:24 PM UTC 24 |
| Peak memory | 229492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024211261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1024211261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/39.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/39.keymgr_lc_disable.255787570 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 126212616 ps |
| CPU time | 4.96 seconds |
| Started | Sep 18 07:58:17 PM UTC 24 |
| Finished | Sep 18 07:58:24 PM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255787570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.255787570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/39.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/39.keymgr_random.3370175864 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 91560482 ps |
| CPU time | 5.6 seconds |
| Started | Sep 18 07:58:17 PM UTC 24 |
| Finished | Sep 18 07:58:24 PM UTC 24 |
| Peak memory | 223556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370175864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3370175864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/39.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/39.keymgr_sideload.4155237807 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 5219197457 ps |
| CPU time | 48.28 seconds |
| Started | Sep 18 07:58:15 PM UTC 24 |
| Finished | Sep 18 07:59:05 PM UTC 24 |
| Peak memory | 217656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155237807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.4155237807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/39.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_aes.550593019 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 861062993 ps |
| CPU time | 18.41 seconds |
| Started | Sep 18 07:58:16 PM UTC 24 |
| Finished | Sep 18 07:58:36 PM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550593019 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.550593019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/39.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_kmac.2939181452 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 366074142 ps |
| CPU time | 3.43 seconds |
| Started | Sep 18 07:58:16 PM UTC 24 |
| Finished | Sep 18 07:58:21 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939181452 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2939181452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/39.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_otbn.4234437191 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 49483099 ps |
| CPU time | 2.64 seconds |
| Started | Sep 18 07:58:16 PM UTC 24 |
| Finished | Sep 18 07:58:20 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234437191 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.4234437191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/39.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_protect.2236620808 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 292250497 ps |
| CPU time | 3.78 seconds |
| Started | Sep 18 07:58:19 PM UTC 24 |
| Finished | Sep 18 07:58:24 PM UTC 24 |
| Peak memory | 227572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236620808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2236620808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/39.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/39.keymgr_smoke.354377253 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 153896736 ps |
| CPU time | 2.51 seconds |
| Started | Sep 18 07:58:15 PM UTC 24 |
| Finished | Sep 18 07:58:19 PM UTC 24 |
| Peak memory | 215340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354377253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.354377253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/39.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all.753353555 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 904130264 ps |
| CPU time | 15.45 seconds |
| Started | Sep 18 07:58:19 PM UTC 24 |
| Finished | Sep 18 07:58:36 PM UTC 24 |
| Peak memory | 225736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753353555 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.753353555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/39.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all_with_rand_reset.992838668 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 399872141 ps |
| CPU time | 7.6 seconds |
| Started | Sep 18 07:58:19 PM UTC 24 |
| Finished | Sep 18 07:58:28 PM UTC 24 |
| Peak memory | 231748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=992838668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr _stress_all_with_rand_reset.992838668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/39.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/39.keymgr_sw_invalid_input.1534847643 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 138419661 ps |
| CPU time | 4.76 seconds |
| Started | Sep 18 07:58:18 PM UTC 24 |
| Finished | Sep 18 07:58:23 PM UTC 24 |
| Peak memory | 217276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534847643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1534847643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/39.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/39.keymgr_sync_async_fault_cross.3416149621 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 167854197 ps |
| CPU time | 2.12 seconds |
| Started | Sep 18 07:58:19 PM UTC 24 |
| Finished | Sep 18 07:58:22 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416149621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3416149621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/39.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/4.keymgr_alert_test.2759884586 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 26900384 ps |
| CPU time | 1.33 seconds |
| Started | Sep 18 07:54:50 PM UTC 24 |
| Finished | Sep 18 07:54:53 PM UTC 24 |
| Peak memory | 212892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759884586 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2759884586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/4.keymgr_cfg_regwen.1931890045 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 185564223 ps |
| CPU time | 3.82 seconds |
| Started | Sep 18 07:54:45 PM UTC 24 |
| Finished | Sep 18 07:54:50 PM UTC 24 |
| Peak memory | 223396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931890045 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1931890045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/4.keymgr_direct_to_disabled.2292978972 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 147068878 ps |
| CPU time | 3.37 seconds |
| Started | Sep 18 07:54:45 PM UTC 24 |
| Finished | Sep 18 07:54:50 PM UTC 24 |
| Peak memory | 217656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292978972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2292978972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/4.keymgr_kmac_rsp_err.357525342 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 78344822 ps |
| CPU time | 5.22 seconds |
| Started | Sep 18 07:54:48 PM UTC 24 |
| Finished | Sep 18 07:54:54 PM UTC 24 |
| Peak memory | 223612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357525342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.357525342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/4.keymgr_lc_disable.2409462439 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 199754927 ps |
| CPU time | 3.53 seconds |
| Started | Sep 18 07:54:45 PM UTC 24 |
| Finished | Sep 18 07:54:50 PM UTC 24 |
| Peak memory | 223172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409462439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2409462439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/4.keymgr_random.2890158446 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 374815126 ps |
| CPU time | 4.82 seconds |
| Started | Sep 18 07:54:45 PM UTC 24 |
| Finished | Sep 18 07:54:51 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890158446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2890158446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/4.keymgr_sec_cm.856522626 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 847836999 ps |
| CPU time | 22.2 seconds |
| Started | Sep 18 07:54:50 PM UTC 24 |
| Finished | Sep 18 07:55:14 PM UTC 24 |
| Peak memory | 261460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856522626 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.856522626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/4.keymgr_sideload.642122223 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 415059871 ps |
| CPU time | 5.1 seconds |
| Started | Sep 18 07:54:44 PM UTC 24 |
| Finished | Sep 18 07:54:50 PM UTC 24 |
| Peak memory | 217236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642122223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.642122223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_aes.4090744632 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 3878448588 ps |
| CPU time | 44.71 seconds |
| Started | Sep 18 07:54:45 PM UTC 24 |
| Finished | Sep 18 07:55:31 PM UTC 24 |
| Peak memory | 217576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090744632 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.4090744632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_kmac.2774227773 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 285670416 ps |
| CPU time | 11.51 seconds |
| Started | Sep 18 07:54:44 PM UTC 24 |
| Finished | Sep 18 07:54:57 PM UTC 24 |
| Peak memory | 215116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774227773 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2774227773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_otbn.3738844336 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 581769004 ps |
| CPU time | 16.54 seconds |
| Started | Sep 18 07:54:45 PM UTC 24 |
| Finished | Sep 18 07:55:03 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738844336 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3738844336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_protect.1412840534 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 134992504 ps |
| CPU time | 2.94 seconds |
| Started | Sep 18 07:54:48 PM UTC 24 |
| Finished | Sep 18 07:54:52 PM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412840534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1412840534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/4.keymgr_smoke.2425197061 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 6200173307 ps |
| CPU time | 27.46 seconds |
| Started | Sep 18 07:54:44 PM UTC 24 |
| Finished | Sep 18 07:55:13 PM UTC 24 |
| Peak memory | 217420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425197061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2425197061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/4.keymgr_sw_invalid_input.2424953743 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3634101150 ps |
| CPU time | 24.78 seconds |
| Started | Sep 18 07:54:45 PM UTC 24 |
| Finished | Sep 18 07:55:12 PM UTC 24 |
| Peak memory | 217644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424953743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2424953743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/4.keymgr_sync_async_fault_cross.2211497662 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 111814950 ps |
| CPU time | 2.21 seconds |
| Started | Sep 18 07:54:49 PM UTC 24 |
| Finished | Sep 18 07:54:52 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211497662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2211497662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/4.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/40.keymgr_alert_test.3212381261 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 52703904 ps |
| CPU time | 0.82 seconds |
| Started | Sep 18 07:58:25 PM UTC 24 |
| Finished | Sep 18 07:58:27 PM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212381261 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3212381261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/40.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/40.keymgr_cfg_regwen.3893865318 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 2347875129 ps |
| CPU time | 12.89 seconds |
| Started | Sep 18 07:58:22 PM UTC 24 |
| Finished | Sep 18 07:58:36 PM UTC 24 |
| Peak memory | 225852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893865318 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3893865318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/40.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/40.keymgr_custom_cm.1968766200 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 70514603 ps |
| CPU time | 3.29 seconds |
| Started | Sep 18 07:58:24 PM UTC 24 |
| Finished | Sep 18 07:58:29 PM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968766200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1968766200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/40.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/40.keymgr_direct_to_disabled.231078836 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 5810971788 ps |
| CPU time | 39.13 seconds |
| Started | Sep 18 07:58:23 PM UTC 24 |
| Finished | Sep 18 07:59:04 PM UTC 24 |
| Peak memory | 227964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231078836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.231078836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/40.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/40.keymgr_hwsw_invalid_input.341034367 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 232058987 ps |
| CPU time | 5.44 seconds |
| Started | Sep 18 07:58:24 PM UTC 24 |
| Finished | Sep 18 07:58:31 PM UTC 24 |
| Peak memory | 223756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341034367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.341034367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/40.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/40.keymgr_kmac_rsp_err.2247641106 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 81789658 ps |
| CPU time | 4.94 seconds |
| Started | Sep 18 07:58:24 PM UTC 24 |
| Finished | Sep 18 07:58:30 PM UTC 24 |
| Peak memory | 230228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247641106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2247641106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/40.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/40.keymgr_lc_disable.1888310819 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 113272891 ps |
| CPU time | 5.57 seconds |
| Started | Sep 18 07:58:23 PM UTC 24 |
| Finished | Sep 18 07:58:30 PM UTC 24 |
| Peak memory | 229544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888310819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1888310819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/40.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/40.keymgr_random.3209747101 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 2012733039 ps |
| CPU time | 13.33 seconds |
| Started | Sep 18 07:58:22 PM UTC 24 |
| Finished | Sep 18 07:58:36 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209747101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3209747101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/40.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/40.keymgr_sideload.2258921582 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 114047110 ps |
| CPU time | 3.28 seconds |
| Started | Sep 18 07:58:21 PM UTC 24 |
| Finished | Sep 18 07:58:26 PM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258921582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2258921582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/40.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_aes.4198631223 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 86539465 ps |
| CPU time | 3.73 seconds |
| Started | Sep 18 07:58:21 PM UTC 24 |
| Finished | Sep 18 07:58:26 PM UTC 24 |
| Peak memory | 217304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198631223 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.4198631223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/40.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_kmac.3423068036 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 61579640 ps |
| CPU time | 2.95 seconds |
| Started | Sep 18 07:58:21 PM UTC 24 |
| Finished | Sep 18 07:58:26 PM UTC 24 |
| Peak memory | 215460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423068036 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3423068036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/40.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_otbn.921079650 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 92343009 ps |
| CPU time | 5.15 seconds |
| Started | Sep 18 07:58:22 PM UTC 24 |
| Finished | Sep 18 07:58:28 PM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921079650 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.921079650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/40.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_protect.3436823613 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 267294636 ps |
| CPU time | 5.5 seconds |
| Started | Sep 18 07:58:25 PM UTC 24 |
| Finished | Sep 18 07:58:32 PM UTC 24 |
| Peak memory | 217536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436823613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3436823613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/40.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/40.keymgr_smoke.3280876234 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 40246021 ps |
| CPU time | 3.16 seconds |
| Started | Sep 18 07:58:20 PM UTC 24 |
| Finished | Sep 18 07:58:24 PM UTC 24 |
| Peak memory | 217596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280876234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3280876234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/40.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all.4052029732 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 19427578715 ps |
| CPU time | 110.74 seconds |
| Started | Sep 18 07:58:25 PM UTC 24 |
| Finished | Sep 18 08:00:18 PM UTC 24 |
| Peak memory | 227696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052029732 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.4052029732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/40.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all_with_rand_reset.4050896121 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 551148555 ps |
| CPU time | 18.42 seconds |
| Started | Sep 18 07:58:25 PM UTC 24 |
| Finished | Sep 18 07:58:45 PM UTC 24 |
| Peak memory | 230316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4050896121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymg r_stress_all_with_rand_reset.4050896121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/40.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/40.keymgr_sw_invalid_input.2888619576 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 293268967 ps |
| CPU time | 6.63 seconds |
| Started | Sep 18 07:58:23 PM UTC 24 |
| Finished | Sep 18 07:58:31 PM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888619576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2888619576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/40.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/40.keymgr_sync_async_fault_cross.2169833066 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 49065850 ps |
| CPU time | 2.17 seconds |
| Started | Sep 18 07:58:25 PM UTC 24 |
| Finished | Sep 18 07:58:29 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169833066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2169833066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/40.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/41.keymgr_alert_test.3360770889 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 20061020 ps |
| CPU time | 1.2 seconds |
| Started | Sep 18 07:58:33 PM UTC 24 |
| Finished | Sep 18 07:58:35 PM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360770889 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3360770889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/41.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/41.keymgr_cfg_regwen.183673224 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 54335495 ps |
| CPU time | 4.23 seconds |
| Started | Sep 18 07:58:29 PM UTC 24 |
| Finished | Sep 18 07:58:34 PM UTC 24 |
| Peak memory | 225444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183673224 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.183673224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/41.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/41.keymgr_direct_to_disabled.3278779684 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 65451666 ps |
| CPU time | 3.1 seconds |
| Started | Sep 18 07:58:29 PM UTC 24 |
| Finished | Sep 18 07:58:33 PM UTC 24 |
| Peak memory | 217248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278779684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3278779684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/41.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/41.keymgr_kmac_rsp_err.4065186245 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 188312869 ps |
| CPU time | 2.6 seconds |
| Started | Sep 18 07:58:30 PM UTC 24 |
| Finished | Sep 18 07:58:34 PM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065186245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.4065186245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/41.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/41.keymgr_lc_disable.3075864034 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 221842185 ps |
| CPU time | 3.87 seconds |
| Started | Sep 18 07:58:29 PM UTC 24 |
| Finished | Sep 18 07:58:34 PM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075864034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3075864034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/41.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/41.keymgr_random.3393074350 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 178912706 ps |
| CPU time | 7.43 seconds |
| Started | Sep 18 07:58:29 PM UTC 24 |
| Finished | Sep 18 07:58:38 PM UTC 24 |
| Peak memory | 223492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393074350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3393074350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/41.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/41.keymgr_sideload.2075513348 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 207071112 ps |
| CPU time | 7.72 seconds |
| Started | Sep 18 07:58:27 PM UTC 24 |
| Finished | Sep 18 07:58:35 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075513348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2075513348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/41.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_aes.4015698121 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 49469890 ps |
| CPU time | 2.89 seconds |
| Started | Sep 18 07:58:28 PM UTC 24 |
| Finished | Sep 18 07:58:32 PM UTC 24 |
| Peak memory | 217512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015698121 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.4015698121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/41.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_kmac.3543187143 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 158455835 ps |
| CPU time | 3.31 seconds |
| Started | Sep 18 07:58:27 PM UTC 24 |
| Finished | Sep 18 07:58:31 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543187143 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3543187143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/41.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_otbn.1390594964 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 172997496 ps |
| CPU time | 4.27 seconds |
| Started | Sep 18 07:58:28 PM UTC 24 |
| Finished | Sep 18 07:58:33 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390594964 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1390594964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/41.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_protect.3830253768 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 112675976 ps |
| CPU time | 4.28 seconds |
| Started | Sep 18 07:58:31 PM UTC 24 |
| Finished | Sep 18 07:58:37 PM UTC 24 |
| Peak memory | 227572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830253768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3830253768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/41.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/41.keymgr_smoke.3819923117 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 4266577525 ps |
| CPU time | 15.01 seconds |
| Started | Sep 18 07:58:26 PM UTC 24 |
| Finished | Sep 18 07:58:43 PM UTC 24 |
| Peak memory | 217392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819923117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3819923117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/41.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all.345214880 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 3314354489 ps |
| CPU time | 11.89 seconds |
| Started | Sep 18 07:58:33 PM UTC 24 |
| Finished | Sep 18 07:58:45 PM UTC 24 |
| Peak memory | 227700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345214880 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.345214880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/41.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all_with_rand_reset.1676748050 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 833125035 ps |
| CPU time | 9.8 seconds |
| Started | Sep 18 07:58:33 PM UTC 24 |
| Finished | Sep 18 07:58:43 PM UTC 24 |
| Peak memory | 231732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1676748050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymg r_stress_all_with_rand_reset.1676748050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/41.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/41.keymgr_sw_invalid_input.1921623111 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 118657970 ps |
| CPU time | 6.7 seconds |
| Started | Sep 18 07:58:29 PM UTC 24 |
| Finished | Sep 18 07:58:37 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921623111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1921623111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/41.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/41.keymgr_sync_async_fault_cross.3534804953 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 100083796 ps |
| CPU time | 2.68 seconds |
| Started | Sep 18 07:58:31 PM UTC 24 |
| Finished | Sep 18 07:58:35 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534804953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3534804953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/41.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/42.keymgr_alert_test.1967002367 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 15910232 ps |
| CPU time | 1.33 seconds |
| Started | Sep 18 07:58:38 PM UTC 24 |
| Finished | Sep 18 07:58:40 PM UTC 24 |
| Peak memory | 212832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967002367 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1967002367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/42.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/42.keymgr_cfg_regwen.1191254695 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 58210973 ps |
| CPU time | 3.6 seconds |
| Started | Sep 18 07:58:36 PM UTC 24 |
| Finished | Sep 18 07:58:41 PM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191254695 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1191254695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/42.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/42.keymgr_custom_cm.1534703919 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 1161949644 ps |
| CPU time | 7.88 seconds |
| Started | Sep 18 07:58:38 PM UTC 24 |
| Finished | Sep 18 07:58:47 PM UTC 24 |
| Peak memory | 231860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534703919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1534703919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/42.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/42.keymgr_direct_to_disabled.4184478674 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 335777690 ps |
| CPU time | 4.18 seconds |
| Started | Sep 18 07:58:36 PM UTC 24 |
| Finished | Sep 18 07:58:41 PM UTC 24 |
| Peak memory | 227892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184478674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.4184478674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/42.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/42.keymgr_hwsw_invalid_input.3103877848 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 349777047 ps |
| CPU time | 4.11 seconds |
| Started | Sep 18 07:58:36 PM UTC 24 |
| Finished | Sep 18 07:58:42 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103877848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3103877848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/42.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/42.keymgr_kmac_rsp_err.647443896 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 33046092 ps |
| CPU time | 2.32 seconds |
| Started | Sep 18 07:58:36 PM UTC 24 |
| Finished | Sep 18 07:58:40 PM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647443896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.647443896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/42.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/42.keymgr_lc_disable.184476438 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 53317807 ps |
| CPU time | 3 seconds |
| Started | Sep 18 07:58:36 PM UTC 24 |
| Finished | Sep 18 07:58:40 PM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184476438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.184476438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/42.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/42.keymgr_random.2460401276 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 223422374 ps |
| CPU time | 5.9 seconds |
| Started | Sep 18 07:58:36 PM UTC 24 |
| Finished | Sep 18 07:58:43 PM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460401276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2460401276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/42.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/42.keymgr_sideload.4061456855 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 66045299 ps |
| CPU time | 2.81 seconds |
| Started | Sep 18 07:58:34 PM UTC 24 |
| Finished | Sep 18 07:58:38 PM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061456855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.4061456855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/42.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_aes.3152418553 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 63820228 ps |
| CPU time | 3.38 seconds |
| Started | Sep 18 07:58:35 PM UTC 24 |
| Finished | Sep 18 07:58:39 PM UTC 24 |
| Peak memory | 217320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152418553 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3152418553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/42.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_kmac.896103387 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 849034162 ps |
| CPU time | 5.9 seconds |
| Started | Sep 18 07:58:35 PM UTC 24 |
| Finished | Sep 18 07:58:42 PM UTC 24 |
| Peak memory | 217392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896103387 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.896103387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/42.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_otbn.3106123307 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 357294119 ps |
| CPU time | 4.78 seconds |
| Started | Sep 18 07:58:35 PM UTC 24 |
| Finished | Sep 18 07:58:41 PM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106123307 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3106123307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/42.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_protect.2181197511 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 126809065 ps |
| CPU time | 4.02 seconds |
| Started | Sep 18 07:58:38 PM UTC 24 |
| Finished | Sep 18 07:58:43 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181197511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2181197511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/42.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/42.keymgr_smoke.2847512923 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 133202790 ps |
| CPU time | 2.38 seconds |
| Started | Sep 18 07:58:34 PM UTC 24 |
| Finished | Sep 18 07:58:37 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847512923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2847512923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/42.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all.3476302998 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 1390906759 ps |
| CPU time | 26.96 seconds |
| Started | Sep 18 07:58:38 PM UTC 24 |
| Finished | Sep 18 07:59:06 PM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476302998 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3476302998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/42.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/42.keymgr_sw_invalid_input.1818166693 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 74616288 ps |
| CPU time | 3.76 seconds |
| Started | Sep 18 07:58:36 PM UTC 24 |
| Finished | Sep 18 07:58:41 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818166693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1818166693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/42.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/42.keymgr_sync_async_fault_cross.1092665049 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 129892955 ps |
| CPU time | 2.81 seconds |
| Started | Sep 18 07:58:38 PM UTC 24 |
| Finished | Sep 18 07:58:42 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092665049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1092665049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/42.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/43.keymgr_alert_test.342760761 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 79246816 ps |
| CPU time | 1.22 seconds |
| Started | Sep 18 07:58:43 PM UTC 24 |
| Finished | Sep 18 07:58:45 PM UTC 24 |
| Peak memory | 212892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342760761 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.342760761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/43.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/43.keymgr_cfg_regwen.89240927 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 262707328 ps |
| CPU time | 2.86 seconds |
| Started | Sep 18 07:58:41 PM UTC 24 |
| Finished | Sep 18 07:58:45 PM UTC 24 |
| Peak memory | 225440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89240927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keym gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.89240927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/43.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/43.keymgr_custom_cm.3477266907 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 3251020105 ps |
| CPU time | 25.5 seconds |
| Started | Sep 18 07:58:43 PM UTC 24 |
| Finished | Sep 18 07:59:10 PM UTC 24 |
| Peak memory | 217408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477266907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3477266907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/43.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/43.keymgr_direct_to_disabled.2503674754 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 341180216 ps |
| CPU time | 3.05 seconds |
| Started | Sep 18 07:58:41 PM UTC 24 |
| Finished | Sep 18 07:58:46 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503674754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2503674754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/43.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/43.keymgr_hwsw_invalid_input.3499917857 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 156249892 ps |
| CPU time | 4.73 seconds |
| Started | Sep 18 07:58:42 PM UTC 24 |
| Finished | Sep 18 07:58:47 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499917857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3499917857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/43.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/43.keymgr_lc_disable.3656966380 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 369102840 ps |
| CPU time | 7.21 seconds |
| Started | Sep 18 07:58:42 PM UTC 24 |
| Finished | Sep 18 07:58:50 PM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656966380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3656966380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/43.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/43.keymgr_random.3524039703 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 116658943 ps |
| CPU time | 4.2 seconds |
| Started | Sep 18 07:58:40 PM UTC 24 |
| Finished | Sep 18 07:58:46 PM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524039703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3524039703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/43.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/43.keymgr_sideload.2817910912 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 42382097 ps |
| CPU time | 2.37 seconds |
| Started | Sep 18 07:58:39 PM UTC 24 |
| Finished | Sep 18 07:58:42 PM UTC 24 |
| Peak memory | 217472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817910912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2817910912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/43.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_aes.4107581030 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 79389763 ps |
| CPU time | 3.21 seconds |
| Started | Sep 18 07:58:40 PM UTC 24 |
| Finished | Sep 18 07:58:44 PM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107581030 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.4107581030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/43.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_kmac.1725079215 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 74222738 ps |
| CPU time | 3.2 seconds |
| Started | Sep 18 07:58:39 PM UTC 24 |
| Finished | Sep 18 07:58:43 PM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725079215 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1725079215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/43.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_otbn.2022222728 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 3384165647 ps |
| CPU time | 16.26 seconds |
| Started | Sep 18 07:58:40 PM UTC 24 |
| Finished | Sep 18 07:58:58 PM UTC 24 |
| Peak memory | 217468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022222728 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2022222728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/43.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_protect.3653303689 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 18427620343 ps |
| CPU time | 31.19 seconds |
| Started | Sep 18 07:58:43 PM UTC 24 |
| Finished | Sep 18 07:59:15 PM UTC 24 |
| Peak memory | 229676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653303689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3653303689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/43.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/43.keymgr_smoke.2361016417 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 263665191 ps |
| CPU time | 3.38 seconds |
| Started | Sep 18 07:58:38 PM UTC 24 |
| Finished | Sep 18 07:58:42 PM UTC 24 |
| Peak memory | 217392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361016417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2361016417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/43.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/43.keymgr_stress_all.1014009386 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 759239567 ps |
| CPU time | 12.48 seconds |
| Started | Sep 18 07:58:43 PM UTC 24 |
| Finished | Sep 18 07:58:57 PM UTC 24 |
| Peak memory | 229704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014009386 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1014009386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/43.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/43.keymgr_sw_invalid_input.3979139472 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 655035054 ps |
| CPU time | 18.72 seconds |
| Started | Sep 18 07:58:42 PM UTC 24 |
| Finished | Sep 18 07:59:02 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979139472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3979139472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/43.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/43.keymgr_sync_async_fault_cross.250398418 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 155168656 ps |
| CPU time | 2.3 seconds |
| Started | Sep 18 07:58:43 PM UTC 24 |
| Finished | Sep 18 07:58:46 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250398418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.250398418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/43.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/44.keymgr_alert_test.2721408929 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 11851960 ps |
| CPU time | 1.29 seconds |
| Started | Sep 18 07:58:48 PM UTC 24 |
| Finished | Sep 18 07:58:51 PM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721408929 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2721408929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/44.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/44.keymgr_cfg_regwen.1325298905 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 37726344 ps |
| CPU time | 3.7 seconds |
| Started | Sep 18 07:58:46 PM UTC 24 |
| Finished | Sep 18 07:58:50 PM UTC 24 |
| Peak memory | 225528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325298905 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1325298905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/44.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/44.keymgr_custom_cm.3625827639 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 74219823 ps |
| CPU time | 4.2 seconds |
| Started | Sep 18 07:58:47 PM UTC 24 |
| Finished | Sep 18 07:58:52 PM UTC 24 |
| Peak memory | 223816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625827639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3625827639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/44.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/44.keymgr_direct_to_disabled.1252126809 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 33447323 ps |
| CPU time | 2.73 seconds |
| Started | Sep 18 07:58:46 PM UTC 24 |
| Finished | Sep 18 07:58:49 PM UTC 24 |
| Peak memory | 215612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252126809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1252126809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/44.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/44.keymgr_hwsw_invalid_input.1548440247 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 88943160 ps |
| CPU time | 4.89 seconds |
| Started | Sep 18 07:58:47 PM UTC 24 |
| Finished | Sep 18 07:58:53 PM UTC 24 |
| Peak memory | 219312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548440247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1548440247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/44.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/44.keymgr_kmac_rsp_err.104052140 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 122108300 ps |
| CPU time | 4.68 seconds |
| Started | Sep 18 07:58:47 PM UTC 24 |
| Finished | Sep 18 07:58:53 PM UTC 24 |
| Peak memory | 223744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104052140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.104052140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/44.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/44.keymgr_lc_disable.2377875389 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 185765429 ps |
| CPU time | 3.45 seconds |
| Started | Sep 18 07:58:46 PM UTC 24 |
| Finished | Sep 18 07:58:50 PM UTC 24 |
| Peak memory | 229544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377875389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2377875389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/44.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/44.keymgr_random.3570496419 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 562470011 ps |
| CPU time | 4.51 seconds |
| Started | Sep 18 07:58:45 PM UTC 24 |
| Finished | Sep 18 07:58:50 PM UTC 24 |
| Peak memory | 217604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570496419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3570496419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/44.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/44.keymgr_sideload.436318670 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 518163616 ps |
| CPU time | 7.42 seconds |
| Started | Sep 18 07:58:44 PM UTC 24 |
| Finished | Sep 18 07:58:53 PM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436318670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.436318670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/44.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_aes.3304651682 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 51067386 ps |
| CPU time | 2.87 seconds |
| Started | Sep 18 07:58:44 PM UTC 24 |
| Finished | Sep 18 07:58:48 PM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304651682 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3304651682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/44.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_kmac.255120880 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 1232929895 ps |
| CPU time | 6.14 seconds |
| Started | Sep 18 07:58:44 PM UTC 24 |
| Finished | Sep 18 07:58:51 PM UTC 24 |
| Peak memory | 217660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255120880 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.255120880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/44.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_otbn.384181896 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 605768381 ps |
| CPU time | 18.92 seconds |
| Started | Sep 18 07:58:44 PM UTC 24 |
| Finished | Sep 18 07:59:05 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384181896 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.384181896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/44.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_protect.1808026446 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 79776926 ps |
| CPU time | 2.78 seconds |
| Started | Sep 18 07:58:47 PM UTC 24 |
| Finished | Sep 18 07:58:51 PM UTC 24 |
| Peak memory | 215168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808026446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1808026446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/44.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/44.keymgr_smoke.243719143 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 194472171 ps |
| CPU time | 4.08 seconds |
| Started | Sep 18 07:58:43 PM UTC 24 |
| Finished | Sep 18 07:58:48 PM UTC 24 |
| Peak memory | 217192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243719143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.243719143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/44.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/44.keymgr_stress_all.800127239 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 420733037 ps |
| CPU time | 20.35 seconds |
| Started | Sep 18 07:58:48 PM UTC 24 |
| Finished | Sep 18 07:59:10 PM UTC 24 |
| Peak memory | 231468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800127239 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.800127239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/44.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/44.keymgr_sw_invalid_input.598116370 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 145975848 ps |
| CPU time | 5.37 seconds |
| Started | Sep 18 07:58:46 PM UTC 24 |
| Finished | Sep 18 07:58:52 PM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598116370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.598116370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/44.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/44.keymgr_sync_async_fault_cross.1708170906 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 41705476 ps |
| CPU time | 1.77 seconds |
| Started | Sep 18 07:58:47 PM UTC 24 |
| Finished | Sep 18 07:58:50 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708170906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1708170906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/44.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/45.keymgr_alert_test.1219251658 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 11409756 ps |
| CPU time | 1.27 seconds |
| Started | Sep 18 07:58:54 PM UTC 24 |
| Finished | Sep 18 07:58:56 PM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219251658 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1219251658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/45.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/45.keymgr_cfg_regwen.2573680000 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 4794597903 ps |
| CPU time | 95.43 seconds |
| Started | Sep 18 07:58:51 PM UTC 24 |
| Finished | Sep 18 08:00:28 PM UTC 24 |
| Peak memory | 225552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573680000 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2573680000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/45.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/45.keymgr_custom_cm.1740018437 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 92061195 ps |
| CPU time | 2.6 seconds |
| Started | Sep 18 07:58:52 PM UTC 24 |
| Finished | Sep 18 07:58:56 PM UTC 24 |
| Peak memory | 227908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740018437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1740018437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/45.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/45.keymgr_direct_to_disabled.1034104442 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 67189126 ps |
| CPU time | 2.8 seconds |
| Started | Sep 18 07:58:51 PM UTC 24 |
| Finished | Sep 18 07:58:55 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034104442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1034104442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/45.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/45.keymgr_hwsw_invalid_input.4287321138 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 105600697 ps |
| CPU time | 4.63 seconds |
| Started | Sep 18 07:58:51 PM UTC 24 |
| Finished | Sep 18 07:58:57 PM UTC 24 |
| Peak memory | 231260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287321138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.4287321138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/45.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/45.keymgr_kmac_rsp_err.2338355440 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 199839308 ps |
| CPU time | 3.05 seconds |
| Started | Sep 18 07:58:52 PM UTC 24 |
| Finished | Sep 18 07:58:56 PM UTC 24 |
| Peak memory | 223336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338355440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2338355440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/45.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/45.keymgr_lc_disable.277696461 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 51218276 ps |
| CPU time | 4.03 seconds |
| Started | Sep 18 07:58:51 PM UTC 24 |
| Finished | Sep 18 07:58:56 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277696461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.277696461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/45.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/45.keymgr_random.1783056920 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 1164929975 ps |
| CPU time | 30.51 seconds |
| Started | Sep 18 07:58:51 PM UTC 24 |
| Finished | Sep 18 07:59:23 PM UTC 24 |
| Peak memory | 217224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783056920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1783056920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/45.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/45.keymgr_sideload.1727725243 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 459077942 ps |
| CPU time | 5.49 seconds |
| Started | Sep 18 07:58:48 PM UTC 24 |
| Finished | Sep 18 07:58:55 PM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727725243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1727725243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/45.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_aes.607210334 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 944384430 ps |
| CPU time | 8.5 seconds |
| Started | Sep 18 07:58:50 PM UTC 24 |
| Finished | Sep 18 07:58:59 PM UTC 24 |
| Peak memory | 217248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607210334 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.607210334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/45.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_kmac.341182442 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 126376811 ps |
| CPU time | 2.07 seconds |
| Started | Sep 18 07:58:48 PM UTC 24 |
| Finished | Sep 18 07:58:52 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341182442 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.341182442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/45.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_otbn.766231737 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 1427188203 ps |
| CPU time | 8.58 seconds |
| Started | Sep 18 07:58:50 PM UTC 24 |
| Finished | Sep 18 07:58:59 PM UTC 24 |
| Peak memory | 217596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766231737 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.766231737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/45.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_protect.101691412 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 30073612 ps |
| CPU time | 2.46 seconds |
| Started | Sep 18 07:58:52 PM UTC 24 |
| Finished | Sep 18 07:58:56 PM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101691412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.101691412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/45.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/45.keymgr_smoke.865626359 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 41631769 ps |
| CPU time | 2.33 seconds |
| Started | Sep 18 07:58:48 PM UTC 24 |
| Finished | Sep 18 07:58:52 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865626359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.865626359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/45.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/45.keymgr_stress_all.3650255084 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 127232211 ps |
| CPU time | 5.38 seconds |
| Started | Sep 18 07:58:52 PM UTC 24 |
| Finished | Sep 18 07:58:59 PM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650255084 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3650255084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/45.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/45.keymgr_sw_invalid_input.3191382191 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 273437555 ps |
| CPU time | 3.57 seconds |
| Started | Sep 18 07:58:51 PM UTC 24 |
| Finished | Sep 18 07:58:56 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191382191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3191382191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/45.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/45.keymgr_sync_async_fault_cross.423762964 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 106076516 ps |
| CPU time | 4.96 seconds |
| Started | Sep 18 07:58:52 PM UTC 24 |
| Finished | Sep 18 07:58:58 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423762964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.423762964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/45.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/46.keymgr_alert_test.2027665065 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 114062963 ps |
| CPU time | 1.11 seconds |
| Started | Sep 18 07:58:59 PM UTC 24 |
| Finished | Sep 18 07:59:01 PM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027665065 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2027665065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/46.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/46.keymgr_cfg_regwen.2020892252 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 64763172 ps |
| CPU time | 2.69 seconds |
| Started | Sep 18 07:58:56 PM UTC 24 |
| Finished | Sep 18 07:59:00 PM UTC 24 |
| Peak memory | 223804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020892252 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2020892252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/46.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/46.keymgr_custom_cm.141892654 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 403927161 ps |
| CPU time | 6.05 seconds |
| Started | Sep 18 07:58:57 PM UTC 24 |
| Finished | Sep 18 07:59:05 PM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141892654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.141892654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/46.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/46.keymgr_direct_to_disabled.3686243133 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 97854178 ps |
| CPU time | 2.39 seconds |
| Started | Sep 18 07:58:56 PM UTC 24 |
| Finished | Sep 18 07:59:00 PM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686243133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3686243133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/46.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/46.keymgr_hwsw_invalid_input.3910816886 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 66617118 ps |
| CPU time | 2.48 seconds |
| Started | Sep 18 07:58:57 PM UTC 24 |
| Finished | Sep 18 07:59:01 PM UTC 24 |
| Peak memory | 223420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910816886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3910816886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/46.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/46.keymgr_kmac_rsp_err.4167802913 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 166535487 ps |
| CPU time | 2.96 seconds |
| Started | Sep 18 07:58:57 PM UTC 24 |
| Finished | Sep 18 07:59:01 PM UTC 24 |
| Peak memory | 231608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167802913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.4167802913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/46.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/46.keymgr_lc_disable.3771131680 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 155753704 ps |
| CPU time | 3.78 seconds |
| Started | Sep 18 07:58:57 PM UTC 24 |
| Finished | Sep 18 07:59:02 PM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771131680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3771131680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/46.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/46.keymgr_random.872548050 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 78252126 ps |
| CPU time | 4.32 seconds |
| Started | Sep 18 07:58:55 PM UTC 24 |
| Finished | Sep 18 07:59:00 PM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872548050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.872548050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/46.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/46.keymgr_sideload.779806892 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 64457281 ps |
| CPU time | 4.51 seconds |
| Started | Sep 18 07:58:54 PM UTC 24 |
| Finished | Sep 18 07:58:59 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779806892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.779806892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/46.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_aes.3794928050 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 50712725 ps |
| CPU time | 2.34 seconds |
| Started | Sep 18 07:58:54 PM UTC 24 |
| Finished | Sep 18 07:58:57 PM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794928050 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3794928050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/46.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_kmac.4010695950 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 73857753 ps |
| CPU time | 2.63 seconds |
| Started | Sep 18 07:58:54 PM UTC 24 |
| Finished | Sep 18 07:58:57 PM UTC 24 |
| Peak memory | 217544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010695950 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.4010695950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/46.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_otbn.1204097000 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 39291507 ps |
| CPU time | 2.96 seconds |
| Started | Sep 18 07:58:55 PM UTC 24 |
| Finished | Sep 18 07:58:59 PM UTC 24 |
| Peak memory | 217352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204097000 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1204097000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/46.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_protect.2921517903 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 118617942 ps |
| CPU time | 4.39 seconds |
| Started | Sep 18 07:58:57 PM UTC 24 |
| Finished | Sep 18 07:59:03 PM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921517903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2921517903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/46.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/46.keymgr_smoke.1103647319 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 1253379282 ps |
| CPU time | 22.61 seconds |
| Started | Sep 18 07:58:54 PM UTC 24 |
| Finished | Sep 18 07:59:18 PM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103647319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1103647319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/46.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/46.keymgr_stress_all.3806637108 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 368702289 ps |
| CPU time | 4 seconds |
| Started | Sep 18 07:58:59 PM UTC 24 |
| Finished | Sep 18 07:59:04 PM UTC 24 |
| Peak memory | 229832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806637108 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3806637108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/46.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/46.keymgr_sw_invalid_input.3936546564 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 972766462 ps |
| CPU time | 6.41 seconds |
| Started | Sep 18 07:58:57 PM UTC 24 |
| Finished | Sep 18 07:59:05 PM UTC 24 |
| Peak memory | 215536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936546564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3936546564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/46.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/46.keymgr_sync_async_fault_cross.2223389040 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 1845718803 ps |
| CPU time | 9.68 seconds |
| Started | Sep 18 07:58:59 PM UTC 24 |
| Finished | Sep 18 07:59:09 PM UTC 24 |
| Peak memory | 219380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223389040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2223389040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/46.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/47.keymgr_alert_test.2984335264 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 44412986 ps |
| CPU time | 0.91 seconds |
| Started | Sep 18 07:59:08 PM UTC 24 |
| Finished | Sep 18 07:59:10 PM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984335264 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2984335264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/47.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/47.keymgr_cfg_regwen.3823537154 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 5069254799 ps |
| CPU time | 49.77 seconds |
| Started | Sep 18 07:59:00 PM UTC 24 |
| Finished | Sep 18 07:59:52 PM UTC 24 |
| Peak memory | 223528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823537154 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3823537154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/47.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/47.keymgr_custom_cm.206248051 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 3325282223 ps |
| CPU time | 19.74 seconds |
| Started | Sep 18 07:59:08 PM UTC 24 |
| Finished | Sep 18 07:59:29 PM UTC 24 |
| Peak memory | 231936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206248051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.206248051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/47.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/47.keymgr_direct_to_disabled.2251424650 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 158967864 ps |
| CPU time | 2.4 seconds |
| Started | Sep 18 07:59:00 PM UTC 24 |
| Finished | Sep 18 07:59:04 PM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251424650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2251424650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/47.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/47.keymgr_hwsw_invalid_input.709343876 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 124572141 ps |
| CPU time | 5.03 seconds |
| Started | Sep 18 07:59:01 PM UTC 24 |
| Finished | Sep 18 07:59:09 PM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709343876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.709343876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/47.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/47.keymgr_kmac_rsp_err.514803087 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 102086456 ps |
| CPU time | 2.05 seconds |
| Started | Sep 18 07:59:01 PM UTC 24 |
| Finished | Sep 18 07:59:06 PM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514803087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.514803087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/47.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/47.keymgr_lc_disable.287149627 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 183529823 ps |
| CPU time | 4.28 seconds |
| Started | Sep 18 07:59:00 PM UTC 24 |
| Finished | Sep 18 07:59:06 PM UTC 24 |
| Peak memory | 223592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287149627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.287149627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/47.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/47.keymgr_random.3594381922 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 1524356589 ps |
| CPU time | 27.19 seconds |
| Started | Sep 18 07:59:00 PM UTC 24 |
| Finished | Sep 18 07:59:29 PM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594381922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3594381922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/47.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/47.keymgr_sideload.1924859901 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 36013685 ps |
| CPU time | 3.55 seconds |
| Started | Sep 18 07:58:59 PM UTC 24 |
| Finished | Sep 18 07:59:03 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924859901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1924859901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/47.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_aes.820720257 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 60854692 ps |
| CPU time | 3.38 seconds |
| Started | Sep 18 07:59:00 PM UTC 24 |
| Finished | Sep 18 07:59:05 PM UTC 24 |
| Peak memory | 217512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820720257 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.820720257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/47.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_kmac.308873220 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 32667933 ps |
| CPU time | 2.59 seconds |
| Started | Sep 18 07:58:59 PM UTC 24 |
| Finished | Sep 18 07:59:02 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308873220 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.308873220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/47.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_otbn.1607735743 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 38641652 ps |
| CPU time | 2.89 seconds |
| Started | Sep 18 07:59:00 PM UTC 24 |
| Finished | Sep 18 07:59:04 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607735743 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1607735743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/47.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_protect.389343604 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 5154760479 ps |
| CPU time | 20.31 seconds |
| Started | Sep 18 07:59:08 PM UTC 24 |
| Finished | Sep 18 07:59:30 PM UTC 24 |
| Peak memory | 217452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389343604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.389343604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/47.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/47.keymgr_smoke.1635785503 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 249527733 ps |
| CPU time | 3.12 seconds |
| Started | Sep 18 07:58:59 PM UTC 24 |
| Finished | Sep 18 07:59:03 PM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635785503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1635785503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/47.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all.3927715486 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 980619873 ps |
| CPU time | 18.15 seconds |
| Started | Sep 18 07:59:08 PM UTC 24 |
| Finished | Sep 18 07:59:28 PM UTC 24 |
| Peak memory | 227564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927715486 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3927715486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/47.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/47.keymgr_sw_invalid_input.1526534515 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 68404474 ps |
| CPU time | 4 seconds |
| Started | Sep 18 07:59:01 PM UTC 24 |
| Finished | Sep 18 07:59:07 PM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526534515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1526534515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/47.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/47.keymgr_sync_async_fault_cross.2107423154 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 248948028 ps |
| CPU time | 1.84 seconds |
| Started | Sep 18 07:59:08 PM UTC 24 |
| Finished | Sep 18 07:59:11 PM UTC 24 |
| Peak memory | 216820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107423154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2107423154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/47.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/48.keymgr_alert_test.138923966 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 64022442 ps |
| CPU time | 1.17 seconds |
| Started | Sep 18 07:59:10 PM UTC 24 |
| Finished | Sep 18 07:59:12 PM UTC 24 |
| Peak memory | 212892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138923966 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.138923966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/48.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/48.keymgr_cfg_regwen.3035377814 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 163230427 ps |
| CPU time | 3.97 seconds |
| Started | Sep 18 07:59:10 PM UTC 24 |
| Finished | Sep 18 07:59:15 PM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035377814 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3035377814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/48.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/48.keymgr_custom_cm.2006690878 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 144464581 ps |
| CPU time | 7.15 seconds |
| Started | Sep 18 07:59:10 PM UTC 24 |
| Finished | Sep 18 07:59:18 PM UTC 24 |
| Peak memory | 217668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006690878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2006690878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/48.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/48.keymgr_direct_to_disabled.2004566551 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 47818295 ps |
| CPU time | 1.93 seconds |
| Started | Sep 18 07:59:10 PM UTC 24 |
| Finished | Sep 18 07:59:13 PM UTC 24 |
| Peak memory | 214868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004566551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2004566551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/48.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/48.keymgr_hwsw_invalid_input.3278748517 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 150607041 ps |
| CPU time | 3.76 seconds |
| Started | Sep 18 07:59:10 PM UTC 24 |
| Finished | Sep 18 07:59:15 PM UTC 24 |
| Peak memory | 225492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278748517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3278748517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/48.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/48.keymgr_kmac_rsp_err.317944411 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 52271068 ps |
| CPU time | 3.6 seconds |
| Started | Sep 18 07:59:10 PM UTC 24 |
| Finished | Sep 18 07:59:15 PM UTC 24 |
| Peak memory | 231744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317944411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.317944411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/48.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/48.keymgr_lc_disable.3711088836 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 272370421 ps |
| CPU time | 5.08 seconds |
| Started | Sep 18 07:59:10 PM UTC 24 |
| Finished | Sep 18 07:59:16 PM UTC 24 |
| Peak memory | 229620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711088836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3711088836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/48.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/48.keymgr_random.4231630994 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 556760790 ps |
| CPU time | 6.77 seconds |
| Started | Sep 18 07:59:10 PM UTC 24 |
| Finished | Sep 18 07:59:17 PM UTC 24 |
| Peak memory | 217484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231630994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.4231630994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/48.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/48.keymgr_sideload.4185431118 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 1271564657 ps |
| CPU time | 3.23 seconds |
| Started | Sep 18 07:59:09 PM UTC 24 |
| Finished | Sep 18 07:59:14 PM UTC 24 |
| Peak memory | 217472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185431118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.4185431118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/48.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_aes.2576002874 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 147313547 ps |
| CPU time | 2.53 seconds |
| Started | Sep 18 07:59:09 PM UTC 24 |
| Finished | Sep 18 07:59:13 PM UTC 24 |
| Peak memory | 217500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576002874 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2576002874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/48.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_kmac.3898151764 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 82974800 ps |
| CPU time | 3.04 seconds |
| Started | Sep 18 07:59:09 PM UTC 24 |
| Finished | Sep 18 07:59:14 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898151764 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3898151764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/48.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_otbn.1535318489 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 780839760 ps |
| CPU time | 7.1 seconds |
| Started | Sep 18 07:59:10 PM UTC 24 |
| Finished | Sep 18 07:59:18 PM UTC 24 |
| Peak memory | 217352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535318489 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1535318489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/48.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_protect.3334343725 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 60531428 ps |
| CPU time | 2.8 seconds |
| Started | Sep 18 07:59:10 PM UTC 24 |
| Finished | Sep 18 07:59:14 PM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334343725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3334343725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/48.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/48.keymgr_smoke.3472705170 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 111928225 ps |
| CPU time | 2.29 seconds |
| Started | Sep 18 07:59:08 PM UTC 24 |
| Finished | Sep 18 07:59:12 PM UTC 24 |
| Peak memory | 217192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472705170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3472705170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/48.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all.2246281971 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 4735114229 ps |
| CPU time | 45.03 seconds |
| Started | Sep 18 07:59:10 PM UTC 24 |
| Finished | Sep 18 07:59:57 PM UTC 24 |
| Peak memory | 231684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246281971 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2246281971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/48.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all_with_rand_reset.1488290992 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 1021756598 ps |
| CPU time | 20.75 seconds |
| Started | Sep 18 07:59:10 PM UTC 24 |
| Finished | Sep 18 07:59:32 PM UTC 24 |
| Peak memory | 229672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1488290992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymg r_stress_all_with_rand_reset.1488290992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/48.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/48.keymgr_sw_invalid_input.3981044915 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 76402665 ps |
| CPU time | 3.35 seconds |
| Started | Sep 18 07:59:10 PM UTC 24 |
| Finished | Sep 18 07:59:14 PM UTC 24 |
| Peak memory | 217544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981044915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3981044915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/48.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/48.keymgr_sync_async_fault_cross.1441450409 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 72917814 ps |
| CPU time | 2.29 seconds |
| Started | Sep 18 07:59:10 PM UTC 24 |
| Finished | Sep 18 07:59:13 PM UTC 24 |
| Peak memory | 217284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441450409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1441450409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/48.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/49.keymgr_alert_test.3186765432 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 18082793 ps |
| CPU time | 1.54 seconds |
| Started | Sep 18 07:59:16 PM UTC 24 |
| Finished | Sep 18 07:59:19 PM UTC 24 |
| Peak memory | 212832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186765432 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3186765432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/49.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/49.keymgr_cfg_regwen.1444585326 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 125979849 ps |
| CPU time | 3.57 seconds |
| Started | Sep 18 07:59:11 PM UTC 24 |
| Finished | Sep 18 07:59:16 PM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444585326 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1444585326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/49.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/49.keymgr_custom_cm.1269501375 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 73036006 ps |
| CPU time | 3.42 seconds |
| Started | Sep 18 07:59:15 PM UTC 24 |
| Finished | Sep 18 07:59:19 PM UTC 24 |
| Peak memory | 217596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269501375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1269501375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/49.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/49.keymgr_direct_to_disabled.3677951646 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 137915869 ps |
| CPU time | 2.69 seconds |
| Started | Sep 18 07:59:13 PM UTC 24 |
| Finished | Sep 18 07:59:16 PM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677951646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3677951646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/49.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/49.keymgr_hwsw_invalid_input.974176080 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 112308348 ps |
| CPU time | 3.85 seconds |
| Started | Sep 18 07:59:14 PM UTC 24 |
| Finished | Sep 18 07:59:19 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974176080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.974176080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/49.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/49.keymgr_kmac_rsp_err.1537932356 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 51217797 ps |
| CPU time | 2.79 seconds |
| Started | Sep 18 07:59:15 PM UTC 24 |
| Finished | Sep 18 07:59:19 PM UTC 24 |
| Peak memory | 219316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537932356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1537932356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/49.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/49.keymgr_lc_disable.2332504681 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 659397669 ps |
| CPU time | 6.82 seconds |
| Started | Sep 18 07:59:14 PM UTC 24 |
| Finished | Sep 18 07:59:22 PM UTC 24 |
| Peak memory | 223404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332504681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2332504681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/49.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/49.keymgr_random.1609754728 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 191430364 ps |
| CPU time | 3.96 seconds |
| Started | Sep 18 07:59:11 PM UTC 24 |
| Finished | Sep 18 07:59:17 PM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609754728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1609754728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/49.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/49.keymgr_sideload.4006954800 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 197829184 ps |
| CPU time | 4.07 seconds |
| Started | Sep 18 07:59:10 PM UTC 24 |
| Finished | Sep 18 07:59:15 PM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006954800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.4006954800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/49.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_aes.2734674549 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 60073182 ps |
| CPU time | 3.99 seconds |
| Started | Sep 18 07:59:11 PM UTC 24 |
| Finished | Sep 18 07:59:16 PM UTC 24 |
| Peak memory | 217320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734674549 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2734674549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/49.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_kmac.3293071531 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 272621754 ps |
| CPU time | 2.99 seconds |
| Started | Sep 18 07:59:11 PM UTC 24 |
| Finished | Sep 18 07:59:15 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293071531 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3293071531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/49.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_otbn.2531760716 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 88929015 ps |
| CPU time | 3.64 seconds |
| Started | Sep 18 07:59:11 PM UTC 24 |
| Finished | Sep 18 07:59:16 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531760716 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2531760716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/49.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_protect.294462635 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 123566496 ps |
| CPU time | 3.39 seconds |
| Started | Sep 18 07:59:15 PM UTC 24 |
| Finished | Sep 18 07:59:19 PM UTC 24 |
| Peak memory | 217392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294462635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.294462635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/49.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/49.keymgr_smoke.391091414 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 288748101 ps |
| CPU time | 7.55 seconds |
| Started | Sep 18 07:59:10 PM UTC 24 |
| Finished | Sep 18 07:59:19 PM UTC 24 |
| Peak memory | 217096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391091414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.391091414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/49.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all.509124490 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 1172981097 ps |
| CPU time | 43.21 seconds |
| Started | Sep 18 07:59:15 PM UTC 24 |
| Finished | Sep 18 08:00:00 PM UTC 24 |
| Peak memory | 225708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509124490 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.509124490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/49.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/49.keymgr_sw_invalid_input.1071673494 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 1147100364 ps |
| CPU time | 33.68 seconds |
| Started | Sep 18 07:59:14 PM UTC 24 |
| Finished | Sep 18 07:59:49 PM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071673494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1071673494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/49.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/49.keymgr_sync_async_fault_cross.2840605057 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 34517106 ps |
| CPU time | 2.29 seconds |
| Started | Sep 18 07:59:15 PM UTC 24 |
| Finished | Sep 18 07:59:18 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840605057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2840605057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/49.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/5.keymgr_alert_test.952804433 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 13789230 ps |
| CPU time | 1.12 seconds |
| Started | Sep 18 07:54:57 PM UTC 24 |
| Finished | Sep 18 07:55:00 PM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952804433 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.952804433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/5.keymgr_direct_to_disabled.4071799162 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 68541877 ps |
| CPU time | 3.63 seconds |
| Started | Sep 18 07:54:53 PM UTC 24 |
| Finished | Sep 18 07:54:58 PM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071799162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.4071799162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/5.keymgr_hwsw_invalid_input.4069171210 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 228956858 ps |
| CPU time | 4.44 seconds |
| Started | Sep 18 07:54:54 PM UTC 24 |
| Finished | Sep 18 07:55:00 PM UTC 24 |
| Peak memory | 223364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069171210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.4069171210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/5.keymgr_kmac_rsp_err.1283757110 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 60076067 ps |
| CPU time | 4.88 seconds |
| Started | Sep 18 07:54:54 PM UTC 24 |
| Finished | Sep 18 07:55:00 PM UTC 24 |
| Peak memory | 231312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283757110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1283757110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/5.keymgr_lc_disable.4242989075 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 307640584 ps |
| CPU time | 5.2 seconds |
| Started | Sep 18 07:54:53 PM UTC 24 |
| Finished | Sep 18 07:54:59 PM UTC 24 |
| Peak memory | 225512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242989075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.4242989075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/5.keymgr_random.2763850127 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 51454904 ps |
| CPU time | 3.2 seconds |
| Started | Sep 18 07:54:51 PM UTC 24 |
| Finished | Sep 18 07:54:56 PM UTC 24 |
| Peak memory | 215536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763850127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2763850127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/5.keymgr_sideload.55846055 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 1819806114 ps |
| CPU time | 6.38 seconds |
| Started | Sep 18 07:54:51 PM UTC 24 |
| Finished | Sep 18 07:54:59 PM UTC 24 |
| Peak memory | 217280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55846055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.55846055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_kmac.2731170044 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 129246730 ps |
| CPU time | 3.73 seconds |
| Started | Sep 18 07:54:51 PM UTC 24 |
| Finished | Sep 18 07:54:56 PM UTC 24 |
| Peak memory | 215484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731170044 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2731170044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_otbn.345715262 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 21048403 ps |
| CPU time | 2.41 seconds |
| Started | Sep 18 07:54:51 PM UTC 24 |
| Finished | Sep 18 07:54:55 PM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345715262 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.345715262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_protect.1620948133 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 681246686 ps |
| CPU time | 6.28 seconds |
| Started | Sep 18 07:54:55 PM UTC 24 |
| Finished | Sep 18 07:55:03 PM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620948133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1620948133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/5.keymgr_smoke.2891668926 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1797823020 ps |
| CPU time | 8.54 seconds |
| Started | Sep 18 07:54:50 PM UTC 24 |
| Finished | Sep 18 07:55:00 PM UTC 24 |
| Peak memory | 215292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891668926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2891668926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/5.keymgr_sw_invalid_input.1024923378 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 194383532 ps |
| CPU time | 7.08 seconds |
| Started | Sep 18 07:54:53 PM UTC 24 |
| Finished | Sep 18 07:55:01 PM UTC 24 |
| Peak memory | 217452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024923378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1024923378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/6.keymgr_alert_test.4251194908 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 42153210 ps |
| CPU time | 1.25 seconds |
| Started | Sep 18 07:55:04 PM UTC 24 |
| Finished | Sep 18 07:55:07 PM UTC 24 |
| Peak memory | 212892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251194908 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.4251194908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/6.keymgr_cfg_regwen.2098109724 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 534330932 ps |
| CPU time | 7.93 seconds |
| Started | Sep 18 07:55:01 PM UTC 24 |
| Finished | Sep 18 07:55:10 PM UTC 24 |
| Peak memory | 225708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098109724 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2098109724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/6.keymgr_direct_to_disabled.458860559 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 64989246 ps |
| CPU time | 4.29 seconds |
| Started | Sep 18 07:55:01 PM UTC 24 |
| Finished | Sep 18 07:55:06 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458860559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.458860559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/6.keymgr_hwsw_invalid_input.551428690 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 281881532 ps |
| CPU time | 3.57 seconds |
| Started | Sep 18 07:55:01 PM UTC 24 |
| Finished | Sep 18 07:55:06 PM UTC 24 |
| Peak memory | 223396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551428690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.551428690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/6.keymgr_kmac_rsp_err.2420400081 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 205921688 ps |
| CPU time | 3.88 seconds |
| Started | Sep 18 07:55:01 PM UTC 24 |
| Finished | Sep 18 07:55:06 PM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420400081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2420400081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/6.keymgr_lc_disable.3067830438 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 33629651 ps |
| CPU time | 2.47 seconds |
| Started | Sep 18 07:55:01 PM UTC 24 |
| Finished | Sep 18 07:55:04 PM UTC 24 |
| Peak memory | 213304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067830438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3067830438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/6.keymgr_random.3306810125 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 319149063 ps |
| CPU time | 4.1 seconds |
| Started | Sep 18 07:55:00 PM UTC 24 |
| Finished | Sep 18 07:55:05 PM UTC 24 |
| Peak memory | 223396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306810125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3306810125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/6.keymgr_sideload.4290882291 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 138318575 ps |
| CPU time | 4.85 seconds |
| Started | Sep 18 07:54:57 PM UTC 24 |
| Finished | Sep 18 07:55:03 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290882291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.4290882291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_aes.3661183992 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 3176337003 ps |
| CPU time | 27.25 seconds |
| Started | Sep 18 07:55:00 PM UTC 24 |
| Finished | Sep 18 07:55:28 PM UTC 24 |
| Peak memory | 217384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661183992 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3661183992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_kmac.2010985250 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 157922768 ps |
| CPU time | 6.66 seconds |
| Started | Sep 18 07:54:58 PM UTC 24 |
| Finished | Sep 18 07:55:06 PM UTC 24 |
| Peak memory | 217456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010985250 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2010985250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_otbn.3329460898 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 72349375 ps |
| CPU time | 3.34 seconds |
| Started | Sep 18 07:55:00 PM UTC 24 |
| Finished | Sep 18 07:55:04 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329460898 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3329460898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_protect.974401283 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 72323545 ps |
| CPU time | 2.53 seconds |
| Started | Sep 18 07:55:02 PM UTC 24 |
| Finished | Sep 18 07:55:06 PM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974401283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.974401283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/6.keymgr_smoke.2262511025 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 100054973 ps |
| CPU time | 1.98 seconds |
| Started | Sep 18 07:54:57 PM UTC 24 |
| Finished | Sep 18 07:55:00 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262511025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2262511025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/6.keymgr_sync_async_fault_cross.2509076597 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 65917222 ps |
| CPU time | 3.02 seconds |
| Started | Sep 18 07:55:02 PM UTC 24 |
| Finished | Sep 18 07:55:06 PM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509076597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2509076597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/6.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/7.keymgr_alert_test.1620725630 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 13955467 ps |
| CPU time | 1.08 seconds |
| Started | Sep 18 07:55:11 PM UTC 24 |
| Finished | Sep 18 07:55:13 PM UTC 24 |
| Peak memory | 212892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620725630 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1620725630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/7.keymgr_cfg_regwen.3056943560 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 715155257 ps |
| CPU time | 9.04 seconds |
| Started | Sep 18 07:55:07 PM UTC 24 |
| Finished | Sep 18 07:55:17 PM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056943560 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3056943560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/7.keymgr_custom_cm.3327675219 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 3484315188 ps |
| CPU time | 31.14 seconds |
| Started | Sep 18 07:55:08 PM UTC 24 |
| Finished | Sep 18 07:55:41 PM UTC 24 |
| Peak memory | 217736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327675219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3327675219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/7.keymgr_direct_to_disabled.91336530 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 45219294 ps |
| CPU time | 1.76 seconds |
| Started | Sep 18 07:55:07 PM UTC 24 |
| Finished | Sep 18 07:55:10 PM UTC 24 |
| Peak memory | 214816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91336530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.91336530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/7.keymgr_hwsw_invalid_input.293319919 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 98990815 ps |
| CPU time | 2.49 seconds |
| Started | Sep 18 07:55:07 PM UTC 24 |
| Finished | Sep 18 07:55:11 PM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293319919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.293319919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/7.keymgr_kmac_rsp_err.534605091 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 770153462 ps |
| CPU time | 3.9 seconds |
| Started | Sep 18 07:55:07 PM UTC 24 |
| Finished | Sep 18 07:55:12 PM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534605091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.534605091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/7.keymgr_lc_disable.3163862076 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 141545959 ps |
| CPU time | 4.29 seconds |
| Started | Sep 18 07:55:07 PM UTC 24 |
| Finished | Sep 18 07:55:12 PM UTC 24 |
| Peak memory | 227764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163862076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3163862076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/7.keymgr_random.2685710405 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 67241959 ps |
| CPU time | 4.59 seconds |
| Started | Sep 18 07:55:07 PM UTC 24 |
| Finished | Sep 18 07:55:13 PM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685710405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2685710405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/7.keymgr_sideload.698912912 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 40567272 ps |
| CPU time | 2.55 seconds |
| Started | Sep 18 07:55:06 PM UTC 24 |
| Finished | Sep 18 07:55:09 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698912912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.698912912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_aes.2298817303 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 89796289 ps |
| CPU time | 2.94 seconds |
| Started | Sep 18 07:55:06 PM UTC 24 |
| Finished | Sep 18 07:55:10 PM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298817303 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2298817303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_kmac.3879802402 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 719796927 ps |
| CPU time | 5.38 seconds |
| Started | Sep 18 07:55:06 PM UTC 24 |
| Finished | Sep 18 07:55:12 PM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879802402 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3879802402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_otbn.3859254274 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 241078568 ps |
| CPU time | 4.67 seconds |
| Started | Sep 18 07:55:07 PM UTC 24 |
| Finished | Sep 18 07:55:13 PM UTC 24 |
| Peak memory | 215508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859254274 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3859254274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/7.keymgr_smoke.4206071479 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 123392716 ps |
| CPU time | 4.59 seconds |
| Started | Sep 18 07:55:04 PM UTC 24 |
| Finished | Sep 18 07:55:10 PM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206071479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.4206071479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all.2418290129 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 94434031 ps |
| CPU time | 6.76 seconds |
| Started | Sep 18 07:55:10 PM UTC 24 |
| Finished | Sep 18 07:55:18 PM UTC 24 |
| Peak memory | 225708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418290129 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2418290129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all_with_rand_reset.1417951906 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1060928427 ps |
| CPU time | 9.54 seconds |
| Started | Sep 18 07:55:10 PM UTC 24 |
| Finished | Sep 18 07:55:21 PM UTC 24 |
| Peak memory | 229672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1417951906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr _stress_all_with_rand_reset.1417951906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/7.keymgr_sw_invalid_input.3938288775 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 697812984 ps |
| CPU time | 5.65 seconds |
| Started | Sep 18 07:55:07 PM UTC 24 |
| Finished | Sep 18 07:55:14 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938288775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3938288775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/7.keymgr_sync_async_fault_cross.2909573931 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 129329164 ps |
| CPU time | 2.77 seconds |
| Started | Sep 18 07:55:10 PM UTC 24 |
| Finished | Sep 18 07:55:14 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909573931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2909573931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/7.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/8.keymgr_alert_test.3241966993 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 99527901 ps |
| CPU time | 1.38 seconds |
| Started | Sep 18 07:55:19 PM UTC 24 |
| Finished | Sep 18 07:55:22 PM UTC 24 |
| Peak memory | 212892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241966993 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3241966993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/8.keymgr_cfg_regwen.372856106 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 118346869 ps |
| CPU time | 4.6 seconds |
| Started | Sep 18 07:55:13 PM UTC 24 |
| Finished | Sep 18 07:55:19 PM UTC 24 |
| Peak memory | 225656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372856106 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.372856106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/8.keymgr_custom_cm.220599978 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 268015401 ps |
| CPU time | 3.96 seconds |
| Started | Sep 18 07:55:18 PM UTC 24 |
| Finished | Sep 18 07:55:23 PM UTC 24 |
| Peak memory | 227980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220599978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.220599978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/8.keymgr_direct_to_disabled.1038704339 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 130536867 ps |
| CPU time | 2.7 seconds |
| Started | Sep 18 07:55:13 PM UTC 24 |
| Finished | Sep 18 07:55:17 PM UTC 24 |
| Peak memory | 223468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038704339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1038704339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/8.keymgr_kmac_rsp_err.1081389572 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 54501481 ps |
| CPU time | 2.99 seconds |
| Started | Sep 18 07:55:18 PM UTC 24 |
| Finished | Sep 18 07:55:22 PM UTC 24 |
| Peak memory | 223556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081389572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1081389572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/8.keymgr_lc_disable.3418169363 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 266452038 ps |
| CPU time | 5.32 seconds |
| Started | Sep 18 07:55:13 PM UTC 24 |
| Finished | Sep 18 07:55:19 PM UTC 24 |
| Peak memory | 215296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418169363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3418169363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/8.keymgr_random.3631824003 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 49009719 ps |
| CPU time | 3.88 seconds |
| Started | Sep 18 07:55:13 PM UTC 24 |
| Finished | Sep 18 07:55:18 PM UTC 24 |
| Peak memory | 227820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631824003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3631824003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/8.keymgr_sideload.888372390 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 322950845 ps |
| CPU time | 3.43 seconds |
| Started | Sep 18 07:55:12 PM UTC 24 |
| Finished | Sep 18 07:55:16 PM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888372390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.888372390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_aes.4075451109 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 80074619 ps |
| CPU time | 2.17 seconds |
| Started | Sep 18 07:55:13 PM UTC 24 |
| Finished | Sep 18 07:55:16 PM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075451109 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.4075451109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_kmac.1589941654 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 28859901 ps |
| CPU time | 3.21 seconds |
| Started | Sep 18 07:55:12 PM UTC 24 |
| Finished | Sep 18 07:55:16 PM UTC 24 |
| Peak memory | 217480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589941654 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1589941654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_otbn.3308567630 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 346105908 ps |
| CPU time | 5.03 seconds |
| Started | Sep 18 07:55:13 PM UTC 24 |
| Finished | Sep 18 07:55:19 PM UTC 24 |
| Peak memory | 217348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308567630 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3308567630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_protect.634994332 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 292980097 ps |
| CPU time | 3.23 seconds |
| Started | Sep 18 07:55:18 PM UTC 24 |
| Finished | Sep 18 07:55:22 PM UTC 24 |
| Peak memory | 225384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634994332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.634994332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/8.keymgr_smoke.3526603041 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 385148606 ps |
| CPU time | 4.87 seconds |
| Started | Sep 18 07:55:11 PM UTC 24 |
| Finished | Sep 18 07:55:17 PM UTC 24 |
| Peak memory | 217188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526603041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3526603041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/8.keymgr_sw_invalid_input.3201665447 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 211434194 ps |
| CPU time | 5.65 seconds |
| Started | Sep 18 07:55:18 PM UTC 24 |
| Finished | Sep 18 07:55:24 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201665447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3201665447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/8.keymgr_sync_async_fault_cross.3234273071 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 425607000 ps |
| CPU time | 3.23 seconds |
| Started | Sep 18 07:55:19 PM UTC 24 |
| Finished | Sep 18 07:55:23 PM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234273071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3234273071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/8.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/9.keymgr_alert_test.2735917827 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 14898015 ps |
| CPU time | 1.37 seconds |
| Started | Sep 18 07:55:24 PM UTC 24 |
| Finished | Sep 18 07:55:27 PM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735917827 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2735917827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/9.keymgr_cfg_regwen.4167793889 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 230015309 ps |
| CPU time | 4.4 seconds |
| Started | Sep 18 07:55:20 PM UTC 24 |
| Finished | Sep 18 07:55:25 PM UTC 24 |
| Peak memory | 223396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167793889 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.4167793889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/9.keymgr_custom_cm.1756907647 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 50773764 ps |
| CPU time | 2.13 seconds |
| Started | Sep 18 07:55:22 PM UTC 24 |
| Finished | Sep 18 07:55:25 PM UTC 24 |
| Peak memory | 230716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756907647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1756907647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/9.keymgr_direct_to_disabled.1167278373 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 120179101 ps |
| CPU time | 3.18 seconds |
| Started | Sep 18 07:55:20 PM UTC 24 |
| Finished | Sep 18 07:55:24 PM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167278373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1167278373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/9.keymgr_hwsw_invalid_input.822593 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 232437830 ps |
| CPU time | 2.52 seconds |
| Started | Sep 18 07:55:21 PM UTC 24 |
| Finished | Sep 18 07:55:24 PM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=ke ymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.822593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/9.keymgr_lc_disable.3932582401 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 127262714 ps |
| CPU time | 1.88 seconds |
| Started | Sep 18 07:55:20 PM UTC 24 |
| Finished | Sep 18 07:55:23 PM UTC 24 |
| Peak memory | 213488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932582401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3932582401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/9.keymgr_random.2598975975 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 340429238 ps |
| CPU time | 4.61 seconds |
| Started | Sep 18 07:55:19 PM UTC 24 |
| Finished | Sep 18 07:55:25 PM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598975975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2598975975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/9.keymgr_sideload.3961769538 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 251468517 ps |
| CPU time | 4.05 seconds |
| Started | Sep 18 07:55:19 PM UTC 24 |
| Finished | Sep 18 07:55:24 PM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961769538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3961769538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_aes.2273802062 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 146912768 ps |
| CPU time | 4.01 seconds |
| Started | Sep 18 07:55:19 PM UTC 24 |
| Finished | Sep 18 07:55:24 PM UTC 24 |
| Peak memory | 217408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273802062 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2273802062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_kmac.2217005287 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 217969547 ps |
| CPU time | 3.84 seconds |
| Started | Sep 18 07:55:19 PM UTC 24 |
| Finished | Sep 18 07:55:24 PM UTC 24 |
| Peak memory | 217460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217005287 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2217005287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_otbn.849161823 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 92413380 ps |
| CPU time | 2.7 seconds |
| Started | Sep 18 07:55:19 PM UTC 24 |
| Finished | Sep 18 07:55:23 PM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849161823 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.849161823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_protect.1126869901 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 295820997 ps |
| CPU time | 5.47 seconds |
| Started | Sep 18 07:55:23 PM UTC 24 |
| Finished | Sep 18 07:55:30 PM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126869901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1126869901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/9.keymgr_smoke.3598003584 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 55310150 ps |
| CPU time | 3.04 seconds |
| Started | Sep 18 07:55:19 PM UTC 24 |
| Finished | Sep 18 07:55:23 PM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598003584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3598003584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all.2266467042 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 2327211065 ps |
| CPU time | 59.12 seconds |
| Started | Sep 18 07:55:23 PM UTC 24 |
| Finished | Sep 18 07:56:24 PM UTC 24 |
| Peak memory | 231532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266467042 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2266467042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all_with_rand_reset.3161321336 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 423202042 ps |
| CPU time | 13.88 seconds |
| Started | Sep 18 07:55:24 PM UTC 24 |
| Finished | Sep 18 07:55:39 PM UTC 24 |
| Peak memory | 229984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3161321336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr _stress_all_with_rand_reset.3161321336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/9.keymgr_sw_invalid_input.2502526216 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 211314204 ps |
| CPU time | 6.71 seconds |
| Started | Sep 18 07:55:21 PM UTC 24 |
| Finished | Sep 18 07:55:29 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502526216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2502526216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/coverage/default/9.keymgr_sync_async_fault_cross.3561801654 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 136608973 ps |
| CPU time | 2.08 seconds |
| Started | Sep 18 07:55:23 PM UTC 24 |
| Finished | Sep 18 07:55:26 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561801654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3561801654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/9.keymgr_sync_async_fault_cross/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |