Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

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Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	14	35	71.43

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	13	22	62.86	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	41	1			T68	1		T118	1		T102	1
auto[OpGenId]	9	1			T188	1		T25	1		T189	1
auto[OpGenSwOut]	18	1			T13	1		T16	1		T36	1
auto[OpGenHwOut]	21	1			T5	2		T6	1		T29	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1677	1			T16	1		T8	90		T48	3
auto[StInit]	79	1			T48	1		T68	1		T26	1
auto[StCreatorRootKey]	41	1			T33	1		T36	1		T38	1
auto[StOwnerIntKey]	46	1			T18	1		T67	1		T49	1
auto[StOwnerKey]	43	1			T13	1		T37	1		T39	1
auto[StDisabled]	436	1			T48	1		T68	7		T117	1
auto[StInvalid]	49	1			T34	1		T61	1		T103	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3358

1

T1

1

T2

1

T3

1

auto[1]

89

1

T13

1

T16

1

T36

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1670	1			T8	90		T48	3		T9	90
auto[StReset]	auto[1]	7	1			T16	1		T127	1		T120	1
auto[StInit]	auto[0]	35	1			T48	1		T5	2		T51	1
auto[StInit]	auto[1]	44	1			T68	1		T26	1		T5	1
auto[StCreatorRootKey]	auto[0]	33	1			T33	1		T38	1		T125	1
auto[StCreatorRootKey]	auto[1]	8	1			T36	1		T53	1		T63	1
auto[StOwnerIntKey]	auto[0]	34	1			T18	1		T67	1		T49	1
auto[StOwnerIntKey]	auto[1]	12	1			T5	1		T118	1		T102	1
auto[StOwnerKey]	auto[0]	33	1			T37	1		T39	1		T126	1
auto[StOwnerKey]	auto[1]	10	1			T13	1		T128	1		T127	1
auto[StDisabled]	auto[0]	428	1			T48	1		T68	6		T117	1
auto[StDisabled]	auto[1]	8	1			T68	1		T6	1		T188	1
auto[StInvalid]	auto[0]	49	1			T34	1		T61	1		T103	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	13	22	62.86	13

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId]]	0	1	1
[auto[StReset]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey] , auto[StDisabled]]	[auto[OpDisable]]	--	--	5

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	6	1			T127	1		T120	1		T121	1
auto[StReset]	auto[OpGenSwOut]	1	1			T16	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	16	1			T68	1		T231	1		T188	2
auto[StInit]	auto[OpGenId]	4	1			T25	1		T232	1		T136	1
auto[StInit]	auto[OpGenSwOut]	9	1			T26	1		T207	1		T127	1
auto[StInit]	auto[OpGenHwOut]	15	1			T5	1		T29	1		T7	1
auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T53	1		T233	1		T234	1
auto[StCreatorRootKey]	auto[OpGenId]	1	1			T63	1		-	-		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	2	1			T36	1		T235	1		-	-
auto[StCreatorRootKey]	auto[OpGenHwOut]	1	1			T236	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T118	1		T102	1		T24	1
auto[StOwnerIntKey]	auto[OpGenId]	1	1			T189	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	1	1			T234	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	1	1			T5	1		-	-		-	-
auto[StOwnerKey]	auto[OpAdvance]	3	1			T128	1		T127	1		T237	1
auto[StOwnerKey]	auto[OpGenId]	1	1			T237	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	3	1			T13	1		T238	1		T239	1
auto[StOwnerKey]	auto[OpGenHwOut]	3	1			T240	1		T234	1		T241	1
auto[StDisabled]	auto[OpAdvance]	3	1			T167	1		T56	1		T242	1
auto[StDisabled]	auto[OpGenId]	2	1			T188	1		T172	1		-	-
auto[StDisabled]	auto[OpGenSwOut]	2	1			T68	1		T243	1		-	-
auto[StDisabled]	auto[OpGenHwOut]	1	1			T6	1		-	-		-	-