Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4604

1

T2

3

T3

3

T4

9

auto[1]

575

1

T12

3

T32

3

T46

7

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4604

1

T2

3

T3

3

T4

9

auto[1]

575

1

T12

3

T32

3

T46

7

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4666

1

T2

3

T3

3

T4

9

auto[1]

513

1

T12

3

T47

2

T58

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4666

1

T2

3

T3

3

T4

9

auto[1]

513

1

T12

3

T47

2

T58

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	398	1			T11	2		T14	1		T57	2
auto[OpGenId]	1064	1			T2	1		T11	2		T12	2
auto[OpGenSwOut]	1142	1			T2	2		T11	1		T12	2
auto[OpGenHwOut]	2501	1			T3	2		T4	9		T11	2
auto[OpDisable]	74	1			T3	1		T119	1		T68	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	398	1			T11	2		T14	1		T57	2
auto[OpGenId]	1064	1			T2	1		T11	2		T12	2
auto[OpGenSwOut]	1142	1			T2	2		T11	1		T12	2
auto[OpGenHwOut]	2501	1			T3	2		T4	9		T11	2
auto[OpDisable]	74	1			T3	1		T119	1		T68	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4648

1

T2

3

T3

3

T4

6

auto[1]

531

1

T4

3

T58

2

T219

3

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4648

1

T2

3

T3

3

T4

6

auto[1]

531

1

T4

3

T58

2

T219

3

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4907

1

T2

3

T3

3

T4

9

auto[1]

272

1

T11

5

T57

7

T66

4

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1756	1			T2	1		T3	1		T4	2
auto[1]	693	1			T4	1		T11	2		T12	1
auto[2]	693	1			T4	1		T14	1		T34	1
auto[3]	700	1			T12	3		T34	1		T32	1
auto[4]	320	1			T4	1		T14	1		T34	1
auto[5]	346	1			T2	1		T4	3		T11	3
auto[6]	352	1			T3	1		T14	1		T32	2
auto[7]	319	1			T2	1		T3	1		T4	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1337	1			T2	2		T3	2		T4	5
clear_one[1]	693	1			T4	1		T11	2		T12	1
clear_one[2]	693	1			T4	1		T14	1		T34	1
clear_one[3]	700	1			T12	3		T34	1		T32	1
clear_none	1756	1			T2	1		T3	1		T4	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	985	1			T4	1		T12	2		T14	1
auto[StInit]	626	1			T3	1		T4	1		T11	2
auto[StCreatorRootKey]	561	1			T4	1		T12	1		T13	1
auto[StOwnerIntKey]	508	1			T2	1		T4	1		T11	2
auto[StOwnerKey]	452	1			T4	1		T11	1		T12	1
auto[StDisabled]	1783	1			T2	2		T3	2		T4	4
auto[StInvalid]	264	1			T34	4		T35	7		T61	3

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	985	1			T4	1		T12	2		T14	1
auto[StInit]	626	1			T3	1		T4	1		T11	2
auto[StCreatorRootKey]	561	1			T4	1		T12	1		T13	1
auto[StOwnerIntKey]	508	1			T2	1		T4	1		T11	2
auto[StOwnerKey]	452	1			T4	1		T11	1		T12	1
auto[StDisabled]	1783	1			T2	2		T3	2		T4	4
auto[StInvalid]	264	1			T34	4		T35	7		T61	3

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[0]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[0]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[2]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[2]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[2]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[3]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[4] - auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[4] - auto[6]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[4] - auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[4] - auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StInit]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpGenId]	159	1			T105	1		T48	1		T45	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	163	1			T34	1		T48	1		T66	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	252	1			T4	1		T12	1		T14	1
auto[0]	auto[StInit]	auto[OpAdvance]	32	1			T67	1		T84	1		T244	1
auto[0]	auto[StInit]	auto[OpGenId]	75	1			T11	1		T17	1		T57	2
auto[0]	auto[StInit]	auto[OpGenSwOut]	92	1			T58	1		T219	1		T68	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	164	1			T3	1		T11	1		T47	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	18	1			T60	1		T210	1		T245	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	49	1			T15	1		T48	1		T68	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	50	1			T18	1		T218	1		T112	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	95	1			T4	1		T13	1		T46	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	14	1			T213	1		T5	1		T130	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	37	1			T68	1		T246	1		T51	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	34	1			T2	1		T119	1		T130	2
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	67	1			T47	1		T46	1		T92	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	13	1			T213	1		T84	1		T247	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	13	1			T102	1		T248	1		T127	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	20	1			T68	1		T244	1		T249	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	37	1			T250	1		T251	1		T141	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	14	1			T66	1		T84	1		T69	1
auto[0]	auto[StDisabled]	auto[OpGenId]	63	1			T213	1		T215	1		T68	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	55	1			T105	1		T216	1		T212	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	150	1			T32	1		T46	2		T223	1
auto[0]	auto[StDisabled]	auto[OpDisable]	18	1			T116	1		T52	1		T252	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	10	1			T103	1		T123	1		T206	1
auto[0]	auto[StInvalid]	auto[OpGenId]	19	1			T61	2		T103	1		T253	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	20	1			T35	1		T103	1		T88	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	23	1			T85	1		T104	2		T254	1
auto[1]	auto[StReset]	auto[OpAdvance]	3	1			T69	1		T255	1		T256	1
auto[1]	auto[StReset]	auto[OpGenId]	16	1			T12	1		T68	1		T129	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	9	1			T257	1		T258	1		T134	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	53	1			T34	1		T225	1		T259	1
auto[1]	auto[StInit]	auto[OpAdvance]	8	1			T102	1		T168	1		T63	1
auto[1]	auto[StInit]	auto[OpGenId]	12	1			T51	1		T69	1		T188	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	10	1			T14	1		T68	1		T5	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	16	1			T225	1		T260	1		T69	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T67	1		T261	1		T94	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T262	1		T263	1		T91	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T115	1		T130	1		T264	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	44	1			T265	1		T266	1		T84	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T267	1		T268	1		T269	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T219	1		T68	1		T102	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T215	1		T196	1		T30	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	28	1			T4	1		T265	1		T259	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T270	1		T271	1		T272	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	17	1			T48	1		T68	1		T6	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	26	1			T102	1		T196	1		T273	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	43	1			T226	1		T274	1		T275	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	33	1			T213	1		T245	1		T83	1
auto[1]	auto[StDisabled]	auto[OpGenId]	45	1			T83	1		T228	1		T276	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	58	1			T11	1		T58	1		T66	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	150	1			T11	1		T32	1		T47	1
auto[1]	auto[StDisabled]	auto[OpDisable]	13	1			T112	1		T113	1		T277	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	4	1			T86	1		T254	1		T278	1
auto[1]	auto[StInvalid]	auto[OpGenId]	8	1			T35	1		T278	1		T279	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	18	1			T42	2		T89	1		T124	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T34	1		T35	1		T280	1
auto[2]	auto[StReset]	auto[OpGenId]	23	1			T51	1		T143	1		T102	2
auto[2]	auto[StReset]	auto[OpGenSwOut]	15	1			T189	1		T190	2		T132	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	42	1			T32	1		T105	1		T45	1
auto[2]	auto[StInit]	auto[OpAdvance]	10	1			T127	1		T281	1		T98	1
auto[2]	auto[StInit]	auto[OpGenId]	8	1			T102	1		T282	1		T283	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	11	1			T218	1		T127	1		T284	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	34	1			T46	1		T223	1		T285	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T142	1		T286	1		T287	2
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T246	1		T233	1		T191	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T42	1		T5	1		T53	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	34	1			T211	1		T68	1		T285	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T40	1		T288	1		T287	3
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T14	1		T115	1		T130	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T245	1		T51	1		T289	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	44	1			T285	1		T290	1		T291	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T288	1		T287	1		T292	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	16	1			T127	1		T293	1		T264	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T69	1		T294	1		T188	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	26	1			T47	1		T219	1		T223	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	27	1			T141	1		T130	1		T72	1
auto[2]	auto[StDisabled]	auto[OpGenId]	57	1			T215	1		T68	1		T83	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	61	1			T105	1		T57	1		T219	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	153	1			T4	1		T32	1		T46	1
auto[2]	auto[StDisabled]	auto[OpDisable]	9	1			T198	1		T295	1		T296	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	8	1			T297	1		T298	1		T299	1
auto[2]	auto[StInvalid]	auto[OpGenId]	15	1			T85	1		T104	1		T123	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T88	1		T143	1		T300	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	15	1			T34	1		T42	1		T280	1
auto[3]	auto[StReset]	auto[OpAdvance]	1	1			T72	1		-	-		-	-
auto[3]	auto[StReset]	auto[OpGenId]	15	1			T48	1		T218	1		T102	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	20	1			T229	1		T21	1		T289	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	45	1			T34	1		T85	1		T259	1
auto[3]	auto[StInit]	auto[OpAdvance]	8	1			T57	2		T83	1		T194	1
auto[3]	auto[StInit]	auto[OpGenId]	8	1			T120	1		T136	1		T301	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	13	1			T51	1		T102	1		T72	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	20	1			T221	1		T275	1		T228	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T83	1		T302	1		T127	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	21	1			T57	1		T5	1		T303	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T66	2		T68	1		T129	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	30	1			T275	1		T290	1		T291	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T129	1		T27	1		T71	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T57	1		T140	1		T102	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T68	1		T283	1		T262	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	42	1			T221	1		T226	1		T230	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T304	1		T56	1		T189	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	6	1			T188	1		T305	1		T193	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	18	1			T12	1		T105	1		T102	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	59	1			T46	1		T221	1		T225	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	16	1			T294	1		T304	1		T306	1
auto[3]	auto[StDisabled]	auto[OpGenId]	63	1			T246	1		T220	2		T115	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	51	1			T12	1		T92	1		T307	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	149	1			T12	1		T32	1		T46	1
auto[3]	auto[StDisabled]	auto[OpDisable]	9	1			T68	1		T115	1		T264	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	11	1			T123	1		T206	1		T86	1
auto[3]	auto[StInvalid]	auto[OpGenId]	5	1			T35	1		T308	1		T309	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T253	1		T310	1		T299	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T85	1		T42	1		T310	1
auto[4]	auto[StReset]	auto[OpGenId]	11	1			T130	1		T86	1		T30	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	13	1			T264	1		T305	1		T193	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	20	1			T216	1		T229	1		T259	1
auto[4]	auto[StInit]	auto[OpAdvance]	4	1			T68	1		T187	1		T311	1
auto[4]	auto[StInit]	auto[OpGenId]	7	1			T312	1		T313	1		T314	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	10	1			T220	1		T130	1		T295	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	4	1			T315	1		T305	1		T238	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T66	1		T72	1		T305	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T102	1		T316	1		T317	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T114	1		T262	1		T318	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	14	1			T14	1		T319	1		T320	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T305	1		T189	1		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T66	1		T321	1		T194	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T72	1		T273	1		T190	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	25	1			T32	1		T223	1		T224	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T322	1		-	-		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	8	1			T57	1		T129	1		T323	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T324	1		T240	1		T325	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T4	1		T326	1		T327	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	12	1			T83	1		T130	1		T70	2
auto[4]	auto[StDisabled]	auto[OpGenId]	24	1			T213	1		T130	2		T328	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T5	1		T276	1		T102	2
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	67	1			T221	1		T68	2		T230	1
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T329	1		T330	1		T331	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	2	1			T332	1		T333	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	4	1			T279	1		T334	1		T335	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T299	1		T336	1		T337	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T34	1		T202	1		T298	1
auto[5]	auto[StReset]	auto[OpGenId]	7	1			T282	1		T279	1		T257	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	13	1			T48	1		T51	1		T102	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	28	1			T68	1		T259	1		T260	1
auto[5]	auto[StInit]	auto[OpAdvance]	4	1			T129	1		T87	1		T338	1
auto[5]	auto[StInit]	auto[OpGenId]	5	1			T188	1		T262	1		T339	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	7	1			T340	1		T130	2		T233	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	10	1			T4	1		T319	1		T130	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T220	1		T24	1		T341	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T12	1		T342	1		T135	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T102	1		T270	1		T343	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	15	1			T32	1		T221	1		T119	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T11	2		T51	1		T128	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T288	1		T344	1		T136	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T345	1		T346	1		T234	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T225	1		T260	1		T347	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T240	1		T348	1		T349	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	10	1			T11	1		T344	1		T350	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T235	1		-	-		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	15	1			T218	1		T259	1		T204	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	13	1			T14	1		T245	1		T289	1
auto[5]	auto[StDisabled]	auto[OpGenId]	19	1			T2	1		T209	1		T188	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T276	1		T196	1		T188	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	92	1			T4	2		T47	2		T221	2
auto[5]	auto[StDisabled]	auto[OpDisable]	7	1			T131	1		T132	1		T136	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	1	1			T351	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	4	1			T104	1		T336	2		T332	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T253	1		T254	1		T352	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T124	1		T353	1		-	-
auto[6]	auto[StReset]	auto[OpGenId]	10	1			T102	1		T354	1		T353	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	10	1			T51	1		T29	1		T355	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	17	1			T229	1		T266	1		T260	1
auto[6]	auto[StInit]	auto[OpAdvance]	1	1			T87	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenId]	9	1			T190	2		T306	1		T134	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	6	1			T263	1		T270	1		T356	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	15	1			T32	1		T204	1		T320	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T357	1		T358	1		T359	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T323	1		T167	1		T193	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T69	1		T263	1		T360	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T223	1		T230	1		T347	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T70	1		T325	1		T270	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T357	2		T192	1		T361	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T52	1		T362	1		T363	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T228	1		T277	1		T209	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T364	1		-	-		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	4	1			T68	1		T365	1		T366	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T66	1		T5	1		T316	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T32	1		T285	1		T367	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	12	1			T244	1		T70	3		T195	1
auto[6]	auto[StDisabled]	auto[OpGenId]	30	1			T228	1		T244	3		T102	2
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	40	1			T14	1		T246	1		T323	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	69	1			T3	1		T223	2		T226	3
auto[6]	auto[StDisabled]	auto[OpDisable]	6	1			T130	1		T240	1		T368	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T86	1		T298	1		T369	1
auto[6]	auto[StInvalid]	auto[OpGenId]	7	1			T61	1		T206	1		T370	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T35	1		T371	1		T372	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T280	1		T143	1		T254	1
auto[7]	auto[StReset]	auto[OpAdvance]	1	1			T373	1		-	-		-	-
auto[7]	auto[StReset]	auto[OpGenId]	14	1			T51	1		T127	2		T189	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	6	1			T5	1		T374	1		T167	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	19	1			T266	1		T375	1		T87	1
auto[7]	auto[StInit]	auto[OpGenId]	6	1			T365	1		T135	1		T376	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	5	1			T305	1		T91	1		T358	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	12	1			T259	1		T51	1		T138	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T68	1		T54	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T340	1		T240	1		T377	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T130	2		T189	1		T378	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T47	1		T379	1		T380	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T189	1		-	-		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T105	1		T381	1		T195	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T102	1		T264	1		T342	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T6	1		T188	1		T328	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T187	1		T382	1		T242	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	7	1			T130	1		T311	1		T286	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T216	1		T84	1		T136	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	15	1			T266	1		T197	1		T383	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	10	1			T22	1		T248	1		T127	1
auto[7]	auto[StDisabled]	auto[OpGenId]	17	1			T130	1		T317	1		T191	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T2	1		T218	1		T303	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	74	1			T4	1		T47	1		T225	1
auto[7]	auto[StDisabled]	auto[OpDisable]	6	1			T3	1		T119	1		T203	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	2	1			T297	1		T384	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	4	1			T34	1		T42	1		T253	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T35	1		T124	1		T334	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T35	1		T143	1		T279	1