Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

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Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1337

1

T2

2

T3

2

T4

5

clear_one[1]

auto[0]

auto[0]

auto[0]

420

1

T11

2

T12

1

T14

1

clear_one[1]

auto[0]

auto[0]

auto[1]

119

1

T4

1

T219

1

T225

2

clear_one[1]

auto[0]

auto[1]

auto[0]

116

1

T47

1

T223

1

T68

2

clear_one[1]

auto[0]

auto[1]

auto[1]

38

1

T58

1

T247

1

T288

1

clear_one[2]

auto[0]

auto[0]

auto[0]

414

1

T14

1

T34

1

T32

1

clear_one[2]

auto[0]

auto[0]

auto[1]

105

1

T4

1

T219

2

T230

1

clear_one[2]

auto[1]

auto[0]

auto[0]

129

1

T32

1

T46

1

T57

1

clear_one[2]

auto[1]

auto[0]

auto[1]

45

1

T58

1

T102

1

T187

1

clear_one[3]

auto[0]

auto[0]

auto[0]

397

1

T34

1

T105

1

T48

1

clear_one[3]

auto[0]

auto[1]

auto[0]

127

1

T274

2

T218

1

T259

3

clear_one[3]

auto[1]

auto[0]

auto[0]

136

1

T32

1

T46

2

T57

3

clear_one[3]

auto[1]

auto[1]

auto[0]

40

1

T12

3

T68

1

T92

1

clear_none

auto[0]

auto[0]

auto[0]

1252

1

T2

1

T3

1

T4

1

clear_none

auto[0]

auto[0]

auto[1]

133

1

T4

1

T225

1

T230

1

clear_none

auto[0]

auto[1]

auto[0]

114

1

T47

1

T223

1

T68

2

clear_none

auto[0]

auto[1]

auto[1]

32

1

T68

1

T188

1

T249

2

clear_none

auto[1]

auto[0]

auto[0]

144

1

T32

1

T46

4

T119

1

clear_none

auto[1]

auto[0]

auto[1]

35

1

T224

1

T41

1

T244

1

clear_none

auto[1]

auto[1]

auto[0]

22

1

T216

1

T102

1

T130

1

clear_none

auto[1]

auto[1]

auto[1]

24

1

T211

1

T117

1

T385

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1274	1			T2	2		T3	2		T4	5
clear_all	auto[1]	63	1			T11	2		T66	1		T83	1
clear_one[1]	auto[0]	646	1			T4	1		T12	1		T14	1
clear_one[1]	auto[1]	47	1			T11	2		T83	2		T69	3
clear_one[2]	auto[0]	646	1			T4	1		T14	1		T34	1
clear_one[2]	auto[1]	47	1			T57	1		T66	2		T83	1
clear_one[3]	auto[0]	645	1			T12	3		T34	1		T32	1
clear_one[3]	auto[1]	55	1			T57	4		T66	1		T83	1
clear_none	auto[0]	1696	1			T2	1		T3	1		T4	2
clear_none	auto[1]	60	1			T11	1		T57	2		T83	1