Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10859

1

T1

9

T2

6

T3

4

auto[Attestation]

7528

1

T1

3

T2

2

T3

12

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2739	1			T1	3		T2	1		T3	1
auto[Aes]	3279	1			T1	2		T2	1		T3	4
auto[Kmac]	3263	1			T1	1		T2	2		T3	4
auto[Otbn]	3353	1			T2	2		T3	3		T4	10

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7527	1			T1	8		T2	8		T3	4
auto[OpGenId]	5753	1			T1	6		T2	2		T3	4
auto[OpGenSwOut]	5833	1			T1	6		T2	4		T3	5
auto[OpGenHwOut]	6801	1			T2	2		T3	7		T4	10
auto[OpDisable]	126	1			T3	1		T45	1		T119	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10428

1

T1

8

T2

8

T3

15

auto[OpDoneFail]

15612

1

T1

12

T2

8

T3

6

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6288	1			T1	5		T2	1		T3	1
auto[StInit]	3553	1			T1	2		T2	2		T3	3
auto[StCreatorRootKey]	3105	1			T1	2		T2	2		T3	5
auto[StOwnerIntKey]	2804	1			T1	2		T2	2		T3	5
auto[StOwnerKey]	2384	1			T1	2		T2	2		T3	3
auto[StDisabled]	7906	1			T1	7		T2	7		T3	4

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	339	1			T1	2		T14	1		T34	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	99	1			T14	2		T17	1		T210	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	74	1			T1	1		T59	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	79	1			T59	1		T37	1		T211	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	67	1			T68	1		T212	1		T210	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	203	1			T2	1		T3	1		T11	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	334	1			T1	1		T33	1		T105	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	99	1			T17	1		T58	1		T68	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	64	1			T213	1		T38	1		T214	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	77	1			T215	1		T50	1		T84	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	67	1			T2	1		T11	1		T58	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	220	1			T11	1		T12	2		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	307	1			T13	2		T34	1		T105	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	96	1			T14	1		T45	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	97	1			T3	1		T58	1		T66	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	79	1			T2	1		T14	1		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	76	1			T12	1		T58	1		T216	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	214	1			T1	1		T3	1		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	324	1			T14	1		T45	2		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	95	1			T58	1		T18	1		T212	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	67	1			T14	1		T33	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	66	1			T60	1		T68	1		T83	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	49	1			T68	1		T210	1		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	213	1			T11	1		T12	1		T58	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	79	1			T68	4		T102	1		T130	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	97	1			T17	2		T45	1		T217	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	67	1			T33	1		T57	1		T37	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	67	1			T60	1		T83	1		T218	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	77	1			T13	1		T219	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	217	1			T11	1		T14	1		T105	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	78	1			T68	1		T5	2		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	96	1			T15	1		T17	1		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	81	1			T213	1		T129	1		T115	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	71	1			T57	1		T58	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	62	1			T1	1		T92	1		T218	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	212	1			T12	1		T105	1		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	70	1			T68	3		T51	3		T52	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	98	1			T219	1		T213	1		T211	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	77	1			T15	1		T68	2		T92	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	61	1			T3	1		T119	2		T218	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	45	1			T105	1		T57	1		T68	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	228	1			T105	1		T57	1		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	72	1			T48	1		T68	4		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	99	1			T33	1		T220	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	102	1			T2	1		T15	1		T18	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	86	1			T3	1		T12	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	65	1			T59	1		T219	1		T216	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	221	1			T12	2		T48	1		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	283	1			T13	1		T34	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	94	1			T45	1		T58	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	69	1			T13	1		T68	2		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	63	1			T14	1		T60	1		T220	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	56	1			T58	1		T219	1		T210	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	197	1			T11	1		T57	1		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	411	1			T34	1		T32	6		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	102	1			T17	3		T46	1		T57	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	117	1			T12	1		T219	1		T221	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	92	1			T32	1		T46	1		T221	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	92	1			T32	1		T46	1		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	286	1			T3	1		T11	1		T32	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	459	1			T12	1		T14	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	89	1			T2	1		T66	1		T119	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	92	1			T47	1		T68	1		T222	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	98	1			T223	1		T216	1		T224	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	95	1			T60	1		T219	1		T66	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	264	1			T47	3		T219	1		T223	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	445	1			T4	2		T12	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	118	1			T4	1		T13	1		T17	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	121	1			T14	1		T15	1		T92	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	106	1			T4	1		T219	1		T224	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	71	1			T60	2		T225	1		T226	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	267	1			T4	2		T12	1		T57	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	59	1			T68	4		T5	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	77	1			T18	1		T213	1		T117	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	75	1			T57	1		T119	1		T227	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	70	1			T57	1		T50	1		T228	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	43	1			T141	1		T102	1		T187	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	188	1			T12	2		T57	2		T216	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	53	1			T51	2		T102	3		T130	4
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	110	1			T11	2		T12	1		T32	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	100	1			T32	1		T105	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	102	1			T3	1		T119	1		T68	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	75	1			T3	1		T12	1		T60	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	278	1			T3	1		T11	1		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	58	1			T5	1		T51	2		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	105	1			T17	1		T47	1		T223	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	114	1			T15	1		T223	1		T229	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	97	1			T3	1		T12	2		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	67	1			T13	1		T47	1		T223	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	277	1			T47	1		T48	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	70	1			T48	1		T68	2		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	106	1			T3	1		T105	1		T66	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	127	1			T3	1		T4	1		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	93	1			T12	1		T225	1		T230	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	77	1			T4	1		T12	2		T68	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	293	1			T2	1		T4	2		T45	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	208	1			T1	1		T59	2		T37	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	653	1			T1	2		T2	1		T3	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	196	1			T2	1		T11	1		T58	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	665	1			T1	1		T11	1		T12	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	234	1			T2	1		T3	1		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	635	1			T1	1		T3	1		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	156	1			T33	1		T60	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	658	1			T11	1		T12	1		T14	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	200	1			T13	1		T33	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	404	1			T11	1		T14	1		T17	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	199	1			T1	1		T57	1		T58	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	401	1			T12	1		T15	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	166	1			T3	1		T15	1		T105	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	413	1			T105	1		T57	1		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	229	1			T2	1		T3	1		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	416	1			T12	2		T33	1		T48	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	171	1			T13	1		T14	1		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	591	1			T11	1		T13	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	279	1			T12	1		T32	2		T46	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	821	1			T3	1		T11	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	273	1			T47	1		T60	1		T219	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	824	1			T2	1		T12	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	288	1			T4	1		T14	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	840	1			T4	5		T12	2		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	176	1			T57	2		T119	1		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	336	1			T12	2		T57	2		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	265	1			T3	2		T12	1		T32	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	453	1			T3	1		T11	3		T12	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	267	1			T3	1		T12	2		T13	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	451	1			T17	1		T47	2		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	277	1			T3	1		T4	2		T12	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	489	1			T2	1		T3	1		T4	2