Unified Coverage Report :: Group Instance : attest_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31994

1

T1

24

T2

19

T3

25

auto[1]

280

1

T11

5

T57

6

T66

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32001	1			T1	24		T2	19		T3	25
auto[134217728:268435455]	8	1			T404	1		T405	1		T406	1
auto[268435456:402653183]	10	1			T11	2		T66	1		T407	1
auto[402653184:536870911]	16	1			T83	1		T84	1		T69	1
auto[536870912:671088639]	10	1			T57	1		T70	1		T407	1
auto[671088640:805306367]	4	1			T407	1		T408	1		T409	1
auto[805306368:939524095]	6	1			T57	1		T338	1		T410	1
auto[939524096:1073741823]	10	1			T244	1		T72	1		T357	1
auto[1073741824:1207959551]	4	1			T407	1		T411	1		T408	1
auto[1207959552:1342177279]	12	1			T83	1		T72	1		T338	1
auto[1342177280:1476395007]	6	1			T66	1		T70	1		T72	1
auto[1476395008:1610612735]	6	1			T244	1		T283	1		T412	1
auto[1610612736:1744830463]	10	1			T66	1		T288	1		T287	1
auto[1744830464:1879048191]	3	1			T83	1		T412	1		T256	1
auto[1879048192:2013265919]	13	1			T11	1		T72	1		T248	1
auto[2013265920:2147483647]	12	1			T70	1		T71	1		T72	1
auto[2147483648:2281701375]	10	1			T244	1		T70	1		T72	2
auto[2281701376:2415919103]	7	1			T84	1		T72	2		T357	1
auto[2415919104:2550136831]	17	1			T11	1		T70	1		T71	1
auto[2550136832:2684354559]	7	1			T248	2		T396	1		T406	2
auto[2684354560:2818572287]	11	1			T57	1		T72	1		T248	1
auto[2818572288:2952790015]	7	1			T70	1		T304	1		T406	1
auto[2952790016:3087007743]	15	1			T57	1		T66	1		T69	1
auto[3087007744:3221225471]	5	1			T57	1		T283	1		T413	2
auto[3221225472:3355443199]	9	1			T83	1		T84	1		T244	1
auto[3355443200:3489660927]	11	1			T57	1		T414	1		T406	1
auto[3489660928:3623878655]	4	1			T11	1		T288	1		T406	1
auto[3623878656:3758096383]	11	1			T70	1		T248	1		T405	1
auto[3758096384:3892314111]	6	1			T248	1		T287	1		T364	1
auto[3892314112:4026531839]	5	1			T405	1		T407	1		T287	1
auto[4026531840:4160749567]	12	1			T70	1		T72	1		T288	1
auto[4160749568:4294967295]	6	1			T70	1		T248	1		T304	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31994	1			T1	24		T2	19		T3	25
auto[0:134217727]	auto[1]	7	1			T66	1		T244	1		T72	1
auto[134217728:268435455]	auto[1]	8	1			T404	1		T405	1		T406	1
auto[268435456:402653183]	auto[1]	10	1			T11	2		T66	1		T407	1
auto[402653184:536870911]	auto[1]	16	1			T83	1		T84	1		T69	1
auto[536870912:671088639]	auto[1]	10	1			T57	1		T70	1		T407	1
auto[671088640:805306367]	auto[1]	4	1			T407	1		T408	1		T409	1
auto[805306368:939524095]	auto[1]	6	1			T57	1		T338	1		T410	1
auto[939524096:1073741823]	auto[1]	10	1			T244	1		T72	1		T357	1
auto[1073741824:1207959551]	auto[1]	4	1			T407	1		T411	1		T408	1
auto[1207959552:1342177279]	auto[1]	12	1			T83	1		T72	1		T338	1
auto[1342177280:1476395007]	auto[1]	6	1			T66	1		T70	1		T72	1
auto[1476395008:1610612735]	auto[1]	6	1			T244	1		T283	1		T412	1
auto[1610612736:1744830463]	auto[1]	10	1			T66	1		T288	1		T287	1
auto[1744830464:1879048191]	auto[1]	3	1			T83	1		T412	1		T256	1
auto[1879048192:2013265919]	auto[1]	13	1			T11	1		T72	1		T248	1
auto[2013265920:2147483647]	auto[1]	12	1			T70	1		T71	1		T72	1
auto[2147483648:2281701375]	auto[1]	10	1			T244	1		T70	1		T72	2
auto[2281701376:2415919103]	auto[1]	7	1			T84	1		T72	2		T357	1
auto[2415919104:2550136831]	auto[1]	17	1			T11	1		T70	1		T71	1
auto[2550136832:2684354559]	auto[1]	7	1			T248	2		T396	1		T406	2
auto[2684354560:2818572287]	auto[1]	11	1			T57	1		T72	1		T248	1
auto[2818572288:2952790015]	auto[1]	7	1			T70	1		T304	1		T406	1
auto[2952790016:3087007743]	auto[1]	15	1			T57	1		T66	1		T69	1
auto[3087007744:3221225471]	auto[1]	5	1			T57	1		T283	1		T413	2
auto[3221225472:3355443199]	auto[1]	9	1			T83	1		T84	1		T244	1
auto[3355443200:3489660927]	auto[1]	11	1			T57	1		T414	1		T406	1
auto[3489660928:3623878655]	auto[1]	4	1			T11	1		T288	1		T406	1
auto[3623878656:3758096383]	auto[1]	11	1			T70	1		T248	1		T405	1
auto[3758096384:3892314111]	auto[1]	6	1			T248	1		T287	1		T364	1
auto[3892314112:4026531839]	auto[1]	5	1			T405	1		T407	1		T287	1
auto[4026531840:4160749567]	auto[1]	12	1			T70	1		T72	1		T288	1
auto[4160749568:4294967295]	auto[1]	6	1			T70	1		T248	1		T304	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1456

1

T3

2

T14

1

T34

5

auto[1]

1779

1

T3

1

T11

4

T12

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T11	1		T34	1		T119	1
auto[134217728:268435455]	99	1			T11	1		T57	1		T117	1
auto[268435456:402653183]	108	1			T3	1		T13	1		T18	1
auto[402653184:536870911]	100	1			T13	1		T66	1		T68	1
auto[536870912:671088639]	106	1			T17	1		T48	1		T216	1
auto[671088640:805306367]	104	1			T3	1		T12	1		T13	1
auto[805306368:939524095]	92	1			T34	1		T219	1		T66	1
auto[939524096:1073741823]	114	1			T14	1		T17	1		T213	1
auto[1073741824:1207959551]	90	1			T17	1		T48	1		T57	1
auto[1207959552:1342177279]	93	1			T58	1		T216	1		T5	1
auto[1342177280:1476395007]	93	1			T57	1		T58	1		T66	1
auto[1476395008:1610612735]	102	1			T13	1		T14	1		T60	1
auto[1610612736:1744830463]	88	1			T58	1		T36	1		T68	2
auto[1744830464:1879048191]	93	1			T13	1		T14	1		T58	1
auto[1879048192:2013265919]	133	1			T34	1		T17	1		T58	1
auto[2013265920:2147483647]	73	1			T57	1		T61	1		T92	1
auto[2147483648:2281701375]	99	1			T14	1		T48	1		T219	1
auto[2281701376:2415919103]	102	1			T12	1		T16	1		T68	1
auto[2415919104:2550136831]	100	1			T3	1		T103	1		T42	1
auto[2550136832:2684354559]	110	1			T14	1		T48	1		T57	1
auto[2684354560:2818572287]	98	1			T12	1		T61	1		T103	2
auto[2818572288:2952790015]	101	1			T36	1		T220	1		T104	2
auto[2952790016:3087007743]	99	1			T11	1		T13	1		T216	1
auto[3087007744:3221225471]	108	1			T15	1		T35	1		T213	1
auto[3221225472:3355443199]	107	1			T17	1		T48	1		T67	1
auto[3355443200:3489660927]	104	1			T12	1		T34	1		T17	1
auto[3489660928:3623878655]	104	1			T12	1		T17	1		T45	1
auto[3623878656:3758096383]	108	1			T34	1		T36	1		T68	3
auto[3758096384:3892314111]	102	1			T13	1		T58	1		T66	1
auto[3892314112:4026531839]	101	1			T57	1		T36	1		T245	1
auto[4026531840:4160749567]	111	1			T34	1		T57	1		T211	1
auto[4160749568:4294967295]	92	1			T11	1		T12	1		T35	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	40	1			T34	1		T42	1		T88	1
auto[0:134217727]	auto[1]	61	1			T11	1		T119	1		T83	1
auto[134217728:268435455]	auto[0]	38	1			T52	1		T143	1		T130	1
auto[134217728:268435455]	auto[1]	61	1			T11	1		T57	1		T117	1
auto[268435456:402653183]	auto[0]	40	1			T3	1		T213	1		T218	1
auto[268435456:402653183]	auto[1]	68	1			T13	1		T18	1		T51	1
auto[402653184:536870911]	auto[0]	39	1			T220	1		T229	1		T21	1
auto[402653184:536870911]	auto[1]	61	1			T13	1		T66	1		T68	1
auto[536870912:671088639]	auto[0]	53	1			T17	1		T48	1		T216	1
auto[536870912:671088639]	auto[1]	53	1			T129	1		T6	1		T244	1
auto[671088640:805306367]	auto[0]	42	1			T45	1		T35	1		T5	1
auto[671088640:805306367]	auto[1]	62	1			T3	1		T12	1		T13	1
auto[805306368:939524095]	auto[0]	42	1			T219	1		T129	1		T123	1
auto[805306368:939524095]	auto[1]	50	1			T34	1		T66	1		T84	1
auto[939524096:1073741823]	auto[0]	58	1			T67	1		T68	1		T117	1
auto[939524096:1073741823]	auto[1]	56	1			T14	1		T17	1		T213	1
auto[1073741824:1207959551]	auto[0]	30	1			T17	1		T52	1		T142	1
auto[1073741824:1207959551]	auto[1]	60	1			T48	1		T57	1		T68	1
auto[1207959552:1342177279]	auto[0]	40	1			T58	1		T216	1		T228	1
auto[1207959552:1342177279]	auto[1]	53	1			T5	1		T244	1		T113	1
auto[1342177280:1476395007]	auto[0]	44	1			T57	1		T66	1		T68	1
auto[1342177280:1476395007]	auto[1]	49	1			T58	1		T117	1		T340	1
auto[1476395008:1610612735]	auto[0]	47	1			T68	1		T280	1		T102	2
auto[1476395008:1610612735]	auto[1]	55	1			T13	1		T14	1		T60	1
auto[1610612736:1744830463]	auto[0]	39	1			T58	1		T36	1		T68	1
auto[1610612736:1744830463]	auto[1]	49	1			T68	1		T92	1		T83	1
auto[1744830464:1879048191]	auto[0]	43	1			T36	1		T68	1		T85	1
auto[1744830464:1879048191]	auto[1]	50	1			T13	1		T14	1		T58	1
auto[1879048192:2013265919]	auto[0]	57	1			T34	1		T17	1		T68	1
auto[1879048192:2013265919]	auto[1]	76	1			T58	1		T60	1		T211	1
auto[2013265920:2147483647]	auto[0]	42	1			T61	1		T289	1		T143	1
auto[2013265920:2147483647]	auto[1]	31	1			T57	1		T92	1		T294	1
auto[2147483648:2281701375]	auto[0]	36	1			T219	1		T213	2		T119	2
auto[2147483648:2281701375]	auto[1]	63	1			T14	1		T48	1		T218	1
auto[2281701376:2415919103]	auto[0]	48	1			T5	2		T104	1		T253	1
auto[2281701376:2415919103]	auto[1]	54	1			T12	1		T16	1		T68	1
auto[2415919104:2550136831]	auto[0]	54	1			T3	1		T103	1		T129	1
auto[2415919104:2550136831]	auto[1]	46	1			T42	1		T228	1		T102	1
auto[2550136832:2684354559]	auto[0]	50	1			T14	1		T36	1		T85	1
auto[2550136832:2684354559]	auto[1]	60	1			T48	1		T57	1		T68	1
auto[2684354560:2818572287]	auto[0]	41	1			T61	1		T88	1		T5	1
auto[2684354560:2818572287]	auto[1]	57	1			T12	1		T103	2		T92	1
auto[2818572288:2952790015]	auto[0]	47	1			T36	1		T104	2		T6	1
auto[2818572288:2952790015]	auto[1]	54	1			T220	1		T102	1		T130	1
auto[2952790016:3087007743]	auto[0]	42	1			T218	1		T289	1		T140	1
auto[2952790016:3087007743]	auto[1]	57	1			T11	1		T13	1		T216	1
auto[3087007744:3221225471]	auto[0]	49	1			T35	1		T213	1		T103	1
auto[3087007744:3221225471]	auto[1]	59	1			T15	1		T216	2		T88	1
auto[3221225472:3355443199]	auto[0]	51	1			T17	1		T85	1		T245	1
auto[3221225472:3355443199]	auto[1]	56	1			T48	1		T67	1		T52	1
auto[3355443200:3489660927]	auto[0]	47	1			T34	1		T17	1		T61	1
auto[3355443200:3489660927]	auto[1]	57	1			T12	1		T66	1		T253	1
auto[3489660928:3623878655]	auto[0]	54	1			T17	1		T67	1		T51	1
auto[3489660928:3623878655]	auto[1]	50	1			T12	1		T45	1		T57	1
auto[3623878656:3758096383]	auto[0]	55	1			T34	1		T36	1		T68	3
auto[3623878656:3758096383]	auto[1]	53	1			T220	1		T244	1		T118	1
auto[3758096384:3892314111]	auto[0]	42	1			T39	1		T88	1		T52	1
auto[3758096384:3892314111]	auto[1]	60	1			T13	1		T58	1		T66	1
auto[3892314112:4026531839]	auto[0]	47	1			T57	1		T36	1		T245	1
auto[3892314112:4026531839]	auto[1]	54	1			T51	2		T102	1		T130	1
auto[4026531840:4160749567]	auto[0]	52	1			T34	1		T104	1		T140	1
auto[4026531840:4160749567]	auto[1]	59	1			T57	1		T211	1		T218	1
auto[4160749568:4294967295]	auto[0]	47	1			T5	2		T228	1		T253	1
auto[4160749568:4294967295]	auto[1]	45	1			T11	1		T12	1		T35	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1474

1

T3

2

T11

1

T12

1

auto[1]

1762

1

T3

1

T11

3

T12

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	90	1			T17	1		T57	1		T216	1
auto[134217728:268435455]	112	1			T14	1		T57	2		T220	1
auto[268435456:402653183]	85	1			T61	1		T219	2		T66	1
auto[402653184:536870911]	116	1			T17	1		T36	1		T83	1
auto[536870912:671088639]	98	1			T36	2		T67	1		T68	1
auto[671088640:805306367]	121	1			T13	2		T68	2		T228	1
auto[805306368:939524095]	93	1			T13	1		T36	1		T117	1
auto[939524096:1073741823]	87	1			T12	1		T34	1		T92	1
auto[1073741824:1207959551]	96	1			T45	1		T61	1		T213	1
auto[1207959552:1342177279]	97	1			T11	1		T66	1		T67	1
auto[1342177280:1476395007]	117	1			T12	1		T34	1		T57	1
auto[1476395008:1610612735]	93	1			T48	1		T66	1		T103	1
auto[1610612736:1744830463]	109	1			T16	1		T34	1		T48	1
auto[1744830464:1879048191]	92	1			T3	1		T36	1		T35	1
auto[1879048192:2013265919]	101	1			T17	1		T58	2		T35	1
auto[2013265920:2147483647]	119	1			T11	1		T14	1		T57	1
auto[2147483648:2281701375]	113	1			T48	1		T67	1		T210	1
auto[2281701376:2415919103]	116	1			T14	1		T57	1		T213	1
auto[2415919104:2550136831]	102	1			T45	1		T58	1		T60	1
auto[2550136832:2684354559]	100	1			T12	1		T13	2		T68	1
auto[2684354560:2818572287]	104	1			T17	1		T18	1		T67	1
auto[2818572288:2952790015]	101	1			T11	1		T12	1		T129	1
auto[2952790016:3087007743]	86	1			T11	1		T34	1		T58	1
auto[3087007744:3221225471]	104	1			T34	1		T216	1		T66	1
auto[3221225472:3355443199]	86	1			T68	1		T39	1		T129	1
auto[3355443200:3489660927]	92	1			T12	1		T14	1		T57	1
auto[3489660928:3623878655]	105	1			T13	1		T15	1		T17	1
auto[3623878656:3758096383]	107	1			T68	2		T5	2		T229	1
auto[3758096384:3892314111]	105	1			T3	1		T14	1		T17	1
auto[3892314112:4026531839]	85	1			T3	1		T13	1		T34	1
auto[4026531840:4160749567]	98	1			T216	1		T211	1		T68	1
auto[4160749568:4294967295]	106	1			T12	1		T48	1		T58	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T17	1		T68	1		T42	1
auto[0:134217727]	auto[1]	43	1			T57	1		T216	1		T67	1
auto[134217728:268435455]	auto[0]	48	1			T57	2		T229	1		T104	1
auto[134217728:268435455]	auto[1]	64	1			T14	1		T220	1		T84	1
auto[268435456:402653183]	auto[0]	42	1			T61	1		T219	1		T119	1
auto[268435456:402653183]	auto[1]	43	1			T219	1		T66	1		T130	1
auto[402653184:536870911]	auto[0]	50	1			T17	1		T36	1		T228	1
auto[402653184:536870911]	auto[1]	66	1			T83	1		T129	1		T218	1
auto[536870912:671088639]	auto[0]	40	1			T36	2		T67	1		T68	1
auto[536870912:671088639]	auto[1]	58	1			T218	1		T102	1		T130	3
auto[671088640:805306367]	auto[0]	51	1			T68	1		T21	1		T118	1
auto[671088640:805306367]	auto[1]	70	1			T13	2		T68	1		T228	1
auto[805306368:939524095]	auto[0]	39	1			T36	1		T88	1		T141	1
auto[805306368:939524095]	auto[1]	54	1			T13	1		T117	1		T112	1
auto[939524096:1073741823]	auto[0]	40	1			T34	1		T141	1		T130	1
auto[939524096:1073741823]	auto[1]	47	1			T12	1		T92	1		T39	1
auto[1073741824:1207959551]	auto[0]	52	1			T45	1		T61	1		T213	1
auto[1073741824:1207959551]	auto[1]	44	1			T114	1		T220	1		T52	1
auto[1207959552:1342177279]	auto[0]	45	1			T11	1		T66	1		T67	1
auto[1207959552:1342177279]	auto[1]	52	1			T68	1		T303	1		T276	1
auto[1342177280:1476395007]	auto[0]	61	1			T34	1		T88	1		T229	1
auto[1342177280:1476395007]	auto[1]	56	1			T12	1		T57	1		T85	1
auto[1476395008:1610612735]	auto[0]	42	1			T48	1		T68	1		T289	2
auto[1476395008:1610612735]	auto[1]	51	1			T66	1		T103	1		T68	1
auto[1610612736:1744830463]	auto[0]	45	1			T34	1		T83	1		T129	1
auto[1610612736:1744830463]	auto[1]	64	1			T16	1		T48	1		T58	1
auto[1744830464:1879048191]	auto[0]	51	1			T3	1		T36	1		T35	1
auto[1744830464:1879048191]	auto[1]	41	1			T52	1		T22	1		T130	1
auto[1879048192:2013265919]	auto[0]	50	1			T17	1		T35	1		T84	1
auto[1879048192:2013265919]	auto[1]	51	1			T58	2		T115	1		T21	1
auto[2013265920:2147483647]	auto[0]	62	1			T57	1		T103	1		T52	1
auto[2013265920:2147483647]	auto[1]	57	1			T11	1		T14	1		T68	1
auto[2147483648:2281701375]	auto[0]	59	1			T67	1		T6	1		T253	1
auto[2147483648:2281701375]	auto[1]	54	1			T48	1		T210	1		T52	1
auto[2281701376:2415919103]	auto[0]	47	1			T213	1		T218	1		T5	1
auto[2281701376:2415919103]	auto[1]	69	1			T14	1		T57	1		T202	1
auto[2415919104:2550136831]	auto[0]	45	1			T85	1		T84	1		T52	2
auto[2415919104:2550136831]	auto[1]	57	1			T45	1		T58	1		T60	1
auto[2550136832:2684354559]	auto[0]	49	1			T68	1		T129	1		T5	1
auto[2550136832:2684354559]	auto[1]	51	1			T12	1		T13	2		T92	1
auto[2684354560:2818572287]	auto[0]	38	1			T17	1		T68	1		T92	1
auto[2684354560:2818572287]	auto[1]	66	1			T18	1		T67	1		T117	1
auto[2818572288:2952790015]	auto[0]	50	1			T52	2		T140	1		T102	1
auto[2818572288:2952790015]	auto[1]	51	1			T11	1		T12	1		T129	1
auto[2952790016:3087007743]	auto[0]	36	1			T34	1		T58	1		T85	1
auto[2952790016:3087007743]	auto[1]	50	1			T11	1		T60	1		T216	2
auto[3087007744:3221225471]	auto[0]	45	1			T216	1		T68	1		T280	1
auto[3087007744:3221225471]	auto[1]	59	1			T34	1		T66	1		T119	1
auto[3221225472:3355443199]	auto[0]	33	1			T5	1		T6	1		T21	1
auto[3221225472:3355443199]	auto[1]	53	1			T68	1		T39	1		T129	1
auto[3355443200:3489660927]	auto[0]	44	1			T14	1		T36	1		T40	1
auto[3355443200:3489660927]	auto[1]	48	1			T12	1		T57	1		T66	1
auto[3489660928:3623878655]	auto[0]	45	1			T17	1		T213	1		T68	1
auto[3489660928:3623878655]	auto[1]	60	1			T13	1		T15	1		T39	1
auto[3623878656:3758096383]	auto[0]	56	1			T5	1		T229	1		T51	1
auto[3623878656:3758096383]	auto[1]	51	1			T68	2		T5	1		T141	1
auto[3758096384:3892314111]	auto[0]	46	1			T3	1		T17	1		T253	1
auto[3758096384:3892314111]	auto[1]	59	1			T14	1		T213	1		T42	1
auto[3892314112:4026531839]	auto[0]	34	1			T34	1		T17	1		T48	1
auto[3892314112:4026531839]	auto[1]	51	1			T3	1		T13	1		T57	1
auto[4026531840:4160749567]	auto[0]	38	1			T85	1		T42	1		T129	1
auto[4026531840:4160749567]	auto[1]	60	1			T216	1		T211	1		T68	1
auto[4160749568:4294967295]	auto[0]	44	1			T12	1		T58	1		T213	1
auto[4160749568:4294967295]	auto[1]	62	1			T48	1		T42	1		T83	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1448

1

T3

2

T13

1

T14

1

auto[1]

1787

1

T3

1

T11

4

T12

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	91	1			T88	1		T218	1		T104	1
auto[134217728:268435455]	124	1			T48	1		T36	1		T213	1
auto[268435456:402653183]	88	1			T66	1		T5	2		T229	1
auto[402653184:536870911]	97	1			T13	1		T57	1		T35	1
auto[536870912:671088639]	92	1			T13	1		T17	2		T45	1
auto[671088640:805306367]	116	1			T13	1		T57	1		T103	1
auto[805306368:939524095]	101	1			T11	1		T58	2		T68	1
auto[939524096:1073741823]	124	1			T13	1		T14	1		T66	2
auto[1073741824:1207959551]	98	1			T3	2		T45	1		T58	1
auto[1207959552:1342177279]	107	1			T13	1		T36	1		T68	1
auto[1342177280:1476395007]	103	1			T14	2		T119	1		T41	1
auto[1476395008:1610612735]	100	1			T17	1		T57	1		T216	1
auto[1610612736:1744830463]	99	1			T35	1		T61	1		T66	2
auto[1744830464:1879048191]	97	1			T16	1		T34	1		T211	1
auto[1879048192:2013265919]	107	1			T12	1		T36	1		T68	1
auto[2013265920:2147483647]	90	1			T11	1		T60	1		T210	1
auto[2147483648:2281701375]	106	1			T11	1		T13	1		T48	2
auto[2281701376:2415919103]	103	1			T216	1		T119	1		T68	1
auto[2415919104:2550136831]	93	1			T15	1		T68	1		T114	1
auto[2550136832:2684354559]	83	1			T12	1		T57	2		T36	1
auto[2684354560:2818572287]	86	1			T17	1		T219	1		T85	1
auto[2818572288:2952790015]	102	1			T12	1		T13	1		T17	1
auto[2952790016:3087007743]	115	1			T11	1		T12	1		T36	1
auto[3087007744:3221225471]	93	1			T34	1		T17	1		T48	1
auto[3221225472:3355443199]	120	1			T68	1		T88	1		T6	3
auto[3355443200:3489660927]	99	1			T34	1		T48	1		T57	1
auto[3489660928:3623878655]	101	1			T12	1		T61	1		T68	1
auto[3623878656:3758096383]	98	1			T14	1		T34	1		T18	1
auto[3758096384:3892314111]	96	1			T34	1		T57	1		T58	1
auto[3892314112:4026531839]	108	1			T3	1		T12	1		T17	1
auto[4026531840:4160749567]	103	1			T36	1		T219	1		T245	1
auto[4160749568:4294967295]	95	1			T14	1		T34	1		T35	1