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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2847 1 T3 3 T11 4 T12 6
auto[1] 270 1 T11 8 T57 6 T66 5


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 102 1 T11 1 T34 1 T17 1
auto[134217728:268435455] 99 1 T11 1 T68 1 T218 1
auto[268435456:402653183] 98 1 T103 1 T85 1 T129 1
auto[402653184:536870911] 95 1 T11 1 T14 1 T34 1
auto[536870912:671088639] 105 1 T12 1 T66 1 T68 1
auto[671088640:805306367] 84 1 T61 1 T68 2 T84 2
auto[805306368:939524095] 99 1 T14 1 T17 1 T48 1
auto[939524096:1073741823] 106 1 T57 1 T58 2 T66 2
auto[1073741824:1207959551] 109 1 T3 1 T11 1 T12 2
auto[1207959552:1342177279] 92 1 T36 1 T88 1 T220 1
auto[1342177280:1476395007] 81 1 T140 1 T102 1 T89 1
auto[1476395008:1610612735] 111 1 T11 1 T12 1 T34 1
auto[1610612736:1744830463] 95 1 T13 1 T14 1 T16 1
auto[1744830464:1879048191] 94 1 T11 1 T58 1 T213 1
auto[1879048192:2013265919] 104 1 T12 1 T15 1 T57 1
auto[2013265920:2147483647] 102 1 T57 1 T66 1 T117 1
auto[2147483648:2281701375] 86 1 T13 1 T14 1 T48 1
auto[2281701376:2415919103] 104 1 T3 1 T13 1 T57 2
auto[2415919104:2550136831] 104 1 T14 1 T35 1 T60 1
auto[2550136832:2684354559] 87 1 T34 2 T57 1 T216 1
auto[2684354560:2818572287] 108 1 T11 1 T17 1 T57 1
auto[2818572288:2952790015] 96 1 T119 1 T103 1 T85 2
auto[2952790016:3087007743] 87 1 T17 1 T211 1 T52 1
auto[3087007744:3221225471] 101 1 T58 1 T66 1 T211 1
auto[3221225472:3355443199] 98 1 T11 1 T17 1 T58 1
auto[3355443200:3489660927] 109 1 T60 1 T61 1 T219 1
auto[3489660928:3623878655] 113 1 T18 1 T117 1 T83 2
auto[3623878656:3758096383] 90 1 T12 1 T216 1 T66 1
auto[3758096384:3892314111] 100 1 T11 2 T34 1 T216 1
auto[3892314112:4026531839] 89 1 T45 2 T57 1 T58 1
auto[4026531840:4160749567] 81 1 T114 1 T117 1 T253 1
auto[4160749568:4294967295] 88 1 T3 1 T11 2 T220 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 90 1 T34 1 T17 1 T35 1
auto[0:134217727] auto[1] 12 1 T11 1 T69 1 T248 1
auto[134217728:268435455] auto[0] 95 1 T68 1 T218 1 T303 1
auto[134217728:268435455] auto[1] 4 1 T11 1 T255 1 T348 1
auto[268435456:402653183] auto[0] 96 1 T103 1 T85 1 T129 1
auto[268435456:402653183] auto[1] 2 1 T406 1 T419 1 - -
auto[402653184:536870911] auto[0] 86 1 T14 1 T34 1 T17 2
auto[402653184:536870911] auto[1] 9 1 T11 1 T412 1 T404 1
auto[536870912:671088639] auto[0] 97 1 T12 1 T66 1 T68 1
auto[536870912:671088639] auto[1] 8 1 T244 1 T248 1 T412 1
auto[671088640:805306367] auto[0] 81 1 T61 1 T68 2 T84 2
auto[671088640:805306367] auto[1] 3 1 T287 1 T411 1 T426 1
auto[805306368:939524095] auto[0] 94 1 T14 1 T17 1 T48 1
auto[805306368:939524095] auto[1] 5 1 T66 1 T407 2 T364 1
auto[939524096:1073741823] auto[0] 92 1 T57 1 T58 2 T129 1
auto[939524096:1073741823] auto[1] 14 1 T66 2 T69 1 T407 1
auto[1073741824:1207959551] auto[0] 102 1 T3 1 T12 2 T213 1
auto[1073741824:1207959551] auto[1] 7 1 T11 1 T83 1 T72 1
auto[1207959552:1342177279] auto[0] 84 1 T36 1 T88 1 T220 1
auto[1207959552:1342177279] auto[1] 8 1 T69 1 T248 1 T424 1
auto[1342177280:1476395007] auto[0] 68 1 T140 1 T102 1 T89 1
auto[1342177280:1476395007] auto[1] 13 1 T304 1 T405 1 T407 1
auto[1476395008:1610612735] auto[0] 104 1 T12 1 T34 1 T57 2
auto[1476395008:1610612735] auto[1] 7 1 T11 1 T57 1 T70 1
auto[1610612736:1744830463] auto[0] 85 1 T13 1 T14 1 T16 1
auto[1610612736:1744830463] auto[1] 10 1 T57 1 T288 2 T424 1
auto[1744830464:1879048191] auto[0] 87 1 T11 1 T58 1 T213 1
auto[1744830464:1879048191] auto[1] 7 1 T83 1 T248 1 T414 1
auto[1879048192:2013265919] auto[0] 95 1 T12 1 T15 1 T213 1
auto[1879048192:2013265919] auto[1] 9 1 T57 1 T357 1 T421 1
auto[2013265920:2147483647] auto[0] 91 1 T57 1 T66 1 T117 1
auto[2013265920:2147483647] auto[1] 11 1 T338 1 T283 1 T407 1
auto[2147483648:2281701375] auto[0] 76 1 T13 1 T14 1 T48 1
auto[2147483648:2281701375] auto[1] 10 1 T57 2 T70 1 T407 1
auto[2281701376:2415919103] auto[0] 94 1 T3 1 T13 1 T57 2
auto[2281701376:2415919103] auto[1] 10 1 T72 1 T248 1 T283 1
auto[2415919104:2550136831] auto[0] 99 1 T14 1 T35 1 T60 1
auto[2415919104:2550136831] auto[1] 5 1 T69 1 T412 1 T405 1
auto[2550136832:2684354559] auto[0] 78 1 T34 2 T216 1 T42 1
auto[2550136832:2684354559] auto[1] 9 1 T57 1 T406 1 T287 1
auto[2684354560:2818572287] auto[0] 102 1 T11 1 T17 1 T57 1
auto[2684354560:2818572287] auto[1] 6 1 T72 1 T357 1 T404 1
auto[2818572288:2952790015] auto[0] 93 1 T119 1 T103 1 T85 2
auto[2818572288:2952790015] auto[1] 3 1 T407 1 T410 1 T418 1
auto[2952790016:3087007743] auto[0] 81 1 T17 1 T211 1 T52 1
auto[2952790016:3087007743] auto[1] 6 1 T70 1 T248 1 T364 1
auto[3087007744:3221225471] auto[0] 87 1 T58 1 T211 1 T129 1
auto[3087007744:3221225471] auto[1] 14 1 T66 1 T83 1 T84 1
auto[3221225472:3355443199] auto[0] 92 1 T11 1 T17 1 T58 1
auto[3221225472:3355443199] auto[1] 6 1 T404 1 T424 1 T414 1
auto[3355443200:3489660927] auto[0] 95 1 T60 1 T61 1 T219 1
auto[3355443200:3489660927] auto[1] 14 1 T83 1 T283 2 T412 1
auto[3489660928:3623878655] auto[0] 96 1 T18 1 T117 1 T83 2
auto[3489660928:3623878655] auto[1] 17 1 T84 1 T72 1 T283 1
auto[3623878656:3758096383] auto[0] 82 1 T12 1 T216 1 T68 1
auto[3623878656:3758096383] auto[1] 8 1 T66 1 T83 1 T304 2
auto[3758096384:3892314111] auto[0] 91 1 T11 1 T34 1 T216 1
auto[3758096384:3892314111] auto[1] 9 1 T11 1 T357 1 T350 1
auto[3892314112:4026531839] auto[0] 79 1 T45 2 T57 1 T58 1
auto[3892314112:4026531839] auto[1] 10 1 T83 1 T70 1 T248 1
auto[4026531840:4160749567] auto[0] 75 1 T114 1 T117 1 T253 1
auto[4026531840:4160749567] auto[1] 6 1 T72 1 T338 1 T412 1
auto[4160749568:4294967295] auto[0] 80 1 T3 1 T220 1 T84 2
auto[4160749568:4294967295] auto[1] 8 1 T11 2 T357 1 T407 1

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