Unified Coverage Report :: Group Instance : sealing_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1472

1

T3

2

T11

1

T12

1

auto[1]

1763

1

T3

1

T11

3

T12

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	89	1			T68	1		T85	1		T220	1
auto[134217728:268435455]	102	1			T17	1		T48	1		T36	1
auto[268435456:402653183]	90	1			T216	1		T68	1		T39	1
auto[402653184:536870911]	112	1			T3	1		T14	1		T34	1
auto[536870912:671088639]	123	1			T14	1		T57	1		T119	1
auto[671088640:805306367]	95	1			T12	1		T13	1		T34	1
auto[805306368:939524095]	90	1			T3	1		T12	1		T17	1
auto[939524096:1073741823]	92	1			T11	1		T17	2		T57	2
auto[1073741824:1207959551]	99	1			T11	1		T13	1		T58	1
auto[1207959552:1342177279]	129	1			T11	1		T12	1		T57	1
auto[1342177280:1476395007]	101	1			T216	2		T66	1		T92	1
auto[1476395008:1610612735]	97	1			T58	1		T216	1		T68	2
auto[1610612736:1744830463]	132	1			T17	1		T68	1		T85	1
auto[1744830464:1879048191]	107	1			T48	1		T57	1		T36	1
auto[1879048192:2013265919]	109	1			T3	1		T48	1		T58	1
auto[2013265920:2147483647]	106	1			T61	1		T83	2		T5	1
auto[2147483648:2281701375]	102	1			T12	1		T15	1		T34	1
auto[2281701376:2415919103]	75	1			T213	1		T103	1		T68	1
auto[2415919104:2550136831]	87	1			T13	1		T42	1		T104	1
auto[2550136832:2684354559]	120	1			T13	1		T17	1		T60	2
auto[2684354560:2818572287]	99	1			T16	1		T34	1		T57	1
auto[2818572288:2952790015]	103	1			T14	1		T103	1		T68	1
auto[2952790016:3087007743]	93	1			T35	1		T211	1		T218	2
auto[3087007744:3221225471]	89	1			T14	1		T92	1		T228	1
auto[3221225472:3355443199]	91	1			T12	1		T13	1		T61	1
auto[3355443200:3489660927]	91	1			T17	1		T36	1		T35	1
auto[3489660928:3623878655]	108	1			T57	1		T219	1		T67	1
auto[3623878656:3758096383]	103	1			T34	1		T57	1		T36	1
auto[3758096384:3892314111]	101	1			T12	1		T13	1		T48	1
auto[3892314112:4026531839]	99	1			T11	1		T45	1		T216	1
auto[4026531840:4160749567]	94	1			T13	1		T14	1		T34	1
auto[4160749568:4294967295]	107	1			T68	2		T220	1		T115	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	39	1			T68	1		T85	1		T228	1
auto[0:134217727]	auto[1]	50	1			T220	1		T218	1		T228	1
auto[134217728:268435455]	auto[0]	45	1			T17	1		T36	1		T219	1
auto[134217728:268435455]	auto[1]	57	1			T48	1		T18	1		T211	1
auto[268435456:402653183]	auto[0]	38	1			T129	1		T88	2		T5	1
auto[268435456:402653183]	auto[1]	52	1			T216	1		T68	1		T39	1
auto[402653184:536870911]	auto[0]	53	1			T3	1		T58	1		T36	1
auto[402653184:536870911]	auto[1]	59	1			T14	1		T34	1		T58	1
auto[536870912:671088639]	auto[0]	49	1			T68	1		T245	1		T5	1
auto[536870912:671088639]	auto[1]	74	1			T14	1		T57	1		T119	1
auto[671088640:805306367]	auto[0]	44	1			T34	1		T68	2		T129	1
auto[671088640:805306367]	auto[1]	51	1			T12	1		T13	1		T58	1
auto[805306368:939524095]	auto[0]	35	1			T3	1		T17	1		T117	1
auto[805306368:939524095]	auto[1]	55	1			T12	1		T84	1		T417	1
auto[939524096:1073741823]	auto[0]	37	1			T17	2		T57	1		T280	2
auto[939524096:1073741823]	auto[1]	55	1			T11	1		T57	1		T277	1
auto[1073741824:1207959551]	auto[0]	44	1			T88	1		T5	3		T21	1
auto[1073741824:1207959551]	auto[1]	55	1			T11	1		T13	1		T58	1
auto[1207959552:1342177279]	auto[0]	63	1			T12	1		T57	1		T66	1
auto[1207959552:1342177279]	auto[1]	66	1			T11	1		T35	1		T68	1
auto[1342177280:1476395007]	auto[0]	53	1			T216	1		T129	1		T5	1
auto[1342177280:1476395007]	auto[1]	48	1			T216	1		T66	1		T92	1
auto[1476395008:1610612735]	auto[0]	35	1			T58	1		T68	2		T22	1
auto[1476395008:1610612735]	auto[1]	62	1			T216	1		T129	1		T218	1
auto[1610612736:1744830463]	auto[0]	62	1			T17	1		T85	1		T218	1
auto[1610612736:1744830463]	auto[1]	70	1			T68	1		T84	1		T125	1
auto[1744830464:1879048191]	auto[0]	51	1			T36	1		T103	1		T5	1
auto[1744830464:1879048191]	auto[1]	56	1			T48	1		T57	1		T85	1
auto[1879048192:2013265919]	auto[0]	49	1			T48	1		T58	1		T213	1
auto[1879048192:2013265919]	auto[1]	60	1			T3	1		T68	1		T88	1
auto[2013265920:2147483647]	auto[0]	51	1			T61	1		T83	1		T5	1
auto[2013265920:2147483647]	auto[1]	55	1			T83	1		T199	1		T72	1
auto[2147483648:2281701375]	auto[0]	48	1			T34	1		T36	1		T6	1
auto[2147483648:2281701375]	auto[1]	54	1			T12	1		T15	1		T216	1
auto[2281701376:2415919103]	auto[0]	31	1			T21	1		T140	1		T102	1
auto[2281701376:2415919103]	auto[1]	44	1			T213	1		T103	1		T68	1
auto[2415919104:2550136831]	auto[0]	41	1			T104	1		T228	1		T253	1
auto[2415919104:2550136831]	auto[1]	46	1			T13	1		T42	1		T141	2
auto[2550136832:2684354559]	auto[0]	52	1			T17	1		T39	1		T245	1
auto[2550136832:2684354559]	auto[1]	68	1			T13	1		T60	2		T114	1
auto[2684354560:2818572287]	auto[0]	46	1			T34	1		T119	1		T229	1
auto[2684354560:2818572287]	auto[1]	53	1			T16	1		T57	1		T213	1
auto[2818572288:2952790015]	auto[0]	44	1			T14	1		T85	1		T124	2
auto[2818572288:2952790015]	auto[1]	59	1			T103	1		T68	1		T245	1
auto[2952790016:3087007743]	auto[0]	45	1			T35	1		T218	1		T253	1
auto[2952790016:3087007743]	auto[1]	48	1			T211	1		T218	1		T84	1
auto[3087007744:3221225471]	auto[0]	32	1			T123	1		T142	1		T143	1
auto[3087007744:3221225471]	auto[1]	57	1			T14	1		T92	1		T228	1
auto[3221225472:3355443199]	auto[0]	45	1			T61	1		T125	1		T280	2
auto[3221225472:3355443199]	auto[1]	46	1			T12	1		T13	1		T66	1
auto[3355443200:3489660927]	auto[0]	43	1			T17	1		T36	1		T35	1
auto[3355443200:3489660927]	auto[1]	48	1			T213	1		T5	1		T253	1
auto[3489660928:3623878655]	auto[0]	40	1			T67	1		T5	1		T143	1
auto[3489660928:3623878655]	auto[1]	68	1			T57	1		T219	1		T129	1
auto[3623878656:3758096383]	auto[0]	53	1			T34	1		T57	1		T129	1
auto[3623878656:3758096383]	auto[1]	50	1			T36	1		T218	1		T244	1
auto[3758096384:3892314111]	auto[0]	51	1			T45	1		T68	1		T228	1
auto[3758096384:3892314111]	auto[1]	50	1			T12	1		T13	1		T48	1
auto[3892314112:4026531839]	auto[0]	44	1			T11	1		T5	2		T84	1
auto[3892314112:4026531839]	auto[1]	55	1			T45	1		T216	1		T210	1
auto[4026531840:4160749567]	auto[0]	50	1			T34	1		T67	1		T85	1
auto[4026531840:4160749567]	auto[1]	44	1			T13	1		T14	1		T48	1
auto[4160749568:4294967295]	auto[0]	59	1			T220	1		T115	1		T21	1
auto[4160749568:4294967295]	auto[1]	48	1			T68	2		T140	1		T102	2