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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1479 1 T3 2 T11 1 T12 1
auto[1] 1756 1 T3 1 T11 3 T12 5


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 124 1 T17 1 T68 1 T92 1
auto[134217728:268435455] 92 1 T14 1 T36 1 T60 1
auto[268435456:402653183] 89 1 T16 1 T57 1 T36 1
auto[402653184:536870911] 102 1 T13 1 T57 2 T103 1
auto[536870912:671088639] 105 1 T3 2 T57 2 T213 1
auto[671088640:805306367] 117 1 T17 1 T66 2 T68 1
auto[805306368:939524095] 84 1 T14 1 T61 1 T119 1
auto[939524096:1073741823] 102 1 T11 1 T45 1 T216 1
auto[1073741824:1207959551] 96 1 T68 1 T112 1 T84 1
auto[1207959552:1342177279] 89 1 T34 2 T61 1 T129 2
auto[1342177280:1476395007] 108 1 T11 1 T13 1 T34 1
auto[1476395008:1610612735] 79 1 T12 1 T14 1 T57 1
auto[1610612736:1744830463] 107 1 T12 1 T17 1 T48 1
auto[1744830464:1879048191] 111 1 T34 1 T61 1 T216 1
auto[1879048192:2013265919] 109 1 T48 1 T58 1 T36 1
auto[2013265920:2147483647] 97 1 T58 1 T35 1 T216 1
auto[2147483648:2281701375] 95 1 T12 1 T34 1 T218 1
auto[2281701376:2415919103] 83 1 T12 1 T58 1 T67 1
auto[2415919104:2550136831] 83 1 T17 1 T216 1 T218 1
auto[2550136832:2684354559] 97 1 T13 1 T35 1 T104 2
auto[2684354560:2818572287] 105 1 T11 1 T12 1 T219 1
auto[2818572288:2952790015] 117 1 T13 1 T14 1 T17 1
auto[2952790016:3087007743] 109 1 T15 1 T48 1 T216 1
auto[3087007744:3221225471] 114 1 T13 1 T17 1 T68 1
auto[3221225472:3355443199] 89 1 T12 1 T13 1 T57 1
auto[3355443200:3489660927] 92 1 T14 1 T34 1 T5 1
auto[3489660928:3623878655] 100 1 T13 1 T45 1 T36 1
auto[3623878656:3758096383] 102 1 T3 1 T17 1 T48 1
auto[3758096384:3892314111] 107 1 T213 1 T68 3 T85 1
auto[3892314112:4026531839] 115 1 T11 1 T58 1 T119 1
auto[4026531840:4160749567] 124 1 T36 1 T211 1 T68 1
auto[4160749568:4294967295] 92 1 T57 1 T58 1 T36 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 54 1 T17 1 T117 1 T6 1
auto[0:134217727] auto[1] 70 1 T68 1 T92 1 T84 1
auto[134217728:268435455] auto[0] 34 1 T36 1 T85 1 T129 1
auto[134217728:268435455] auto[1] 58 1 T14 1 T60 1 T18 1
auto[268435456:402653183] auto[0] 46 1 T36 1 T213 1 T68 1
auto[268435456:402653183] auto[1] 43 1 T16 1 T57 1 T103 1
auto[402653184:536870911] auto[0] 51 1 T57 1 T5 1 T253 1
auto[402653184:536870911] auto[1] 51 1 T13 1 T57 1 T103 1
auto[536870912:671088639] auto[0] 51 1 T3 1 T213 1 T67 1
auto[536870912:671088639] auto[1] 54 1 T3 1 T57 2 T66 1
auto[671088640:805306367] auto[0] 53 1 T17 1 T66 1 T117 1
auto[671088640:805306367] auto[1] 64 1 T66 1 T68 1 T92 1
auto[805306368:939524095] auto[0] 41 1 T61 1 T119 1 T218 1
auto[805306368:939524095] auto[1] 43 1 T14 1 T68 1 T117 1
auto[939524096:1073741823] auto[0] 47 1 T11 1 T45 1 T216 1
auto[939524096:1073741823] auto[1] 55 1 T84 1 T51 1 T52 1
auto[1073741824:1207959551] auto[0] 43 1 T68 1 T84 1 T102 1
auto[1073741824:1207959551] auto[1] 53 1 T112 1 T51 1 T130 1
auto[1207959552:1342177279] auto[0] 47 1 T34 2 T61 1 T129 1
auto[1207959552:1342177279] auto[1] 42 1 T129 1 T303 1 T244 1
auto[1342177280:1476395007] auto[0] 48 1 T34 1 T68 1 T88 1
auto[1342177280:1476395007] auto[1] 60 1 T11 1 T13 1 T213 1
auto[1476395008:1610612735] auto[0] 37 1 T57 1 T229 1 T69 1
auto[1476395008:1610612735] auto[1] 42 1 T12 1 T14 1 T119 1
auto[1610612736:1744830463] auto[0] 49 1 T17 1 T48 1 T42 1
auto[1610612736:1744830463] auto[1] 58 1 T12 1 T67 1 T42 1
auto[1744830464:1879048191] auto[0] 53 1 T34 1 T61 1 T5 1
auto[1744830464:1879048191] auto[1] 58 1 T216 1 T68 1 T42 1
auto[1879048192:2013265919] auto[0] 51 1 T58 1 T36 1 T67 1
auto[1879048192:2013265919] auto[1] 58 1 T48 1 T92 1 T220 1
auto[2013265920:2147483647] auto[0] 37 1 T35 1 T143 1 T102 3
auto[2013265920:2147483647] auto[1] 60 1 T58 1 T216 1 T66 1
auto[2147483648:2281701375] auto[0] 51 1 T218 1 T5 1 T115 1
auto[2147483648:2281701375] auto[1] 44 1 T12 1 T34 1 T5 2
auto[2281701376:2415919103] auto[0] 34 1 T67 1 T40 1 T229 1
auto[2281701376:2415919103] auto[1] 49 1 T12 1 T58 1 T211 1
auto[2415919104:2550136831] auto[0] 43 1 T216 1 T218 1 T21 1
auto[2415919104:2550136831] auto[1] 40 1 T17 1 T125 1 T130 3
auto[2550136832:2684354559] auto[0] 46 1 T35 1 T104 2 T228 1
auto[2550136832:2684354559] auto[1] 51 1 T13 1 T52 1 T289 1
auto[2684354560:2818572287] auto[0] 45 1 T12 1 T213 1 T66 1
auto[2684354560:2818572287] auto[1] 60 1 T11 1 T219 1 T210 1
auto[2818572288:2952790015] auto[0] 51 1 T14 1 T17 1 T5 1
auto[2818572288:2952790015] auto[1] 66 1 T13 1 T48 1 T60 1
auto[2952790016:3087007743] auto[0] 46 1 T68 1 T6 1 T276 1
auto[2952790016:3087007743] auto[1] 63 1 T15 1 T48 1 T216 1
auto[3087007744:3221225471] auto[0] 54 1 T17 1 T68 1 T5 1
auto[3087007744:3221225471] auto[1] 60 1 T13 1 T117 1 T129 1
auto[3221225472:3355443199] auto[0] 40 1 T58 1 T219 1 T218 1
auto[3221225472:3355443199] auto[1] 49 1 T12 1 T13 1 T57 1
auto[3355443200:3489660927] auto[0] 40 1 T34 1 T5 1 T280 1
auto[3355443200:3489660927] auto[1] 52 1 T14 1 T113 1 T102 1
auto[3489660928:3623878655] auto[0] 47 1 T36 1 T68 1 T5 1
auto[3489660928:3623878655] auto[1] 53 1 T13 1 T45 1 T66 1
auto[3623878656:3758096383] auto[0] 47 1 T3 1 T17 1 T48 1
auto[3623878656:3758096383] auto[1] 55 1 T51 1 T340 1 T130 3
auto[3758096384:3892314111] auto[0] 44 1 T68 2 T129 1 T294 1
auto[3758096384:3892314111] auto[1] 63 1 T213 1 T68 1 T85 1
auto[3892314112:4026531839] auto[0] 49 1 T58 1 T119 1 T103 1
auto[3892314112:4026531839] auto[1] 66 1 T11 1 T52 1 T69 2
auto[4026531840:4160749567] auto[0] 64 1 T36 1 T68 1 T85 1
auto[4026531840:4160749567] auto[1] 60 1 T211 1 T42 1 T218 1
auto[4160749568:4294967295] auto[0] 36 1 T36 1 T229 1 T228 1
auto[4160749568:4294967295] auto[1] 56 1 T57 1 T58 1 T85 1

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