Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6711

1

T3

6

T11

7

T12

11

auto[1]

245

1

T11

5

T57

5

T66

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2799	1			T3	3		T11	3		T12	5
auto[134217728:268435455]	134	1			T3	1		T219	2		T216	1
auto[268435456:402653183]	130	1			T103	1		T211	1		T210	1
auto[402653184:536870911]	178	1			T11	1		T13	1		T17	1
auto[536870912:671088639]	159	1			T14	1		T34	2		T57	1
auto[671088640:805306367]	124	1			T57	1		T213	1		T211	2
auto[805306368:939524095]	152	1			T12	1		T13	2		T58	1
auto[939524096:1073741823]	160	1			T11	1		T17	1		T211	1
auto[1073741824:1207959551]	115	1			T3	1		T211	1		T117	1
auto[1207959552:1342177279]	146	1			T11	1		T14	1		T58	1
auto[1342177280:1476395007]	132	1			T11	1		T57	2		T58	1
auto[1476395008:1610612735]	129	1			T3	1		T11	1		T14	1
auto[1610612736:1744830463]	138	1			T13	1		T34	2		T216	1
auto[1744830464:1879048191]	140	1			T12	1		T13	1		T39	1
auto[1879048192:2013265919]	132	1			T14	1		T17	1		T45	1
auto[2013265920:2147483647]	129	1			T57	1		T219	1		T213	2
auto[2147483648:2281701375]	123	1			T12	1		T17	1		T66	1
auto[2281701376:2415919103]	120	1			T14	1		T34	1		T17	1
auto[2415919104:2550136831]	138	1			T11	1		T12	1		T14	1
auto[2550136832:2684354559]	119	1			T16	1		T17	1		T57	1
auto[2684354560:2818572287]	118	1			T57	1		T211	1		T42	1
auto[2818572288:2952790015]	145	1			T14	1		T103	1		T211	1
auto[2952790016:3087007743]	132	1			T12	1		T14	1		T17	1
auto[3087007744:3221225471]	110	1			T48	1		T57	1		T58	1
auto[3221225472:3355443199]	123	1			T66	1		T119	1		T68	1
auto[3355443200:3489660927]	135	1			T14	1		T15	1		T57	1
auto[3489660928:3623878655]	128	1			T57	1		T213	1		T103	1
auto[3623878656:3758096383]	120	1			T12	1		T36	1		T219	1
auto[3758096384:3892314111]	138	1			T11	1		T48	1		T45	1
auto[3892314112:4026531839]	134	1			T34	1		T57	1		T58	1
auto[4026531840:4160749567]	144	1			T11	1		T14	1		T61	1
auto[4160749568:4294967295]	132	1			T11	1		T219	2		T213	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2793	1			T3	3		T11	3		T12	5
auto[0:134217727]	auto[1]	6	1			T244	1		T405	1		T348	1
auto[134217728:268435455]	auto[0]	131	1			T3	1		T219	2		T216	1
auto[134217728:268435455]	auto[1]	3	1			T244	1		T72	1		T418	1
auto[268435456:402653183]	auto[0]	125	1			T103	1		T211	1		T210	1
auto[268435456:402653183]	auto[1]	5	1			T249	1		T405	1		T255	1
auto[402653184:536870911]	auto[0]	162	1			T13	1		T17	1		T219	1
auto[402653184:536870911]	auto[1]	16	1			T11	1		T57	1		T83	1
auto[536870912:671088639]	auto[0]	149	1			T14	1		T34	2		T57	1
auto[536870912:671088639]	auto[1]	10	1			T248	1		T283	1		T404	2
auto[671088640:805306367]	auto[0]	114	1			T57	1		T213	1		T211	2
auto[671088640:805306367]	auto[1]	10	1			T72	1		T404	1		T414	1
auto[805306368:939524095]	auto[0]	140	1			T12	1		T13	2		T58	1
auto[805306368:939524095]	auto[1]	12	1			T71	1		T357	1		T407	2
auto[939524096:1073741823]	auto[0]	156	1			T17	1		T211	1		T68	3
auto[939524096:1073741823]	auto[1]	4	1			T11	1		T248	1		T406	1
auto[1073741824:1207959551]	auto[0]	106	1			T3	1		T211	1		T117	1
auto[1073741824:1207959551]	auto[1]	9	1			T83	1		T248	1		T357	1
auto[1207959552:1342177279]	auto[0]	139	1			T14	1		T58	1		T216	1
auto[1207959552:1342177279]	auto[1]	7	1			T11	1		T70	1		T404	1
auto[1342177280:1476395007]	auto[0]	123	1			T11	1		T57	1		T58	1
auto[1342177280:1476395007]	auto[1]	9	1			T57	1		T283	1		T350	1
auto[1476395008:1610612735]	auto[0]	128	1			T3	1		T11	1		T14	1
auto[1476395008:1610612735]	auto[1]	1	1			T373	1		-	-		-	-
auto[1610612736:1744830463]	auto[0]	130	1			T13	1		T34	2		T216	1
auto[1610612736:1744830463]	auto[1]	8	1			T72	1		T414	4		T419	1
auto[1744830464:1879048191]	auto[0]	132	1			T12	1		T13	1		T39	1
auto[1744830464:1879048191]	auto[1]	8	1			T83	1		T283	1		T404	2
auto[1879048192:2013265919]	auto[0]	126	1			T14	1		T17	1		T45	1
auto[1879048192:2013265919]	auto[1]	6	1			T72	1		T283	1		T406	1
auto[2013265920:2147483647]	auto[0]	121	1			T219	1		T213	2		T68	1
auto[2013265920:2147483647]	auto[1]	8	1			T57	1		T420	1		T312	2
auto[2147483648:2281701375]	auto[0]	116	1			T12	1		T17	1		T66	1
auto[2147483648:2281701375]	auto[1]	7	1			T404	1		T421	1		T414	1
auto[2281701376:2415919103]	auto[0]	117	1			T14	1		T34	1		T17	1
auto[2281701376:2415919103]	auto[1]	3	1			T412	1		T422	1		T423	1
auto[2415919104:2550136831]	auto[0]	129	1			T11	1		T12	1		T14	1
auto[2415919104:2550136831]	auto[1]	9	1			T413	1		T420	1		T414	3
auto[2550136832:2684354559]	auto[0]	106	1			T16	1		T17	1		T57	1
auto[2550136832:2684354559]	auto[1]	13	1			T83	2		T288	1		T283	1
auto[2684354560:2818572287]	auto[0]	113	1			T57	1		T211	1		T42	1
auto[2684354560:2818572287]	auto[1]	5	1			T70	1		T404	1		T407	1
auto[2818572288:2952790015]	auto[0]	137	1			T14	1		T103	1		T211	1
auto[2818572288:2952790015]	auto[1]	8	1			T72	1		T248	1		T338	1
auto[2952790016:3087007743]	auto[0]	128	1			T12	1		T14	1		T17	1
auto[2952790016:3087007743]	auto[1]	4	1			T407	2		T406	1		T255	1
auto[3087007744:3221225471]	auto[0]	101	1			T48	1		T58	1		T219	1
auto[3087007744:3221225471]	auto[1]	9	1			T57	1		T283	1		T304	1
auto[3221225472:3355443199]	auto[0]	114	1			T119	1		T68	1		T39	1
auto[3221225472:3355443199]	auto[1]	9	1			T66	1		T248	2		T424	1
auto[3355443200:3489660927]	auto[0]	124	1			T14	1		T15	1		T57	1
auto[3355443200:3489660927]	auto[1]	11	1			T304	1		T405	1		T424	1
auto[3489660928:3623878655]	auto[0]	123	1			T57	1		T213	1		T103	1
auto[3489660928:3623878655]	auto[1]	5	1			T69	1		T357	1		T413	1
auto[3623878656:3758096383]	auto[0]	112	1			T12	1		T36	1		T219	1
auto[3623878656:3758096383]	auto[1]	8	1			T405	1		T420	1		T287	1
auto[3758096384:3892314111]	auto[0]	129	1			T11	1		T48	1		T45	1
auto[3758096384:3892314111]	auto[1]	9	1			T57	1		T66	1		T69	1
auto[3892314112:4026531839]	auto[0]	128	1			T34	1		T57	1		T58	1
auto[3892314112:4026531839]	auto[1]	6	1			T83	1		T248	1		T405	1
auto[4026531840:4160749567]	auto[0]	135	1			T14	1		T61	1		T213	1
auto[4026531840:4160749567]	auto[1]	9	1			T11	1		T69	1		T70	1
auto[4160749568:4294967295]	auto[0]	124	1			T219	2		T213	1		T68	1
auto[4160749568:4294967295]	auto[1]	8	1			T11	1		T72	1		T412	1