Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4286

1

T3

2

T11

8

T12

8

auto[1]

2184

1

T3

4

T12

4

T13

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	152	1			T11	2		T61	2		T18	2
auto[134217728:268435455]	198	1			T48	2		T61	2		T66	2
auto[268435456:402653183]	202	1			T12	2		T16	2		T48	2
auto[402653184:536870911]	210	1			T57	4		T119	2		T228	2
auto[536870912:671088639]	202	1			T66	2		T104	4		T115	2
auto[671088640:805306367]	236	1			T14	2		T17	4		T58	2
auto[805306368:939524095]	242	1			T3	2		T57	4		T36	2
auto[939524096:1073741823]	200	1			T15	2		T34	2		T36	2
auto[1073741824:1207959551]	186	1			T3	2		T57	2		T117	2
auto[1207959552:1342177279]	192	1			T14	2		T119	2		T68	2
auto[1342177280:1476395007]	184	1			T12	2		T13	2		T35	2
auto[1476395008:1610612735]	184	1			T60	2		T68	2		T88	2
auto[1610612736:1744830463]	228	1			T12	2		T13	2		T14	2
auto[1744830464:1879048191]	244	1			T11	2		T13	2		T34	2
auto[1879048192:2013265919]	194	1			T34	2		T48	2		T58	2
auto[2013265920:2147483647]	176	1			T129	2		T253	2		T52	2
auto[2147483648:2281701375]	210	1			T17	2		T48	2		T45	2
auto[2281701376:2415919103]	206	1			T12	2		T213	2		T68	4
auto[2415919104:2550136831]	224	1			T17	2		T58	2		T68	6
auto[2550136832:2684354559]	240	1			T34	2		T48	2		T66	2
auto[2684354560:2818572287]	204	1			T17	2		T219	2		T114	2
auto[2818572288:2952790015]	206	1			T13	2		T213	2		T68	2
auto[2952790016:3087007743]	162	1			T58	2		T36	2		T67	2
auto[3087007744:3221225471]	200	1			T34	2		T58	2		T103	2
auto[3221225472:3355443199]	176	1			T12	2		T42	2		T218	2
auto[3355443200:3489660927]	214	1			T3	2		T11	2		T13	2
auto[3489660928:3623878655]	194	1			T12	2		T13	2		T216	2
auto[3623878656:3758096383]	188	1			T17	2		T45	2		T213	2
auto[3758096384:3892314111]	224	1			T66	2		T67	2		T83	4
auto[3892314112:4026531839]	220	1			T13	2		T14	2		T34	2
auto[4026531840:4160749567]	194	1			T11	2		T14	2		T58	2
auto[4160749568:4294967295]	178	1			T17	2		T213	2		T92	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	94	1			T11	2		T68	2		T280	2
auto[0:134217727]	auto[1]	58	1			T61	2		T18	2		T27	2
auto[134217728:268435455]	auto[0]	138	1			T48	2		T66	2		T218	2
auto[134217728:268435455]	auto[1]	60	1			T61	2		T252	2		T305	2
auto[268435456:402653183]	auto[0]	128	1			T42	2		T220	2		T51	2
auto[268435456:402653183]	auto[1]	74	1			T12	2		T16	2		T48	2
auto[402653184:536870911]	auto[0]	120	1			T57	2		T119	2		T228	2
auto[402653184:536870911]	auto[1]	90	1			T57	2		T253	2		T53	2
auto[536870912:671088639]	auto[0]	140	1			T66	2		T115	2		T69	2
auto[536870912:671088639]	auto[1]	62	1			T104	4		T51	2		T130	2
auto[671088640:805306367]	auto[0]	154	1			T14	2		T17	4		T58	2
auto[671088640:805306367]	auto[1]	82	1			T36	2		T66	2		T245	2
auto[805306368:939524095]	auto[0]	162	1			T57	4		T36	2		T35	2
auto[805306368:939524095]	auto[1]	80	1			T3	2		T61	2		T216	2
auto[939524096:1073741823]	auto[0]	138	1			T34	2		T36	2		T35	2
auto[939524096:1073741823]	auto[1]	62	1			T15	2		T83	2		T40	2
auto[1073741824:1207959551]	auto[0]	120	1			T117	2		T220	2		T253	2
auto[1073741824:1207959551]	auto[1]	66	1			T3	2		T57	2		T85	4
auto[1207959552:1342177279]	auto[0]	122	1			T14	2		T68	2		T129	2
auto[1207959552:1342177279]	auto[1]	70	1			T119	2		T42	2		T52	2
auto[1342177280:1476395007]	auto[0]	136	1			T12	2		T13	2		T219	2
auto[1342177280:1476395007]	auto[1]	48	1			T35	2		T253	2		T102	2
auto[1476395008:1610612735]	auto[0]	116	1			T68	2		T88	2		T21	2
auto[1476395008:1610612735]	auto[1]	68	1			T60	2		T5	2		T303	2
auto[1610612736:1744830463]	auto[0]	156	1			T12	2		T13	2		T14	2
auto[1610612736:1744830463]	auto[1]	72	1			T85	2		T5	2		T23	2
auto[1744830464:1879048191]	auto[0]	162	1			T11	2		T13	2		T34	2
auto[1744830464:1879048191]	auto[1]	82	1			T211	2		T88	2		T6	2
auto[1879048192:2013265919]	auto[0]	134	1			T34	2		T48	2		T58	2
auto[1879048192:2013265919]	auto[1]	60	1			T36	2		T211	2		T68	2
auto[2013265920:2147483647]	auto[0]	118	1			T129	2		T253	2		T206	2
auto[2013265920:2147483647]	auto[1]	58	1			T52	2		T89	2		T71	2
auto[2147483648:2281701375]	auto[0]	132	1			T17	2		T48	2		T42	2
auto[2147483648:2281701375]	auto[1]	78	1			T45	2		T60	2		T117	2
auto[2281701376:2415919103]	auto[0]	134	1			T12	2		T213	2		T68	2
auto[2281701376:2415919103]	auto[1]	72	1			T68	2		T84	2		T188	2
auto[2415919104:2550136831]	auto[0]	140	1			T17	2		T58	2		T68	4
auto[2415919104:2550136831]	auto[1]	84	1			T68	2		T92	2		T245	2
auto[2550136832:2684354559]	auto[0]	146	1			T34	2		T48	2		T66	2
auto[2550136832:2684354559]	auto[1]	94	1			T220	2		T5	2		T6	2
auto[2684354560:2818572287]	auto[0]	146	1			T17	2		T219	2		T117	2
auto[2684354560:2818572287]	auto[1]	58	1			T114	2		T52	2		T277	2
auto[2818572288:2952790015]	auto[0]	124	1			T213	2		T39	2		T129	2
auto[2818572288:2952790015]	auto[1]	82	1			T13	2		T68	2		T85	2
auto[2952790016:3087007743]	auto[0]	102	1			T58	2		T36	2		T67	2
auto[2952790016:3087007743]	auto[1]	60	1			T104	2		T52	6		T231	2
auto[3087007744:3221225471]	auto[0]	142	1			T34	2		T58	2		T103	2
auto[3087007744:3221225471]	auto[1]	58	1			T104	2		T141	2		T277	2
auto[3221225472:3355443199]	auto[0]	122	1			T12	2		T42	2		T218	2
auto[3221225472:3355443199]	auto[1]	54	1			T229	2		T6	2		T102	2
auto[3355443200:3489660927]	auto[0]	146	1			T3	2		T11	2		T13	2
auto[3355443200:3489660927]	auto[1]	68	1			T104	2		T6	2		T130	2
auto[3489660928:3623878655]	auto[0]	134	1			T13	2		T216	2		T68	2
auto[3489660928:3623878655]	auto[1]	60	1			T12	2		T119	2		T229	2
auto[3623878656:3758096383]	auto[0]	130	1			T17	2		T213	2		T66	2
auto[3623878656:3758096383]	auto[1]	58	1			T45	2		T210	2		T129	2
auto[3758096384:3892314111]	auto[0]	164	1			T66	2		T67	2		T83	4
auto[3758096384:3892314111]	auto[1]	60	1			T69	2		T142	2		T398	2
auto[3892314112:4026531839]	auto[0]	136	1			T14	2		T57	2		T39	2
auto[3892314112:4026531839]	auto[1]	84	1			T13	2		T34	2		T213	2
auto[4026531840:4160749567]	auto[0]	138	1			T11	2		T14	2		T58	2
auto[4026531840:4160749567]	auto[1]	56	1			T5	2		T41	2		T207	2
auto[4160749568:4294967295]	auto[0]	112	1			T17	2		T213	2		T220	2
auto[4160749568:4294967295]	auto[1]	66	1			T92	2		T245	2		T417	2