Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
74.60	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

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Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	15	34	69.39

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	14	21	60.00	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	44	1			T90	1		T27	1		T127	1
auto[OpGenId]	12	1			T18	1		T36	1		T141	1
auto[OpGenSwOut]	21	1			T56	1		T131	1		T9	1
auto[OpGenHwOut]	28	1			T5	1		T6	1		T7	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1845	1			T10	180		T11	90		T44	1
auto[StInit]	92	1			T35	1		T27	1		T116	1
auto[StCreatorRootKey]	64	1			T15	1		T38	1		T108	1
auto[StOwnerIntKey]	43	1			T90	1		T33	1		T64	1
auto[StOwnerKey]	24	1			T18	1		T5	1		T45	1
auto[StDisabled]	419	1			T90	2		T8	1		T44	3
auto[StInvalid]	49	1			T14	1		T34	1		T39	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3509

1

T1

1

T2

1

T3

1

auto[1]

105

1

T18

1

T5

1

T90

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1839	1			T10	180		T11	90		T44	1
auto[StReset]	auto[1]	6	1			T28	1		T76	1		T49	1
auto[StInit]	auto[0]	41	1			T35	1		T116	1		T21	1
auto[StInit]	auto[1]	51	1			T27	1		T131	1		T9	1
auto[StCreatorRootKey]	auto[0]	44	1			T15	1		T38	1		T108	1
auto[StCreatorRootKey]	auto[1]	20	1			T56	1		T127	1		T141	1
auto[StOwnerIntKey]	auto[0]	29	1			T33	1		T64	1		T135	1
auto[StOwnerIntKey]	auto[1]	14	1			T90	1		T133	1		T36	1
auto[StOwnerKey]	auto[0]	20	1			T45	1		T126	1		T49	1
auto[StOwnerKey]	auto[1]	4	1			T18	1		T5	1		T224	1
auto[StDisabled]	auto[0]	409	1			T90	2		T8	1		T44	3
auto[StDisabled]	auto[1]	10	1			T6	1		T128	1		T7	1
auto[StInvalid]	auto[0]	49	1			T14	1		T34	1		T39	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	14	21	60.00	14

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId]]	0	1	1
[auto[StReset]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[StOwnerIntKey]]	[auto[OpGenSwOut]]	0	1	1
[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerKey] , auto[StDisabled]]	[auto[OpDisable]]	--	--	2

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	5	1			T76	1		T49	1		T130	1
auto[StReset]	auto[OpGenSwOut]	1	1			T28	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	21	1			T27	1		T139	1		T140	1
auto[StInit]	auto[OpGenId]	7	1			T225	1		T180	1		T226	1
auto[StInit]	auto[OpGenSwOut]	12	1			T131	1		T9	1		T132	1
auto[StInit]	auto[OpGenHwOut]	11	1			T76	1		T227	1		T228	1
auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T127	1		T181	1		T229	1
auto[StCreatorRootKey]	auto[OpGenId]	2	1			T141	1		T230	1		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T56	1		T37	1		T231	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	7	1			T232	1		T231	1		T233	1
auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T90	1		T74	1		T202	1
auto[StOwnerIntKey]	auto[OpGenId]	1	1			T36	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	6	1			T133	1		T234	1		T203	1
auto[StOwnerKey]	auto[OpAdvance]	1	1			T235	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenId]	1	1			T18	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T224	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T5	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	4	1			T128	1		T46	1		T203	1
auto[StDisabled]	auto[OpGenId]	1	1			T236	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	2	1			T237	1		T235	1		-	-
auto[StDisabled]	auto[OpGenHwOut]	3	1			T6	1		T7	1		T238	1