Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4640

1

T1

8

T3

3

T4

2

auto[1]

540

1

T13

6

T42

1

T20

2

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4640

1

T1

8

T3

3

T4

2

auto[1]

540

1

T13

6

T42

1

T20

2

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4611

1

T1

2

T3

3

T4

2

auto[1]

569

1

T1

6

T19

3

T89

3

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4611

1

T1

2

T3

3

T4

2

auto[1]

569

1

T1

6

T19

3

T89

3

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	424	1			T3	1		T14	1		T15	1
auto[OpGenId]	1062	1			T3	1		T4	1		T14	1
auto[OpGenSwOut]	1138	1			T3	1		T4	1		T14	1
auto[OpGenHwOut]	2501	1			T1	8		T13	11		T14	1
auto[OpDisable]	55	1			T129	1		T90	1		T124	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	424	1			T3	1		T14	1		T15	1
auto[OpGenId]	1062	1			T3	1		T4	1		T14	1
auto[OpGenSwOut]	1138	1			T3	1		T4	1		T14	1
auto[OpGenHwOut]	2501	1			T1	8		T13	11		T14	1
auto[OpDisable]	55	1			T129	1		T90	1		T124	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4632

1

T1

8

T3

2

T4

2

auto[1]

548

1

T3

1

T16

3

T19

2

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4632

1

T1

8

T3

2

T4

2

auto[1]

548

1

T3

1

T16

3

T19

2

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4906

1

T1

8

T3

3

T4

2

auto[1]

274

1

T66

4

T67

16

T71

1

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1808	1			T1	2		T3	1		T4	1
auto[1]	663	1			T1	3		T13	1		T14	2
auto[2]	708	1			T3	2		T13	6		T42	1
auto[3]	665	1			T1	2		T13	1		T16	2
auto[4]	294	1			T1	1		T16	1		T90	2
auto[5]	321	1			T4	1		T13	1		T14	1
auto[6]	344	1			T13	1		T42	1		T89	1
auto[7]	377	1			T15	2		T16	1		T42	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1336	1			T1	1		T4	1		T13	2
clear_one[1]	663	1			T1	3		T13	1		T14	2
clear_one[2]	708	1			T3	2		T13	6		T42	1
clear_one[3]	665	1			T1	2		T13	1		T16	2
clear_none	1808	1			T1	2		T3	1		T4	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	942	1			T13	3		T15	1		T16	1
auto[StInit]	636	1			T1	1		T3	1		T13	1
auto[StCreatorRootKey]	566	1			T1	1		T4	1		T13	1
auto[StOwnerIntKey]	514	1			T1	1		T13	1		T16	1
auto[StOwnerKey]	456	1			T1	1		T3	1		T13	1
auto[StDisabled]	1782	1			T1	4		T3	1		T4	1
auto[StInvalid]	284	1			T14	4		T32	6		T34	2

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	942	1			T13	3		T15	1		T16	1
auto[StInit]	636	1			T1	1		T3	1		T13	1
auto[StCreatorRootKey]	566	1			T1	1		T4	1		T13	1
auto[StOwnerIntKey]	514	1			T1	1		T13	1		T16	1
auto[StOwnerKey]	456	1			T1	1		T3	1		T13	1
auto[StDisabled]	1782	1			T1	4		T3	1		T4	1
auto[StInvalid]	284	1			T14	4		T32	6		T34	2

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[1] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[1] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[4]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[6]]	[auto[StOwnerIntKey]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	4	1			T239	1		T240	1		T241	1
auto[0]	auto[StReset]	auto[OpGenId]	148	1			T19	1		T20	1		T129	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	137	1			T42	1		T110	1		T90	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	243	1			T13	1		T15	1		T16	1
auto[0]	auto[StInit]	auto[OpAdvance]	51	1			T35	1		T56	1		T60	1
auto[0]	auto[StInit]	auto[OpGenId]	95	1			T3	1		T20	1		T90	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	104	1			T31	1		T20	1		T44	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	179	1			T1	1		T89	1		T110	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	16	1			T66	1		T91	1		T36	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	58	1			T208	1		T6	1		T72	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	45	1			T4	1		T42	1		T90	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	81	1			T16	1		T5	1		T213	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	20	1			T91	1		T242	1		T243	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	26	1			T44	1		T124	1		T125	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	29	1			T112	2		T91	1		T6	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	57	1			T16	1		T215	1		T220	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	12	1			T91	1		T244	1		T245	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	17	1			T115	1		T246	1		T133	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	30	1			T66	1		T71	1		T6	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	45	1			T42	1		T214	1		T217	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	22	1			T67	2		T91	1		T245	2
auto[0]	auto[StDisabled]	auto[OpGenId]	71	1			T42	1		T20	1		T67	3
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	66	1			T19	1		T42	1		T66	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	160	1			T1	1		T217	2		T215	2
auto[0]	auto[StDisabled]	auto[OpDisable]	17	1			T125	1		T151	1		T247	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	14	1			T93	1		T248	1		T249	1
auto[0]	auto[StInvalid]	auto[OpGenId]	16	1			T14	1		T34	1		T111	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	26	1			T32	1		T250	1		T98	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	19	1			T251	1		T93	1		T252	1
auto[1]	auto[StReset]	auto[OpGenId]	22	1			T75	1		T253	1		T102	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	24	1			T110	1		T90	1		T65	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	32	1			T211	1		T95	1		T254	1
auto[1]	auto[StInit]	auto[OpAdvance]	8	1			T25	1		T255	1		T237	1
auto[1]	auto[StInit]	auto[OpGenId]	5	1			T44	1		T24	1		T236	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	12	1			T91	1		T105	1		T256	2
auto[1]	auto[StInit]	auto[OpGenHwOut]	16	1			T257	1		T258	1		T259	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T20	1		T260	1		T261	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T45	1		T133	1		T75	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	17	1			T6	2		T125	1		T50	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	41	1			T1	1		T13	1		T214	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T262	1		T263	1		T264	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T265	1		T266	1		T267	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T6	1		T75	1		T266	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	45	1			T113	1		T44	1		T268	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T89	1		T266	1		T77	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	13	1			T266	2		T269	1		T270	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T208	1		T133	1		T271	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	33	1			T16	1		T272	1		T273	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	20	1			T71	1		T112	1		T209	1
auto[1]	auto[StDisabled]	auto[OpGenId]	45	1			T112	1		T6	2		T274	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	61	1			T19	1		T42	1		T89	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	144	1			T1	2		T214	1		T217	1
auto[1]	auto[StDisabled]	auto[OpDisable]	10	1			T124	1		T275	1		T75	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	7	1			T14	1		T276	1		T277	1
auto[1]	auto[StInvalid]	auto[OpGenId]	11	1			T39	1		T95	1		T249	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T32	1		T93	1		T277	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	15	1			T14	1		T32	1		T94	1
auto[2]	auto[StReset]	auto[OpGenId]	19	1			T65	1		T132	1		T134	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	24	1			T110	1		T265	1		T75	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	44	1			T13	1		T220	1		T278	1
auto[2]	auto[StInit]	auto[OpAdvance]	3	1			T279	1		T280	1		T281	1
auto[2]	auto[StInit]	auto[OpGenId]	13	1			T115	1		T124	1		T45	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	11	1			T122	1		T123	1		T45	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	19	1			T42	1		T214	1		T113	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T282	2		T283	1		T259	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T148	1		T74	1		T49	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	20	1			T44	1		T59	1		T284	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	37	1			T220	1		T268	1		T245	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	14	1			T128	1		T126	1		T75	2
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T45	1		T133	1		T266	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T247	1		T285	1		T203	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	42	1			T13	1		T286	1		T273	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T73	1		T287	1		T235	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	8	1			T133	1		T282	1		T288	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	20	1			T3	1		T112	1		T92	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	45	1			T218	1		T57	1		T289	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	30	1			T3	1		T112	1		T6	3
auto[2]	auto[StDisabled]	auto[OpGenId]	36	1			T44	1		T71	1		T6	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	46	1			T211	1		T209	1		T274	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	170	1			T13	4		T214	2		T220	2
auto[2]	auto[StDisabled]	auto[OpDisable]	8	1			T45	1		T133	1		T290	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	12	1			T291	1		T292	1		T252	1
auto[2]	auto[StInvalid]	auto[OpGenId]	12	1			T39	1		T252	1		T293	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	16	1			T34	1		T98	1		T134	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T39	1		T97	1		T95	1
auto[3]	auto[StReset]	auto[OpGenId]	19	1			T39	1		T131	1		T6	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	10	1			T129	1		T265	1		T49	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	47	1			T44	3		T98	1		T6	1
auto[3]	auto[StInit]	auto[OpAdvance]	3	1			T294	1		T295	1		T296	1
auto[3]	auto[StInit]	auto[OpGenId]	10	1			T265	1		T101	1		T102	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	10	1			T39	1		T125	1		T297	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	21	1			T16	1		T54	1		T216	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T72	1		-	-		-	-
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T298	1		T202	1		T262	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	18	1			T299	1		T239	1		T107	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	34	1			T115	1		T300	1		T25	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T90	1		T206	1		T6	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T115	1		T274	1		T265	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T90	1		T208	1		T60	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	47	1			T1	1		T89	1		T59	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T6	1		T301	2		T77	2
auto[3]	auto[StOwnerKey]	auto[OpGenId]	8	1			T46	1		T302	1		T48	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T206	1		T209	1		T6	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	35	1			T13	1		T44	1		T216	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	25	1			T212	1		T92	1		T274	1
auto[3]	auto[StDisabled]	auto[OpGenId]	57	1			T110	1		T212	1		T115	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	44	1			T19	1		T212	1		T207	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	161	1			T1	1		T16	1		T20	1
auto[3]	auto[StDisabled]	auto[OpDisable]	7	1			T6	1		T125	1		T303	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	3	1			T111	1		T304	1		T305	1
auto[3]	auto[StInvalid]	auto[OpGenId]	9	1			T97	1		T251	1		T306	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T32	1		T134	1		T251	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T97	1		T291	1		T307	2
auto[4]	auto[StReset]	auto[OpAdvance]	1	1			T279	1		-	-		-	-
auto[4]	auto[StReset]	auto[OpGenId]	7	1			T299	1		T308	1		T309	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	9	1			T297	1		T310	1		T311	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	20	1			T219	1		T97	1		T312	1
auto[4]	auto[StInit]	auto[OpAdvance]	1	1			T313	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenId]	3	1			T53	1		T279	2		-	-
auto[4]	auto[StInit]	auto[OpGenSwOut]	5	1			T25	1		T48	1		T314	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	8	1			T195	1		T315	1		T316	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T67	2		T317	1		T318	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T125	1		T203	1		T319	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T67	1		T39	1		T133	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	15	1			T217	1		T320	1		T321	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T46	1		T322	1		T224	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T211	1		T6	1		T323	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T67	1		T133	1		T324	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T67	2		T278	1		T325	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T148	1		T45	1		T326	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	5	1			T67	1		T253	1		T262	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T327	1		T310	1		T328	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T1	1		T67	1		T197	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	7	1			T133	1		T75	1		T329	1
auto[4]	auto[StDisabled]	auto[OpGenId]	20	1			T44	1		T59	1		T219	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T90	1		T71	1		T133	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	68	1			T16	1		T215	2		T286	1
auto[4]	auto[StDisabled]	auto[OpDisable]	5	1			T90	1		T6	1		T133	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	4	1			T330	1		T331	1		T332	1
auto[4]	auto[StInvalid]	auto[OpGenId]	4	1			T32	1		T293	1		T331	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T134	1		T308	1		T333	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T111	1		T96	1		T334	1
auto[5]	auto[StReset]	auto[OpGenId]	5	1			T42	1		T206	1		T284	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	10	1			T125	1		T299	1		T335	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	15	1			T45	1		T75	1		T200	1
auto[5]	auto[StInit]	auto[OpAdvance]	4	1			T203	1		T295	1		T336	1
auto[5]	auto[StInit]	auto[OpGenId]	2	1			T6	1		T337	1		-	-
auto[5]	auto[StInit]	auto[OpGenSwOut]	3	1			T75	1		T107	1		T326	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	14	1			T13	1		T220	1		T320	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T24	1		-	-		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T129	1		T102	1		T105	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T133	1		T52	1		T144	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	26	1			T54	1		T91	1		T266	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T283	1		T239	2		T338	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T266	1		T48	1		T50	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T339	1		T237	1		T340	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T214	1		T217	1		T320	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T6	1		T76	1		T341	2
auto[5]	auto[StOwnerKey]	auto[OpGenId]	6	1			T52	1		T239	1		T130	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T6	1		T342	1		T343	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	23	1			T65	1		T44	1		T344	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	14	1			T133	1		T345	1		T346	1
auto[5]	auto[StDisabled]	auto[OpGenId]	29	1			T4	1		T20	1		T206	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	23	1			T207	1		T347	1		T348	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	66	1			T16	1		T268	1		T289	1
auto[5]	auto[StDisabled]	auto[OpDisable]	2	1			T202	1		T235	1		-	-
auto[5]	auto[StInvalid]	auto[OpAdvance]	4	1			T349	1		T306	1		T293	1
auto[5]	auto[StInvalid]	auto[OpGenId]	9	1			T251	1		T306	1		T350	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T14	1		T94	1		T351	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T307	1		T332	1		T352	1
auto[6]	auto[StReset]	auto[OpGenId]	11	1			T20	1		T124	1		T251	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	12	1			T42	1		T97	1		T265	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	24	1			T13	1		T91	1		T353	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T354	1		T224	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	5	1			T314	1		T181	1		T355	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	3	1			T356	1		T357	1		T355	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	7	1			T358	1		T126	1		T265	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T223	1		-	-		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T125	1		T267	1		T53	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T75	1		T359	1		T343	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T278	1		T150	1		T360	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	2	1			T58	1		T314	1		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T65	1		T361	1		T362	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	12	1			T216	1		T363	1		T364	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T25	1		T256	1		T280	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	10	1			T50	1		T256	1		T343	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T281	1		T365	1		T366	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	24	1			T90	1		T215	1		T220	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	16	1			T75	1		T346	1		T367	2
auto[6]	auto[StDisabled]	auto[OpGenId]	34	1			T115	1		T91	1		T151	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T70	1		T75	1		T368	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	74	1			T89	1		T214	1		T66	1
auto[6]	auto[StDisabled]	auto[OpDisable]	3	1			T75	1		T369	1		T370	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	1	1			T249	1		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	5	1			T98	1		T95	1		T371	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T95	1		T291	1		T293	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T32	1		T351	1		T372	1
auto[7]	auto[StReset]	auto[OpGenId]	11	1			T122	1		T29	1		T307	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	15	1			T123	2		T297	1		T75	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	29	1			T129	1		T220	1		T91	1
auto[7]	auto[StInit]	auto[OpAdvance]	3	1			T373	2		T288	1		-	-
auto[7]	auto[StInit]	auto[OpGenId]	4	1			T148	1		T196	1		T374	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	4	1			T15	1		T6	1		T101	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	8	1			T375	1		T290	1		T376	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T15	1		T284	1		T266	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T133	1		T224	1		T377	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T45	1		T262	1		T104	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	24	1			T110	1		T215	1		T286	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T361	1		-	-		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T129	1		T70	1		T218	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T6	1		T45	1		T284	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T6	1		T300	1		T312	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T260	1		-	-		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	6	1			T58	1		T378	1		T236	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T361	2		T102	1		T373	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T286	1		T54	1		T268	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	19	1			T112	1		T379	1		T73	1
auto[7]	auto[StDisabled]	auto[OpGenId]	30	1			T42	1		T6	1		T133	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	35	1			T8	1		T66	3		T327	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	78	1			T16	1		T286	1		T273	1
auto[7]	auto[StDisabled]	auto[OpDisable]	3	1			T129	1		T267	1		T380	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	1	1			T330	1		-	-		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	8	1			T250	1		T199	1		T351	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T94	1		T291	1		T351	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T104	1		T381	1		-	-