Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

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Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1336

1

T1

1

T4

1

T13

2

clear_one[1]

auto[0]

auto[0]

auto[0]

378

1

T13

1

T14

2

T42

1

clear_one[1]

auto[0]

auto[0]

auto[1]

112

1

T16

1

T113

2

T58

1

clear_one[1]

auto[0]

auto[1]

auto[0]

127

1

T1

3

T89

1

T217

1

clear_one[1]

auto[0]

auto[1]

auto[1]

46

1

T19

1

T89

1

T379

1

clear_one[2]

auto[0]

auto[0]

auto[0]

424

1

T3

1

T13

1

T42

1

clear_one[2]

auto[0]

auto[0]

auto[1]

129

1

T3

1

T220

3

T67

1

clear_one[2]

auto[1]

auto[0]

auto[0]

125

1

T13

5

T214

2

T286

2

clear_one[2]

auto[1]

auto[0]

auto[1]

30

1

T24

1

T72

2

T125

1

clear_one[3]

auto[0]

auto[0]

auto[0]

370

1

T16

2

T129

1

T90

2

clear_one[3]

auto[0]

auto[1]

auto[0]

140

1

T1

2

T19

1

T89

1

clear_one[3]

auto[1]

auto[0]

auto[0]

120

1

T13

1

T20

1

T110

1

clear_one[3]

auto[1]

auto[1]

auto[0]

35

1

T92

1

T45

1

T382

1

clear_none

auto[0]

auto[0]

auto[0]

1283

1

T1

1

T3

1

T4

1

clear_none

auto[0]

auto[0]

auto[1]

125

1

T16

2

T90

1

T220

2

clear_none

auto[0]

auto[1]

auto[0]

129

1

T1

1

T217

3

T44

1

clear_none

auto[0]

auto[1]

auto[1]

41

1

T19

1

T67

2

T133

1

clear_none

auto[1]

auto[0]

auto[0]

134

1

T20

1

T214

1

T215

3

clear_none

auto[1]

auto[0]

auto[1]

45

1

T42

1

T213

1

T218

1

clear_none

auto[1]

auto[1]

auto[0]

31

1

T124

1

T246

1

T143

1

clear_none

auto[1]

auto[1]

auto[1]

20

1

T383

1

T51

4

T203

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1264	1			T1	1		T4	1		T13	2
clear_all	auto[1]	72	1			T66	2		T67	7		T91	1
clear_one[1]	auto[0]	626	1			T1	3		T13	1		T14	2
clear_one[1]	auto[1]	37	1			T71	1		T256	1		T384	2
clear_one[2]	auto[0]	683	1			T3	2		T13	6		T42	1
clear_one[2]	auto[1]	25	1			T67	1		T72	2		T284	3
clear_one[3]	auto[0]	624	1			T1	2		T13	1		T16	2
clear_one[3]	auto[1]	41	1			T92	1		T245	3		T72	1
clear_none	auto[0]	1709	1			T1	2		T3	1		T4	1
clear_none	auto[1]	99	1			T66	2		T67	8		T91	5