Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10639

1

T1

7

T2

8

T3

2

auto[Attestation]

7322

1

T1

1

T2

5

T3

10

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2733	1			T2	2		T3	1		T4	3
auto[Aes]	3255	1			T4	3		T13	12		T15	1
auto[Kmac]	3199	1			T1	8		T2	2		T3	3
auto[Otbn]	3142	1			T2	2		T3	3		T4	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7406	1			T1	8		T2	8		T3	8
auto[OpGenId]	5632	1			T2	7		T3	5		T4	2
auto[OpGenSwOut]	5737	1			T2	6		T3	4		T4	6
auto[OpGenHwOut]	6592	1			T1	8		T3	3		T4	2
auto[OpDisable]	132	1			T4	1		T129	1		T90	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10303

1

T1

8

T2

8

T3

9

auto[OpDoneFail]

15196

1

T1

8

T2

13

T3

11

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6080	1			T1	1		T2	6		T3	1
auto[StInit]	3542	1			T1	2		T2	2		T3	5
auto[StCreatorRootKey]	3158	1			T1	2		T2	2		T3	3
auto[StOwnerIntKey]	2691	1			T1	2		T2	2		T3	1
auto[StOwnerKey]	2333	1			T1	2		T2	2		T3	3
auto[StDisabled]	7695	1			T1	7		T2	7		T3	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	337	1			T2	2		T15	1		T19	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	105	1			T206	1		T112	1		T92	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	91	1			T18	1		T90	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	86	1			T20	1		T5	1		T207	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	60	1			T20	1		T208	1		T209	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	224	1			T19	1		T42	1		T110	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	303	1			T19	2		T110	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	98	1			T4	1		T89	1		T20	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	82	1			T18	1		T90	1		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	70	1			T90	1		T67	1		T6	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	58	1			T208	1		T206	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	199	1			T4	1		T19	1		T20	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	312	1			T15	1		T19	1		T42	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	81	1			T90	1		T8	1		T33	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	85	1			T208	1		T67	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	75	1			T31	2		T19	1		T20	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	62	1			T2	1		T90	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	212	1			T19	1		T208	1		T8	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	322	1			T2	1		T42	3		T20	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	92	1			T15	1		T31	1		T20	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	80	1			T2	1		T114	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	55	1			T4	1		T59	1		T210	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	55	1			T20	1		T62	1		T211	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	205	1			T89	1		T20	1		T90	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	68	1			T44	2		T6	1		T125	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	113	1			T89	1		T44	2		T58	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	87	1			T4	1		T212	1		T213	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	71	1			T31	1		T114	1		T71	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	53	1			T211	2		T6	1		T151	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	208	1			T19	1		T89	1		T110	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	53	1			T90	2		T44	1		T6	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	96	1			T89	1		T66	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	94	1			T31	1		T212	1		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	71	1			T18	1		T8	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	67	1			T31	1		T71	2		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	221	1			T4	1		T19	1		T89	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	69	1			T90	4		T44	1		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	98	1			T2	1		T18	1		T90	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	82	1			T18	1		T19	1		T89	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	69	1			T19	1		T8	1		T211	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	59	1			T31	1		T90	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	221	1			T3	2		T19	2		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	53	1			T44	2		T97	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	95	1			T31	1		T20	1		T8	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	96	1			T3	1		T4	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	67	1			T20	2		T69	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	55	1			T3	1		T206	2		T71	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	222	1			T19	2		T90	1		T208	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	263	1			T15	1		T5	1		T32	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	80	1			T14	1		T129	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	72	1			T110	1		T5	1		T90	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	67	1			T19	1		T103	1		T125	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	47	1			T4	1		T31	1		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	184	1			T4	1		T20	1		T208	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	484	1			T13	4		T20	1		T110	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	105	1			T89	2		T214	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	100	1			T214	1		T213	1		T67	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	114	1			T13	1		T214	1		T65	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	89	1			T215	1		T67	1		T216	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	261	1			T13	2		T110	1		T214	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	397	1			T15	1		T20	2		T110	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	93	1			T1	1		T15	1		T217	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	129	1			T1	1		T31	1		T213	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	96	1			T1	1		T5	1		T8	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	78	1			T217	1		T218	1		T219	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	257	1			T1	4		T217	1		T71	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	419	1			T16	4		T42	1		T110	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	111	1			T15	1		T16	1		T66	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	95	1			T14	1		T16	1		T31	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	94	1			T42	1		T220	1		T69	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	83	1			T16	1		T31	2		T113	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	252	1			T3	1		T16	2		T89	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	66	1			T90	1		T44	4		T97	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	77	1			T14	1		T206	1		T108	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	88	1			T129	1		T207	1		T209	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	63	1			T129	1		T208	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	48	1			T3	1		T6	1		T24	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	175	1			T19	1		T89	1		T129	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	47	1			T44	4		T6	1		T133	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	100	1			T13	1		T15	1		T90	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	107	1			T13	1		T33	1		T215	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	86	1			T215	1		T66	1		T69	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	86	1			T13	1		T31	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	264	1			T13	2		T89	1		T20	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	58	1			T90	3		T44	3		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	115	1			T42	1		T208	1		T8	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	110	1			T14	1		T19	1		T89	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	83	1			T89	1		T217	1		T67	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	94	1			T1	1		T90	1		T67	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	264	1			T3	1		T19	1		T89	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	46	1			T44	1		T6	1		T134	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	123	1			T110	1		T90	1		T208	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	103	1			T90	1		T212	1		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	72	1			T16	1		T19	1		T69	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	85	1			T220	1		T218	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	262	1			T16	2		T90	3		T208	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	218	1			T18	1		T20	2		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	685	1			T2	2		T15	1		T19	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	191	1			T18	1		T90	2		T206	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	619	1			T4	2		T19	3		T89	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	198	1			T2	1		T31	2		T20	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	629	1			T15	1		T19	3		T42	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	175	1			T2	1		T4	1		T20	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	634	1			T2	1		T15	1		T31	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	191	1			T4	1		T31	1		T212	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	409	1			T19	1		T89	2		T110	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	213	1			T18	1		T31	2		T212	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	389	1			T4	1		T19	1		T89	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	192	1			T18	1		T31	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	406	1			T2	1		T3	2		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	204	1			T3	2		T4	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	384	1			T31	1		T19	2		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	176	1			T4	1		T31	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	537	1			T4	1		T14	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	284	1			T13	1		T214	2		T213	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	869	1			T13	6		T89	2		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	289	1			T1	2		T31	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	761	1			T1	5		T15	2		T20	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	249	1			T16	2		T31	3		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	805	1			T3	1		T14	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	180	1			T3	1		T129	2		T207	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	337	1			T14	1		T19	1		T89	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	264	1			T13	2		T31	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	426	1			T13	3		T15	1		T89	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	272	1			T1	1		T14	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	452	1			T3	1		T19	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	252	1			T16	1		T19	1		T90	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	439	1			T16	2		T110	1		T90	4