Unified Coverage Report :: Group Instance : attest_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31412

1

T1

19

T2

27

T3

23

auto[1]

293

1

T66

5

T67

7

T71

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31421	1			T1	19		T2	27		T3	23
auto[134217728:268435455]	11	1			T91	1		T72	1		T73	1
auto[268435456:402653183]	5	1			T66	1		T341	1		T412	2
auto[402653184:536870911]	5	1			T77	1		T239	1		T359	1
auto[536870912:671088639]	11	1			T245	1		T72	1		T361	1
auto[671088640:805306367]	11	1			T67	1		T77	1		T279	1
auto[805306368:939524095]	10	1			T301	1		T284	1		T413	1
auto[939524096:1073741823]	7	1			T259	1		T263	1		T414	1
auto[1073741824:1207959551]	3	1			T361	1		T284	1		T282	1
auto[1207959552:1342177279]	8	1			T361	1		T284	1		T77	1
auto[1342177280:1476395007]	9	1			T91	1		T77	1		T282	2
auto[1476395008:1610612735]	10	1			T66	1		T361	1		T284	1
auto[1610612736:1744830463]	8	1			T67	1		T361	1		T413	1
auto[1744830464:1879048191]	6	1			T361	1		T282	1		T415	1
auto[1879048192:2013265919]	17	1			T71	1		T73	1		T361	1
auto[2013265920:2147483647]	11	1			T66	1		T245	1		T361	1
auto[2147483648:2281701375]	9	1			T72	1		T301	1		T239	1
auto[2281701376:2415919103]	9	1			T71	1		T284	1		T396	1
auto[2415919104:2550136831]	10	1			T66	1		T384	1		T263	1
auto[2550136832:2684354559]	8	1			T282	1		T256	1		T416	1
auto[2684354560:2818572287]	16	1			T284	1		T256	3		T373	1
auto[2818572288:2952790015]	9	1			T245	1		T77	1		T282	1
auto[2952790016:3087007743]	8	1			T284	1		T359	1		T263	1
auto[3087007744:3221225471]	8	1			T67	1		T301	1		T284	1
auto[3221225472:3355443199]	8	1			T67	1		T284	1		T259	1
auto[3355443200:3489660927]	12	1			T67	2		T284	2		T283	1
auto[3489660928:3623878655]	12	1			T92	1		T72	1		T282	2
auto[3623878656:3758096383]	11	1			T72	2		T284	1		T282	1
auto[3758096384:3892314111]	7	1			T67	1		T341	1		T417	1
auto[3892314112:4026531839]	6	1			T284	1		T77	2		T373	1
auto[4026531840:4160749567]	11	1			T66	1		T91	1		T245	1
auto[4160749568:4294967295]	8	1			T72	1		T284	1		T282	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31412	1			T1	19		T2	27		T3	23
auto[0:134217727]	auto[1]	9	1			T284	1		T256	1		T384	1
auto[134217728:268435455]	auto[1]	11	1			T91	1		T72	1		T73	1
auto[268435456:402653183]	auto[1]	5	1			T66	1		T341	1		T412	2
auto[402653184:536870911]	auto[1]	5	1			T77	1		T239	1		T359	1
auto[536870912:671088639]	auto[1]	11	1			T245	1		T72	1		T361	1
auto[671088640:805306367]	auto[1]	11	1			T67	1		T77	1		T279	1
auto[805306368:939524095]	auto[1]	10	1			T301	1		T284	1		T413	1
auto[939524096:1073741823]	auto[1]	7	1			T259	1		T263	1		T414	1
auto[1073741824:1207959551]	auto[1]	3	1			T361	1		T284	1		T282	1
auto[1207959552:1342177279]	auto[1]	8	1			T361	1		T284	1		T77	1
auto[1342177280:1476395007]	auto[1]	9	1			T91	1		T77	1		T282	2
auto[1476395008:1610612735]	auto[1]	10	1			T66	1		T361	1		T284	1
auto[1610612736:1744830463]	auto[1]	8	1			T67	1		T361	1		T413	1
auto[1744830464:1879048191]	auto[1]	6	1			T361	1		T282	1		T415	1
auto[1879048192:2013265919]	auto[1]	17	1			T71	1		T73	1		T361	1
auto[2013265920:2147483647]	auto[1]	11	1			T66	1		T245	1		T361	1
auto[2147483648:2281701375]	auto[1]	9	1			T72	1		T301	1		T239	1
auto[2281701376:2415919103]	auto[1]	9	1			T71	1		T284	1		T396	1
auto[2415919104:2550136831]	auto[1]	10	1			T66	1		T384	1		T263	1
auto[2550136832:2684354559]	auto[1]	8	1			T282	1		T256	1		T416	1
auto[2684354560:2818572287]	auto[1]	16	1			T284	1		T256	3		T373	1
auto[2818572288:2952790015]	auto[1]	9	1			T245	1		T77	1		T282	1
auto[2952790016:3087007743]	auto[1]	8	1			T284	1		T359	1		T263	1
auto[3087007744:3221225471]	auto[1]	8	1			T67	1		T301	1		T284	1
auto[3221225472:3355443199]	auto[1]	8	1			T67	1		T284	1		T259	1
auto[3355443200:3489660927]	auto[1]	12	1			T67	2		T284	2		T283	1
auto[3489660928:3623878655]	auto[1]	12	1			T92	1		T72	1		T282	2
auto[3623878656:3758096383]	auto[1]	11	1			T72	2		T284	1		T282	1
auto[3758096384:3892314111]	auto[1]	7	1			T67	1		T341	1		T417	1
auto[3892314112:4026531839]	auto[1]	6	1			T284	1		T77	2		T373	1
auto[4026531840:4160749567]	auto[1]	11	1			T66	1		T91	1		T245	1
auto[4160749568:4294967295]	auto[1]	8	1			T72	1		T284	1		T282	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1512

1

T4

2

T14

4

T15

1

auto[1]

1706

1

T3

4

T4

3

T15

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	90	1			T89	1		T90	1		T206	1
auto[134217728:268435455]	97	1			T64	1		T71	1		T94	1
auto[268435456:402653183]	104	1			T129	1		T5	2		T64	1
auto[402653184:536870911]	98	1			T3	1		T20	1		T206	1
auto[536870912:671088639]	93	1			T90	1		T212	1		T8	1
auto[671088640:805306367]	102	1			T208	1		T66	1		T34	1
auto[805306368:939524095]	100	1			T14	1		T89	1		T44	1
auto[939524096:1073741823]	111	1			T31	1		T39	1		T218	1
auto[1073741824:1207959551]	104	1			T3	1		T14	1		T90	1
auto[1207959552:1342177279]	96	1			T15	1		T89	1		T20	1
auto[1342177280:1476395007]	100	1			T3	1		T18	1		T19	1
auto[1476395008:1610612735]	103	1			T208	1		T65	2		T67	1
auto[1610612736:1744830463]	106	1			T14	1		T112	1		T103	1
auto[1744830464:1879048191]	91	1			T3	1		T18	1		T19	1
auto[1879048192:2013265919]	102	1			T4	1		T32	1		T8	1
auto[2013265920:2147483647]	95	1			T5	1		T58	1		T250	1
auto[2147483648:2281701375]	92	1			T32	1		T64	2		T97	1
auto[2281701376:2415919103]	99	1			T4	2		T15	1		T31	1
auto[2415919104:2550136831]	102	1			T4	1		T19	1		T8	1
auto[2550136832:2684354559]	112	1			T20	2		T90	1		T206	1
auto[2684354560:2818572287]	95	1			T18	2		T90	1		T208	1
auto[2818572288:2952790015]	97	1			T15	1		T212	1		T250	1
auto[2952790016:3087007743]	101	1			T5	1		T90	1		T65	2
auto[3087007744:3221225471]	99	1			T19	1		T5	1		T212	1
auto[3221225472:3355443199]	95	1			T14	1		T212	1		T56	1
auto[3355443200:3489660927]	108	1			T18	1		T20	1		T8	1
auto[3489660928:3623878655]	103	1			T4	1		T89	1		T20	1
auto[3623878656:3758096383]	113	1			T18	1		T20	1		T90	1
auto[3758096384:3892314111]	107	1			T206	1		T34	1		T71	1
auto[3892314112:4026531839]	106	1			T208	1		T212	1		T65	1
auto[4026531840:4160749567]	95	1			T129	1		T32	1		T218	1
auto[4160749568:4294967295]	102	1			T19	1		T5	1		T32	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	50	1			T34	1		T44	1		T6	1
auto[0:134217727]	auto[1]	40	1			T89	1		T90	1		T206	1
auto[134217728:268435455]	auto[0]	43	1			T94	1		T95	1		T46	1
auto[134217728:268435455]	auto[1]	54	1			T64	1		T71	1		T363	1
auto[268435456:402653183]	auto[0]	47	1			T5	1		T34	1		T6	1
auto[268435456:402653183]	auto[1]	57	1			T129	1		T5	1		T64	1
auto[402653184:536870911]	auto[0]	53	1			T20	1		T67	1		T91	1
auto[402653184:536870911]	auto[1]	45	1			T3	1		T206	1		T44	1
auto[536870912:671088639]	auto[0]	36	1			T90	1		T8	1		T39	1
auto[536870912:671088639]	auto[1]	57	1			T212	1		T69	1		T71	1
auto[671088640:805306367]	auto[0]	48	1			T208	1		T34	1		T39	1
auto[671088640:805306367]	auto[1]	54	1			T66	1		T24	1		T134	1
auto[805306368:939524095]	auto[0]	50	1			T14	1		T89	1		T44	1
auto[805306368:939524095]	auto[1]	50	1			T59	1		T112	1		T24	1
auto[939524096:1073741823]	auto[0]	48	1			T31	1		T218	1		T127	1
auto[939524096:1073741823]	auto[1]	63	1			T39	1		T44	2		T112	1
auto[1073741824:1207959551]	auto[0]	46	1			T14	1		T90	1		T206	1
auto[1073741824:1207959551]	auto[1]	58	1			T3	1		T212	1		T112	2
auto[1207959552:1342177279]	auto[0]	44	1			T20	1		T90	1		T59	1
auto[1207959552:1342177279]	auto[1]	52	1			T15	1		T89	1		T212	1
auto[1342177280:1476395007]	auto[0]	43	1			T18	1		T19	1		T90	1
auto[1342177280:1476395007]	auto[1]	57	1			T3	1		T208	1		T64	1
auto[1476395008:1610612735]	auto[0]	50	1			T208	1		T65	1		T71	1
auto[1476395008:1610612735]	auto[1]	53	1			T65	1		T67	1		T98	1
auto[1610612736:1744830463]	auto[0]	51	1			T14	1		T132	1		T243	1
auto[1610612736:1744830463]	auto[1]	55	1			T112	1		T103	1		T134	1
auto[1744830464:1879048191]	auto[0]	45	1			T20	1		T66	1		T44	1
auto[1744830464:1879048191]	auto[1]	46	1			T3	1		T18	1		T19	1
auto[1879048192:2013265919]	auto[0]	51	1			T32	1		T65	1		T44	1
auto[1879048192:2013265919]	auto[1]	51	1			T4	1		T8	1		T67	1
auto[2013265920:2147483647]	auto[0]	42	1			T5	1		T58	1		T6	1
auto[2013265920:2147483647]	auto[1]	53	1			T250	1		T127	1		T211	1
auto[2147483648:2281701375]	auto[0]	44	1			T64	1		T97	1		T24	1
auto[2147483648:2281701375]	auto[1]	48	1			T32	1		T64	1		T9	1
auto[2281701376:2415919103]	auto[0]	44	1			T4	1		T15	1		T218	1
auto[2281701376:2415919103]	auto[1]	55	1			T4	1		T31	1		T129	1
auto[2415919104:2550136831]	auto[0]	48	1			T4	1		T19	1		T8	1
auto[2415919104:2550136831]	auto[1]	54	1			T127	1		T123	1		T45	3
auto[2550136832:2684354559]	auto[0]	56	1			T20	2		T90	1		T206	1
auto[2550136832:2684354559]	auto[1]	56	1			T218	2		T112	1		T209	1
auto[2684354560:2818572287]	auto[0]	43	1			T218	1		T211	1		T6	1
auto[2684354560:2818572287]	auto[1]	52	1			T18	2		T90	1		T208	1
auto[2818572288:2952790015]	auto[0]	51	1			T212	1		T250	1		T219	2
auto[2818572288:2952790015]	auto[1]	46	1			T15	1		T112	1		T6	1
auto[2952790016:3087007743]	auto[0]	52	1			T90	1		T65	2		T6	2
auto[2952790016:3087007743]	auto[1]	49	1			T5	1		T6	2		T122	1
auto[3087007744:3221225471]	auto[0]	48	1			T19	1		T34	1		T211	1
auto[3087007744:3221225471]	auto[1]	51	1			T5	1		T212	1		T39	1
auto[3221225472:3355443199]	auto[0]	39	1			T14	1		T212	1		T56	1
auto[3221225472:3355443199]	auto[1]	56	1			T92	1		T125	1		T45	2
auto[3355443200:3489660927]	auto[0]	48	1			T20	1		T8	1		T218	1
auto[3355443200:3489660927]	auto[1]	60	1			T18	1		T35	1		T39	1
auto[3489660928:3623878655]	auto[0]	50	1			T20	1		T90	1		T213	1
auto[3489660928:3623878655]	auto[1]	53	1			T4	1		T89	1		T39	1
auto[3623878656:3758096383]	auto[0]	53	1			T18	1		T90	1		T32	1
auto[3623878656:3758096383]	auto[1]	60	1			T20	1		T67	1		T56	1
auto[3758096384:3892314111]	auto[0]	51	1			T206	1		T34	1		T71	1
auto[3758096384:3892314111]	auto[1]	56	1			T6	1		T45	1		T243	1
auto[3892314112:4026531839]	auto[0]	50	1			T208	1		T65	1		T219	1
auto[3892314112:4026531839]	auto[1]	56	1			T212	1		T59	1		T94	1
auto[4026531840:4160749567]	auto[0]	42	1			T129	1		T32	1		T218	1
auto[4026531840:4160749567]	auto[1]	53	1			T56	1		T94	1		T246	1
auto[4160749568:4294967295]	auto[0]	46	1			T32	1		T69	1		T92	1
auto[4160749568:4294967295]	auto[1]	56	1			T19	1		T5	1		T6	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1497

1

T4

2

T14

4

T15

2

auto[1]

1721

1

T3

4

T4

3

T18

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T14	1		T32	1		T65	1
auto[134217728:268435455]	98	1			T14	1		T18	1		T20	1
auto[268435456:402653183]	99	1			T4	1		T18	1		T208	1
auto[402653184:536870911]	110	1			T4	1		T35	1		T34	1
auto[536870912:671088639]	115	1			T3	1		T90	1		T208	1
auto[671088640:805306367]	90	1			T90	1		T44	1		T211	1
auto[805306368:939524095]	103	1			T19	1		T129	1		T90	1
auto[939524096:1073741823]	107	1			T31	1		T5	1		T90	1
auto[1073741824:1207959551]	105	1			T15	1		T20	1		T129	1
auto[1207959552:1342177279]	113	1			T3	1		T14	1		T18	2
auto[1342177280:1476395007]	101	1			T15	1		T90	1		T27	1
auto[1476395008:1610612735]	101	1			T4	1		T14	1		T18	1
auto[1610612736:1744830463]	106	1			T4	1		T34	1		T71	1
auto[1744830464:1879048191]	112	1			T19	1		T212	2		T71	1
auto[1879048192:2013265919]	76	1			T39	1		T44	1		T127	1
auto[2013265920:2147483647]	111	1			T18	1		T89	1		T208	1
auto[2147483648:2281701375]	94	1			T20	1		T90	1		T8	1
auto[2281701376:2415919103]	95	1			T129	1		T90	1		T208	1
auto[2415919104:2550136831]	91	1			T5	1		T90	2		T206	1
auto[2550136832:2684354559]	110	1			T206	2		T65	1		T112	1
auto[2684354560:2818572287]	101	1			T19	1		T20	1		T39	1
auto[2818572288:2952790015]	107	1			T19	1		T5	1		T212	1
auto[2952790016:3087007743]	106	1			T90	1		T65	1		T67	1
auto[3087007744:3221225471]	99	1			T89	1		T20	1		T5	1
auto[3221225472:3355443199]	103	1			T4	1		T31	1		T32	1
auto[3355443200:3489660927]	97	1			T5	1		T212	1		T56	1
auto[3489660928:3623878655]	80	1			T89	1		T129	1		T32	1
auto[3623878656:3758096383]	93	1			T19	1		T5	1		T206	1
auto[3758096384:3892314111]	98	1			T20	1		T39	1		T91	1
auto[3892314112:4026531839]	93	1			T3	1		T206	1		T44	1
auto[4026531840:4160749567]	87	1			T89	1		T65	1		T67	1
auto[4160749568:4294967295]	116	1			T3	1		T67	1		T69	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T14	1		T32	1		T65	1
auto[0:134217727]	auto[1]	48	1			T6	1		T134	1		T125	1
auto[134217728:268435455]	auto[0]	52	1			T14	1		T20	1		T8	1
auto[134217728:268435455]	auto[1]	46	1			T18	1		T98	1		T112	1
auto[268435456:402653183]	auto[0]	45	1			T218	1		T131	1		T6	1
auto[268435456:402653183]	auto[1]	54	1			T4	1		T18	1		T208	1
auto[402653184:536870911]	auto[0]	47	1			T34	1		T98	1		T95	1
auto[402653184:536870911]	auto[1]	63	1			T4	1		T35	1		T44	2
auto[536870912:671088639]	auto[0]	52	1			T90	1		T208	1		T219	1
auto[536870912:671088639]	auto[1]	63	1			T3	1		T212	1		T206	1
auto[671088640:805306367]	auto[0]	44	1			T90	1		T211	1		T98	1
auto[671088640:805306367]	auto[1]	46	1			T44	1		T94	2		T103	1
auto[805306368:939524095]	auto[0]	53	1			T19	1		T129	1		T90	1
auto[805306368:939524095]	auto[1]	50	1			T8	1		T64	1		T65	1
auto[939524096:1073741823]	auto[0]	48	1			T90	1		T208	1		T206	1
auto[939524096:1073741823]	auto[1]	59	1			T31	1		T5	1		T64	1
auto[1073741824:1207959551]	auto[0]	49	1			T15	1		T20	1		T67	1
auto[1073741824:1207959551]	auto[1]	56	1			T129	1		T112	2		T209	1
auto[1207959552:1342177279]	auto[0]	60	1			T14	1		T18	1		T20	2
auto[1207959552:1342177279]	auto[1]	53	1			T3	1		T18	1		T67	1
auto[1342177280:1476395007]	auto[0]	45	1			T15	1		T90	1		T27	1
auto[1342177280:1476395007]	auto[1]	56	1			T122	1		T123	1		T45	3
auto[1476395008:1610612735]	auto[0]	40	1			T4	1		T14	1		T18	1
auto[1476395008:1610612735]	auto[1]	61	1			T8	1		T219	1		T91	1
auto[1610612736:1744830463]	auto[0]	50	1			T34	1		T211	1		T6	1
auto[1610612736:1744830463]	auto[1]	56	1			T4	1		T71	1		T128	1
auto[1744830464:1879048191]	auto[0]	43	1			T19	1		T212	1		T132	1
auto[1744830464:1879048191]	auto[1]	69	1			T212	1		T71	1		T98	1
auto[1879048192:2013265919]	auto[0]	32	1			T44	1		T127	1		T97	1
auto[1879048192:2013265919]	auto[1]	44	1			T39	1		T124	1		T209	1
auto[2013265920:2147483647]	auto[0]	47	1			T208	1		T64	1		T56	1
auto[2013265920:2147483647]	auto[1]	64	1			T18	1		T89	1		T212	1
auto[2147483648:2281701375]	auto[0]	40	1			T90	1		T213	1		T58	1
auto[2147483648:2281701375]	auto[1]	54	1			T20	1		T8	1		T94	1
auto[2281701376:2415919103]	auto[0]	48	1			T208	1		T127	1		T219	1
auto[2281701376:2415919103]	auto[1]	47	1			T129	1		T90	1		T59	1
auto[2415919104:2550136831]	auto[0]	39	1			T27	1		T219	1		T45	1
auto[2415919104:2550136831]	auto[1]	52	1			T5	1		T90	2		T206	1
auto[2550136832:2684354559]	auto[0]	34	1			T206	1		T6	1		T45	1
auto[2550136832:2684354559]	auto[1]	76	1			T206	1		T65	1		T112	1
auto[2684354560:2818572287]	auto[0]	48	1			T218	1		T250	1		T95	1
auto[2684354560:2818572287]	auto[1]	53	1			T19	1		T20	1		T39	1
auto[2818572288:2952790015]	auto[0]	50	1			T19	1		T5	1		T212	1
auto[2818572288:2952790015]	auto[1]	57	1			T59	1		T219	1		T94	1
auto[2952790016:3087007743]	auto[0]	58	1			T90	1		T65	1		T67	1
auto[2952790016:3087007743]	auto[1]	48	1			T39	1		T218	1		T127	1
auto[3087007744:3221225471]	auto[0]	47	1			T20	1		T5	1		T34	1
auto[3087007744:3221225471]	auto[1]	52	1			T89	1		T212	1		T34	1
auto[3221225472:3355443199]	auto[0]	47	1			T4	1		T31	1		T32	1
auto[3221225472:3355443199]	auto[1]	56	1			T91	1		T131	1		T6	1
auto[3355443200:3489660927]	auto[0]	42	1			T212	1		T91	1		T209	1
auto[3355443200:3489660927]	auto[1]	55	1			T5	1		T56	1		T6	1
auto[3489660928:3623878655]	auto[0]	38	1			T32	1		T65	1		T34	1
auto[3489660928:3623878655]	auto[1]	42	1			T89	1		T129	1		T64	1
auto[3623878656:3758096383]	auto[0]	42	1			T19	1		T5	1		T206	1
auto[3623878656:3758096383]	auto[1]	51	1			T69	1		T379	2		T45	1
auto[3758096384:3892314111]	auto[0]	60	1			T20	1		T39	1		T91	1
auto[3758096384:3892314111]	auto[1]	38	1			T6	1		T274	1		T125	1
auto[3892314112:4026531839]	auto[0]	43	1			T44	1		T250	1		T7	1
auto[3892314112:4026531839]	auto[1]	50	1			T3	1		T206	1		T250	1
auto[4026531840:4160749567]	auto[0]	44	1			T89	1		T39	1		T209	1
auto[4026531840:4160749567]	auto[1]	43	1			T65	1		T67	1		T39	1
auto[4160749568:4294967295]	auto[0]	57	1			T69	1		T97	2		T245	1
auto[4160749568:4294967295]	auto[1]	59	1			T3	1		T67	1		T39	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1460

1

T4

2

T14

4

T15

2

auto[1]

1759

1

T3

4

T4

3

T15

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T5	1		T212	1		T206	1
auto[134217728:268435455]	107	1			T4	1		T19	1		T90	1
auto[268435456:402653183]	105	1			T20	2		T8	1		T66	1
auto[402653184:536870911]	85	1			T32	1		T64	1		T65	2
auto[536870912:671088639]	97	1			T3	1		T18	2		T20	1
auto[671088640:805306367]	78	1			T67	1		T218	2		T94	1
auto[805306368:939524095]	88	1			T19	1		T89	1		T206	1
auto[939524096:1073741823]	107	1			T14	1		T212	1		T6	3
auto[1073741824:1207959551]	101	1			T14	1		T129	1		T66	1
auto[1207959552:1342177279]	105	1			T90	2		T32	1		T212	1
auto[1342177280:1476395007]	104	1			T3	1		T5	1		T206	2
auto[1476395008:1610612735]	92	1			T69	1		T6	1		T379	1
auto[1610612736:1744830463]	91	1			T15	1		T31	1		T5	2
auto[1744830464:1879048191]	120	1			T3	1		T4	1		T14	1
auto[1879048192:2013265919]	104	1			T31	1		T32	1		T44	1
auto[2013265920:2147483647]	110	1			T20	1		T35	1		T34	1
auto[2147483648:2281701375]	81	1			T20	2		T212	1		T8	1
auto[2281701376:2415919103]	110	1			T19	1		T90	1		T208	1
auto[2415919104:2550136831]	85	1			T3	1		T18	1		T65	1
auto[2550136832:2684354559]	86	1			T15	1		T18	1		T5	1
auto[2684354560:2818572287]	127	1			T90	1		T206	1		T218	1
auto[2818572288:2952790015]	109	1			T89	1		T58	1		T94	1
auto[2952790016:3087007743]	88	1			T89	1		T32	2		T27	1
auto[3087007744:3221225471]	114	1			T19	1		T65	1		T250	1
auto[3221225472:3355443199]	106	1			T14	1		T20	1		T208	1
auto[3355443200:3489660927]	113	1			T90	1		T67	1		T39	1
auto[3489660928:3623878655]	100	1			T4	1		T206	1		T59	1
auto[3623878656:3758096383]	101	1			T4	1		T15	1		T18	1
auto[3758096384:3892314111]	102	1			T4	1		T129	1		T124	2
auto[3892314112:4026531839]	95	1			T20	1		T129	1		T65	1
auto[4026531840:4160749567]	97	1			T18	1		T89	1		T90	2
auto[4160749568:4294967295]	108	1			T19	1		T90	2		T8	1