Unified Coverage Report :: Group Instance : salt_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2791

1

T3

4

T4

5

T14

4

auto[1]

307

1

T66

5

T67

11

T71

11

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T19	1		T212	2		T44	1
auto[134217728:268435455]	84	1			T212	1		T65	1		T67	1
auto[268435456:402653183]	88	1			T18	1		T8	1		T67	1
auto[402653184:536870911]	93	1			T4	1		T14	1		T18	1
auto[536870912:671088639]	89	1			T4	1		T31	1		T20	1
auto[671088640:805306367]	87	1			T129	1		T67	1		T44	1
auto[805306368:939524095]	101	1			T90	1		T69	1		T219	1
auto[939524096:1073741823]	112	1			T3	1		T8	1		T65	1
auto[1073741824:1207959551]	82	1			T64	1		T65	1		T66	2
auto[1207959552:1342177279]	100	1			T212	1		T39	1		T218	1
auto[1342177280:1476395007]	117	1			T67	1		T44	1		T91	1
auto[1476395008:1610612735]	102	1			T90	1		T206	1		T64	1
auto[1610612736:1744830463]	108	1			T31	1		T20	1		T208	1
auto[1744830464:1879048191]	83	1			T19	1		T129	1		T212	1
auto[1879048192:2013265919]	110	1			T4	2		T20	1		T208	1
auto[2013265920:2147483647]	106	1			T20	1		T211	1		T94	1
auto[2147483648:2281701375]	83	1			T14	1		T5	1		T208	1
auto[2281701376:2415919103]	97	1			T89	1		T90	1		T32	1
auto[2415919104:2550136831]	94	1			T19	1		T20	2		T208	1
auto[2550136832:2684354559]	93	1			T15	1		T69	1		T71	2
auto[2684354560:2818572287]	93	1			T89	1		T213	1		T206	1
auto[2818572288:2952790015]	88	1			T4	1		T27	1		T71	2
auto[2952790016:3087007743]	107	1			T15	1		T89	1		T90	1
auto[3087007744:3221225471]	88	1			T14	1		T32	1		T67	1
auto[3221225472:3355443199]	90	1			T18	1		T20	1		T90	1
auto[3355443200:3489660927]	106	1			T14	1		T19	1		T218	2
auto[3489660928:3623878655]	97	1			T5	1		T66	1		T67	1
auto[3623878656:3758096383]	109	1			T3	1		T212	1		T206	1
auto[3758096384:3892314111]	90	1			T19	1		T67	1		T39	1
auto[3892314112:4026531839]	90	1			T89	1		T218	1		T112	1
auto[4026531840:4160749567]	103	1			T3	1		T129	1		T32	1
auto[4160749568:4294967295]	104	1			T3	1		T5	1		T90	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	99	1			T19	1		T212	2		T44	1
auto[0:134217727]	auto[1]	5	1			T72	1		T284	1		T412	1
auto[134217728:268435455]	auto[0]	76	1			T212	1		T65	1		T39	1
auto[134217728:268435455]	auto[1]	8	1			T67	1		T361	1		T77	1
auto[268435456:402653183]	auto[0]	81	1			T18	1		T8	1		T67	1
auto[268435456:402653183]	auto[1]	7	1			T71	1		T361	1		T77	1
auto[402653184:536870911]	auto[0]	86	1			T4	1		T14	1		T18	1
auto[402653184:536870911]	auto[1]	7	1			T71	1		T419	1		T414	1
auto[536870912:671088639]	auto[0]	81	1			T4	1		T31	1		T20	1
auto[536870912:671088639]	auto[1]	8	1			T91	1		T301	1		T413	1
auto[671088640:805306367]	auto[0]	81	1			T129	1		T44	1		T94	1
auto[671088640:805306367]	auto[1]	6	1			T67	1		T361	1		T259	1
auto[805306368:939524095]	auto[0]	93	1			T90	1		T69	1		T219	1
auto[805306368:939524095]	auto[1]	8	1			T284	1		T269	1		T396	1
auto[939524096:1073741823]	auto[0]	98	1			T3	1		T8	1		T65	1
auto[939524096:1073741823]	auto[1]	14	1			T67	1		T92	1		T361	1
auto[1073741824:1207959551]	auto[0]	69	1			T64	1		T65	1		T59	1
auto[1073741824:1207959551]	auto[1]	13	1			T66	2		T282	1		T239	1
auto[1207959552:1342177279]	auto[0]	89	1			T212	1		T39	1		T218	1
auto[1207959552:1342177279]	auto[1]	11	1			T361	1		T284	1		T259	1
auto[1342177280:1476395007]	auto[0]	102	1			T44	1		T6	3		T245	1
auto[1342177280:1476395007]	auto[1]	15	1			T67	1		T91	1		T282	1
auto[1476395008:1610612735]	auto[0]	98	1			T90	1		T206	1		T64	1
auto[1476395008:1610612735]	auto[1]	4	1			T245	1		T367	1		T279	1
auto[1610612736:1744830463]	auto[0]	100	1			T31	1		T20	1		T208	1
auto[1610612736:1744830463]	auto[1]	8	1			T67	1		T77	1		T419	3
auto[1744830464:1879048191]	auto[0]	76	1			T19	1		T129	1		T212	1
auto[1744830464:1879048191]	auto[1]	7	1			T67	1		T282	2		T263	1
auto[1879048192:2013265919]	auto[0]	102	1			T4	2		T20	1		T208	1
auto[1879048192:2013265919]	auto[1]	8	1			T66	1		T67	1		T71	1
auto[2013265920:2147483647]	auto[0]	94	1			T20	1		T211	1		T94	1
auto[2013265920:2147483647]	auto[1]	12	1			T284	1		T239	1		T384	1
auto[2147483648:2281701375]	auto[0]	75	1			T14	1		T5	1		T208	1
auto[2147483648:2281701375]	auto[1]	8	1			T284	1		T77	1		T256	1
auto[2281701376:2415919103]	auto[0]	84	1			T89	1		T90	1		T32	1
auto[2281701376:2415919103]	auto[1]	13	1			T66	1		T91	1		T301	1
auto[2415919104:2550136831]	auto[0]	84	1			T19	1		T20	2		T208	1
auto[2415919104:2550136831]	auto[1]	10	1			T71	1		T282	2		T419	1
auto[2550136832:2684354559]	auto[0]	81	1			T15	1		T69	1		T71	1
auto[2550136832:2684354559]	auto[1]	12	1			T71	1		T72	1		T239	1
auto[2684354560:2818572287]	auto[0]	85	1			T89	1		T213	1		T206	1
auto[2684354560:2818572287]	auto[1]	8	1			T245	2		T282	1		T263	1
auto[2818572288:2952790015]	auto[0]	81	1			T4	1		T27	1		T250	1
auto[2818572288:2952790015]	auto[1]	7	1			T71	2		T282	1		T259	1
auto[2952790016:3087007743]	auto[0]	97	1			T15	1		T89	1		T90	1
auto[2952790016:3087007743]	auto[1]	10	1			T67	1		T245	1		T415	1
auto[3087007744:3221225471]	auto[0]	80	1			T14	1		T32	1		T67	1
auto[3087007744:3221225471]	auto[1]	8	1			T361	1		T77	1		T282	1
auto[3221225472:3355443199]	auto[0]	81	1			T18	1		T20	1		T90	1
auto[3221225472:3355443199]	auto[1]	9	1			T301	1		T284	1		T77	1
auto[3355443200:3489660927]	auto[0]	92	1			T14	1		T19	1		T218	2
auto[3355443200:3489660927]	auto[1]	14	1			T91	2		T284	2		T259	1
auto[3489660928:3623878655]	auto[0]	86	1			T5	1		T66	1		T39	2
auto[3489660928:3623878655]	auto[1]	11	1			T67	1		T92	1		T413	1
auto[3623878656:3758096383]	auto[0]	93	1			T3	1		T212	1		T206	1
auto[3623878656:3758096383]	auto[1]	16	1			T71	1		T361	1		T282	1
auto[3758096384:3892314111]	auto[0]	82	1			T19	1		T39	1		T92	1
auto[3758096384:3892314111]	auto[1]	8	1			T67	1		T361	1		T373	1
auto[3892314112:4026531839]	auto[0]	83	1			T89	1		T218	1		T112	1
auto[3892314112:4026531839]	auto[1]	7	1			T416	2		T421	2		T422	1
auto[4026531840:4160749567]	auto[0]	89	1			T3	1		T129	1		T32	1
auto[4026531840:4160749567]	auto[1]	14	1			T66	1		T71	1		T361	1
auto[4160749568:4294967295]	auto[0]	93	1			T3	1		T5	1		T90	1
auto[4160749568:4294967295]	auto[1]	11	1			T67	1		T71	2		T256	1