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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1499 1 T4 2 T14 4 T15 2
auto[1] 1720 1 T3 4 T4 3 T15 1


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 97 1 T31 1 T129 1 T90 2
auto[134217728:268435455] 97 1 T20 2 T5 1 T90 1
auto[268435456:402653183] 75 1 T32 1 T8 1 T206 1
auto[402653184:536870911] 103 1 T8 1 T206 1 T71 1
auto[536870912:671088639] 95 1 T14 1 T15 1 T18 1
auto[671088640:805306367] 101 1 T4 1 T18 1 T5 1
auto[805306368:939524095] 95 1 T67 1 T39 1 T94 1
auto[939524096:1073741823] 103 1 T5 1 T32 1 T212 1
auto[1073741824:1207959551] 119 1 T15 1 T20 1 T90 1
auto[1207959552:1342177279] 94 1 T90 1 T212 1 T206 1
auto[1342177280:1476395007] 106 1 T3 1 T4 1 T19 1
auto[1476395008:1610612735] 87 1 T20 1 T67 1 T98 1
auto[1610612736:1744830463] 97 1 T3 1 T206 1 T67 1
auto[1744830464:1879048191] 93 1 T19 1 T65 1 T218 1
auto[1879048192:2013265919] 93 1 T3 1 T90 1 T213 1
auto[2013265920:2147483647] 102 1 T14 1 T89 1 T39 1
auto[2147483648:2281701375] 107 1 T14 1 T208 1 T65 1
auto[2281701376:2415919103] 96 1 T19 1 T89 1 T208 1
auto[2415919104:2550136831] 96 1 T20 1 T129 1 T8 1
auto[2550136832:2684354559] 94 1 T20 1 T5 1 T34 1
auto[2684354560:2818572287] 95 1 T4 1 T212 1 T64 1
auto[2818572288:2952790015] 99 1 T3 1 T129 1 T8 1
auto[2952790016:3087007743] 113 1 T19 1 T208 1 T64 1
auto[3087007744:3221225471] 89 1 T14 1 T18 1 T112 1
auto[3221225472:3355443199] 116 1 T208 2 T218 1 T44 1
auto[3355443200:3489660927] 113 1 T18 1 T90 1 T64 1
auto[3489660928:3623878655] 96 1 T4 1 T90 1 T32 1
auto[3623878656:3758096383] 107 1 T4 1 T18 1 T5 1
auto[3758096384:3892314111] 107 1 T18 1 T89 2 T20 1
auto[3892314112:4026531839] 112 1 T15 1 T19 1 T20 1
auto[4026531840:4160749567] 104 1 T212 1 T65 1 T250 1
auto[4160749568:4294967295] 118 1 T32 1 T64 1 T44 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 42 1 T31 1 T44 1 T91 1
auto[0:134217727] auto[1] 55 1 T129 1 T90 2 T209 1
auto[134217728:268435455] auto[0] 43 1 T20 2 T5 1 T90 1
auto[134217728:268435455] auto[1] 54 1 T206 1 T112 1 T21 1
auto[268435456:402653183] auto[0] 35 1 T64 1 T131 1 T103 1
auto[268435456:402653183] auto[1] 40 1 T32 1 T8 1 T206 1
auto[402653184:536870911] auto[0] 46 1 T8 1 T71 1 T97 2
auto[402653184:536870911] auto[1] 57 1 T206 1 T6 1 T132 1
auto[536870912:671088639] auto[0] 38 1 T14 1 T15 1 T97 2
auto[536870912:671088639] auto[1] 57 1 T18 1 T31 1 T129 1
auto[671088640:805306367] auto[0] 46 1 T5 1 T32 1 T66 1
auto[671088640:805306367] auto[1] 55 1 T4 1 T18 1 T39 1
auto[805306368:939524095] auto[0] 47 1 T67 1 T39 1 T94 1
auto[805306368:939524095] auto[1] 48 1 T112 1 T6 2 T363 1
auto[939524096:1073741823] auto[0] 51 1 T32 1 T59 1 T291 1
auto[939524096:1073741823] auto[1] 52 1 T5 1 T212 1 T112 1
auto[1073741824:1207959551] auto[0] 65 1 T15 1 T20 1 T90 1
auto[1073741824:1207959551] auto[1] 54 1 T98 1 T112 1 T6 1
auto[1207959552:1342177279] auto[0] 48 1 T90 1 T212 1 T71 1
auto[1207959552:1342177279] auto[1] 46 1 T206 1 T65 1 T127 1
auto[1342177280:1476395007] auto[0] 43 1 T4 1 T64 1 T65 1
auto[1342177280:1476395007] auto[1] 63 1 T3 1 T19 1 T5 1
auto[1476395008:1610612735] auto[0] 39 1 T20 1 T97 1 T6 1
auto[1476395008:1610612735] auto[1] 48 1 T67 1 T98 1 T94 1
auto[1610612736:1744830463] auto[0] 45 1 T250 1 T209 1 T132 1
auto[1610612736:1744830463] auto[1] 52 1 T3 1 T206 1 T67 1
auto[1744830464:1879048191] auto[0] 36 1 T19 1 T65 1 T245 1
auto[1744830464:1879048191] auto[1] 57 1 T218 1 T71 1 T6 1
auto[1879048192:2013265919] auto[0] 46 1 T90 1 T213 1 T34 1
auto[1879048192:2013265919] auto[1] 47 1 T3 1 T218 1 T44 1
auto[2013265920:2147483647] auto[0] 53 1 T14 1 T44 1 T91 1
auto[2013265920:2147483647] auto[1] 49 1 T89 1 T39 1 T91 1
auto[2147483648:2281701375] auto[0] 49 1 T14 1 T208 1 T250 1
auto[2147483648:2281701375] auto[1] 58 1 T65 1 T98 1 T94 1
auto[2281701376:2415919103] auto[0] 45 1 T19 1 T212 2 T65 1
auto[2281701376:2415919103] auto[1] 51 1 T89 1 T208 1 T69 1
auto[2415919104:2550136831] auto[0] 47 1 T20 1 T206 1 T58 1
auto[2415919104:2550136831] auto[1] 49 1 T129 1 T8 1 T39 1
auto[2550136832:2684354559] auto[0] 43 1 T20 1 T5 1 T39 1
auto[2550136832:2684354559] auto[1] 51 1 T34 1 T67 1 T44 1
auto[2684354560:2818572287] auto[0] 41 1 T4 1 T219 1 T45 1
auto[2684354560:2818572287] auto[1] 54 1 T212 1 T64 1 T219 1
auto[2818572288:2952790015] auto[0] 45 1 T129 1 T8 1 T206 1
auto[2818572288:2952790015] auto[1] 54 1 T3 1 T67 1 T56 1
auto[2952790016:3087007743] auto[0] 55 1 T208 1 T27 1 T219 1
auto[2952790016:3087007743] auto[1] 58 1 T19 1 T64 1 T39 1
auto[3087007744:3221225471] auto[0] 36 1 T14 1 T6 1 T132 1
auto[3087007744:3221225471] auto[1] 53 1 T18 1 T112 1 T6 3
auto[3221225472:3355443199] auto[0] 53 1 T208 2 T218 1 T24 1
auto[3221225472:3355443199] auto[1] 63 1 T44 1 T92 1 T245 1
auto[3355443200:3489660927] auto[0] 62 1 T34 2 T44 1 T6 1
auto[3355443200:3489660927] auto[1] 51 1 T18 1 T90 1 T64 1
auto[3489660928:3623878655] auto[0] 51 1 T90 1 T32 1 T58 1
auto[3489660928:3623878655] auto[1] 45 1 T4 1 T127 1 T245 1
auto[3623878656:3758096383] auto[0] 50 1 T90 1 T69 1 T39 1
auto[3623878656:3758096383] auto[1] 57 1 T4 1 T18 1 T5 1
auto[3758096384:3892314111] auto[0] 51 1 T18 1 T89 1 T20 1
auto[3758096384:3892314111] auto[1] 56 1 T89 1 T8 1 T218 1
auto[3892314112:4026531839] auto[0] 45 1 T251 1 T382 1 T418 1
auto[3892314112:4026531839] auto[1] 67 1 T15 1 T19 1 T20 1
auto[4026531840:4160749567] auto[0] 53 1 T65 1 T250 1 T127 1
auto[4026531840:4160749567] auto[1] 51 1 T212 1 T6 2 T25 1
auto[4160749568:4294967295] auto[0] 50 1 T32 1 T64 1 T131 1
auto[4160749568:4294967295] auto[1] 68 1 T44 1 T71 1 T112 1

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