Unified Coverage Report :: Group Instance : attest_sw_binding_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1493

1

T4

2

T14

4

T15

1

auto[1]

1725

1

T3

4

T4

3

T15

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T18	1		T20	1		T206	1
auto[134217728:268435455]	97	1			T31	1		T129	1		T90	1
auto[268435456:402653183]	109	1			T20	1		T5	1		T90	1
auto[402653184:536870911]	98	1			T19	1		T8	1		T65	1
auto[536870912:671088639]	86	1			T15	1		T44	1		T219	2
auto[671088640:805306367]	99	1			T212	1		T64	1		T44	1
auto[805306368:939524095]	107	1			T4	1		T66	1		T218	1
auto[939524096:1073741823]	98	1			T14	1		T8	1		T218	1
auto[1073741824:1207959551]	107	1			T14	1		T89	1		T8	1
auto[1207959552:1342177279]	79	1			T89	1		T20	1		T5	1
auto[1342177280:1476395007]	113	1			T3	1		T18	1		T129	1
auto[1476395008:1610612735]	100	1			T32	1		T65	1		T69	1
auto[1610612736:1744830463]	111	1			T4	2		T206	1		T67	1
auto[1744830464:1879048191]	97	1			T90	1		T212	1		T67	1
auto[1879048192:2013265919]	92	1			T5	1		T34	1		T44	2
auto[2013265920:2147483647]	88	1			T206	1		T112	1		T91	2
auto[2147483648:2281701375]	98	1			T32	1		T8	1		T64	1
auto[2281701376:2415919103]	100	1			T208	1		T206	1		T39	1
auto[2415919104:2550136831]	95	1			T15	1		T18	1		T19	1
auto[2550136832:2684354559]	99	1			T20	1		T5	1		T64	1
auto[2684354560:2818572287]	105	1			T90	1		T218	3		T127	1
auto[2818572288:2952790015]	114	1			T89	1		T8	1		T206	1
auto[2952790016:3087007743]	103	1			T14	1		T18	1		T64	1
auto[3087007744:3221225471]	100	1			T4	1		T18	2		T90	1
auto[3221225472:3355443199]	112	1			T129	1		T32	1		T219	1
auto[3355443200:3489660927]	116	1			T19	1		T20	1		T129	1
auto[3489660928:3623878655]	99	1			T4	1		T212	1		T56	1
auto[3623878656:3758096383]	96	1			T3	3		T14	1		T19	1
auto[3758096384:3892314111]	85	1			T20	2		T90	1		T32	1
auto[3892314112:4026531839]	89	1			T90	1		T212	2		T67	1
auto[4026531840:4160749567]	115	1			T15	1		T31	1		T19	1
auto[4160749568:4294967295]	103	1			T5	1		T35	1		T65	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	61	1			T20	1		T206	1		T34	1
auto[0:134217727]	auto[1]	47	1			T18	1		T44	1		T59	1
auto[134217728:268435455]	auto[0]	46	1			T31	1		T65	1		T127	1
auto[134217728:268435455]	auto[1]	51	1			T129	1		T90	1		T218	1
auto[268435456:402653183]	auto[0]	55	1			T20	1		T5	1		T90	1
auto[268435456:402653183]	auto[1]	54	1			T66	1		T98	1		T242	1
auto[402653184:536870911]	auto[0]	52	1			T8	1		T34	1		T9	1
auto[402653184:536870911]	auto[1]	46	1			T19	1		T65	1		T67	1
auto[536870912:671088639]	auto[0]	45	1			T44	1		T219	1		T6	1
auto[536870912:671088639]	auto[1]	41	1			T15	1		T219	1		T91	1
auto[671088640:805306367]	auto[0]	39	1			T64	1		T58	1		T98	1
auto[671088640:805306367]	auto[1]	60	1			T212	1		T44	1		T91	1
auto[805306368:939524095]	auto[0]	51	1			T66	1		T218	1		T211	1
auto[805306368:939524095]	auto[1]	56	1			T4	1		T112	1		T103	1
auto[939524096:1073741823]	auto[0]	38	1			T14	1		T97	1		T6	1
auto[939524096:1073741823]	auto[1]	60	1			T8	1		T218	1		T112	1
auto[1073741824:1207959551]	auto[0]	52	1			T14	1		T8	1		T95	1
auto[1073741824:1207959551]	auto[1]	55	1			T89	1		T39	1		T91	1
auto[1207959552:1342177279]	auto[0]	29	1			T89	1		T20	1		T208	1
auto[1207959552:1342177279]	auto[1]	50	1			T5	1		T32	1		T59	1
auto[1342177280:1476395007]	auto[0]	53	1			T208	1		T212	1		T6	1
auto[1342177280:1476395007]	auto[1]	60	1			T3	1		T18	1		T129	1
auto[1476395008:1610612735]	auto[0]	40	1			T32	1		T65	1		T69	1
auto[1476395008:1610612735]	auto[1]	60	1			T44	1		T112	1		T92	1
auto[1610612736:1744830463]	auto[0]	48	1			T4	1		T206	1		T211	1
auto[1610612736:1744830463]	auto[1]	63	1			T4	1		T67	1		T94	1
auto[1744830464:1879048191]	auto[0]	43	1			T56	1		T25	1		T75	1
auto[1744830464:1879048191]	auto[1]	54	1			T90	1		T212	1		T67	1
auto[1879048192:2013265919]	auto[0]	46	1			T44	1		T97	2		T72	1
auto[1879048192:2013265919]	auto[1]	46	1			T5	1		T34	1		T44	1
auto[2013265920:2147483647]	auto[0]	43	1			T91	1		T209	1		T148	1
auto[2013265920:2147483647]	auto[1]	45	1			T206	1		T112	1		T91	1
auto[2147483648:2281701375]	auto[0]	41	1			T32	1		T8	1		T39	1
auto[2147483648:2281701375]	auto[1]	57	1			T64	1		T112	2		T6	1
auto[2281701376:2415919103]	auto[0]	48	1			T208	1		T56	1		T219	1
auto[2281701376:2415919103]	auto[1]	52	1			T206	1		T39	1		T59	1
auto[2415919104:2550136831]	auto[0]	45	1			T15	1		T19	1		T90	1
auto[2415919104:2550136831]	auto[1]	50	1			T18	1		T6	1		T379	1
auto[2550136832:2684354559]	auto[0]	49	1			T71	1		T127	1		T219	1
auto[2550136832:2684354559]	auto[1]	50	1			T20	1		T5	1		T64	1
auto[2684354560:2818572287]	auto[0]	50	1			T127	1		T6	1		T125	1
auto[2684354560:2818572287]	auto[1]	55	1			T90	1		T218	3		T92	1
auto[2818572288:2952790015]	auto[0]	41	1			T206	1		T58	1		T250	1
auto[2818572288:2952790015]	auto[1]	73	1			T89	1		T8	1		T65	1
auto[2952790016:3087007743]	auto[0]	54	1			T14	1		T64	1		T34	1
auto[2952790016:3087007743]	auto[1]	49	1			T18	1		T209	1		T6	2
auto[3087007744:3221225471]	auto[0]	48	1			T4	1		T18	1		T90	1
auto[3087007744:3221225471]	auto[1]	52	1			T18	1		T67	1		T92	1
auto[3221225472:3355443199]	auto[0]	49	1			T129	1		T32	1		T219	1
auto[3221225472:3355443199]	auto[1]	63	1			T72	1		T151	1		T361	1
auto[3355443200:3489660927]	auto[0]	51	1			T20	1		T90	1		T208	1
auto[3355443200:3489660927]	auto[1]	65	1			T19	1		T129	1		T90	1
auto[3489660928:3623878655]	auto[0]	46	1			T212	1		T219	1		T6	2
auto[3489660928:3623878655]	auto[1]	53	1			T4	1		T56	1		T98	1
auto[3623878656:3758096383]	auto[0]	48	1			T14	1		T19	1		T5	1
auto[3623878656:3758096383]	auto[1]	48	1			T3	3		T206	1		T39	1
auto[3758096384:3892314111]	auto[0]	44	1			T20	2		T90	1		T32	1
auto[3758096384:3892314111]	auto[1]	41	1			T6	2		T134	1		T95	1
auto[3892314112:4026531839]	auto[0]	47	1			T90	1		T212	1		T67	1
auto[3892314112:4026531839]	auto[1]	42	1			T212	1		T71	2		T250	1
auto[4026531840:4160749567]	auto[0]	43	1			T31	1		T20	1		T6	1
auto[4026531840:4160749567]	auto[1]	72	1			T15	1		T19	1		T89	1
auto[4160749568:4294967295]	auto[0]	48	1			T5	1		T65	1		T250	1
auto[4160749568:4294967295]	auto[1]	55	1			T35	1		T69	1		T39	1