SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
75.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 2 | 6 | 75.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
invalid_hw_input_cp | 8 | 2 | 6 | 75.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 8 | 2 | 6 | 75.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
auto[OtpRootKeyValidLow] | 0 | 1 | 1 | |
auto[FlashOwnerSeedInvalid] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[OtpRootKeyInvalid] | 2 | 1 | T193 | 1 | T195 | 1 | - | - | ||||
auto[LcStateInvalid] | 60 | 1 | T29 | 12 | T59 | 12 | T57 | 12 | ||||
auto[OtpDevIdInvalid] | 180 | 1 | T27 | 36 | T28 | 24 | T54 | 60 | ||||
auto[RomDigestInvalid] | 84 | 1 | T27 | 36 | T59 | 36 | T55 | 12 | ||||
auto[RomDigestValidLow] | 36 | 1 | T54 | 12 | T244 | 12 | T245 | 12 | ||||
auto[FlashCreatorSeedInvalid] | 24 | 1 | T54 | 12 | T246 | 12 | - | - |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |