Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
73.02	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

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Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	16	33	67.35

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	15	20	57.14	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	41	1			T71	1		T106	1		T128	1
auto[OpGenId]	13	1			T31	1		T216	1		T217	1
auto[OpGenSwOut]	18	1			T40	1		T68	1		T136	1
auto[OpGenHwOut]	18	1			T7	1		T8	1		T9	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1690	1			T64	4		T12	180		T67	2
auto[StInit]	98	1			T39	1		T60	1		T44	1
auto[StCreatorRootKey]	69	1			T6	1		T10	1		T67	1
auto[StOwnerIntKey]	41	1			T40	1		T71	1		T61	1
auto[StOwnerKey]	23	1			T79	1		T149	1		T84	1
auto[StDisabled]	440	1			T17	1		T20	1		T64	3
auto[StInvalid]	50	1			T38	1		T37	1		T99	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3398

1

T1

1

T2

1

T3

1

auto[1]

90

1

T40

1

T71

1

T7

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1680	1			T64	4		T12	180		T67	2
auto[StReset]	auto[1]	10	1			T106	1		T31	1		T150	1
auto[StInit]	auto[0]	55	1			T39	1		T60	1		T44	1
auto[StInit]	auto[1]	43	1			T7	1		T8	1		T136	1
auto[StCreatorRootKey]	auto[0]	54	1			T6	1		T10	1		T67	1
auto[StCreatorRootKey]	auto[1]	15	1			T68	1		T9	1		T128	1
auto[StOwnerIntKey]	auto[0]	31	1			T61	1		T145	1		T9	1
auto[StOwnerIntKey]	auto[1]	10	1			T40	1		T71	1		T218	1
auto[StOwnerKey]	auto[0]	20	1			T79	1		T149	1		T84	1
auto[StOwnerKey]	auto[1]	3	1			T216	1		T219	1		T220	1
auto[StDisabled]	auto[0]	431	1			T17	1		T20	1		T64	3
auto[StDisabled]	auto[1]	9	1			T203	1		T221	1		T222	1
auto[StInvalid]	auto[0]	50	1			T38	1		T37	1		T99	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	15	20	57.14	15

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StInit]]	[auto[OpDisable]]	0	1	1
[auto[StCreatorRootKey]]	[auto[OpGenId]]	0	1	1
[auto[StCreatorRootKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerKey]]	[auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	3
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	7	1			T106	1		T150	1		T223	1
auto[StReset]	auto[OpGenId]	2	1			T31	1		T217	1		-	-
auto[StReset]	auto[OpGenSwOut]	1	1			T224	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	22	1			T142	1		T11	1		T225	2
auto[StInit]	auto[OpGenId]	5	1			T204	1		T226	1		T227	1
auto[StInit]	auto[OpGenSwOut]	7	1			T136	1		T228	1		T229	1
auto[StInit]	auto[OpGenHwOut]	9	1			T7	1		T8	1		T230	1
auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T128	1		T84	1		T231	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T68	1		T200	1		T36	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	4	1			T9	1		T232	1		T233	1
auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T71	1		T221	1		T234	1
auto[StOwnerIntKey]	auto[OpGenId]	2	1			T235	1		T236	1		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	1	1			T40	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	3	1			T218	1		T237	1		T238	1
auto[StOwnerKey]	auto[OpAdvance]	1	1			T219	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenId]	2	1			T216	1		T220	1		-	-
auto[StDisabled]	auto[OpAdvance]	2	1			T239	1		T163	1		-	-
auto[StDisabled]	auto[OpGenId]	2	1			T221	1		T240	1		-	-
auto[StDisabled]	auto[OpGenSwOut]	3	1			T203	1		T222	1		T241	1
auto[StDisabled]	auto[OpGenHwOut]	2	1			T242	1		T243	1		-	-