Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4640

1

T1

5

T4

6

T5

11

auto[1]

527

1

T1

3

T23

1

T47

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4640

1

T1

5

T4

6

T5

11

auto[1]

527

1

T1

3

T23

1

T47

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4629

1

T1

8

T4

3

T5

8

auto[1]

538

1

T4

3

T5

3

T17

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4629

1

T1

8

T4

3

T5

8

auto[1]

538

1

T4

3

T5

3

T17

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	408	1			T4	1		T16	1		T38	1
auto[OpGenId]	1082	1			T4	2		T16	1		T17	2
auto[OpGenSwOut]	1107	1			T4	2		T16	2		T17	2
auto[OpGenHwOut]	2497	1			T1	8		T4	1		T5	11
auto[OpDisable]	73	1			T129	1		T69	1		T146	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	408	1			T4	1		T16	1		T38	1
auto[OpGenId]	1082	1			T4	2		T16	1		T17	2
auto[OpGenSwOut]	1107	1			T4	2		T16	2		T17	2
auto[OpGenHwOut]	2497	1			T1	8		T4	1		T5	11
auto[OpDisable]	73	1			T129	1		T69	1		T146	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4652

1

T1

8

T4

6

T5

11

auto[1]

515

1

T15

4

T17

1

T18

4

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4652

1

T1

8

T4

6

T5

11

auto[1]

515

1

T15

4

T17

1

T18

4

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4869

1

T1

8

T4

5

T5

11

auto[1]

298

1

T4

1

T127

2

T74

4

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1815	1			T1	2		T4	1		T5	1
auto[1]	616	1			T1	1		T4	1		T5	1
auto[2]	703	1			T1	1		T4	1		T5	2
auto[3]	675	1			T1	1		T4	3		T5	4
auto[4]	306	1			T1	1		T15	1		T16	1
auto[5]	312	1			T1	1		T23	1		T19	1
auto[6]	400	1			T5	2		T16	1		T18	2
auto[7]	340	1			T1	1		T5	1		T15	2

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1358	1			T1	3		T5	3		T15	3
clear_one[1]	616	1			T1	1		T4	1		T5	1
clear_one[2]	703	1			T1	1		T4	1		T5	2
clear_one[3]	675	1			T1	1		T4	3		T5	4
clear_none	1815	1			T1	2		T4	1		T5	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	937	1			T5	3		T15	5		T17	4
auto[StInit]	632	1			T1	1		T4	1		T5	1
auto[StCreatorRootKey]	554	1			T1	1		T4	1		T5	1
auto[StOwnerIntKey]	477	1			T1	1		T5	1		T15	1
auto[StOwnerKey]	449	1			T1	1		T4	1		T5	1
auto[StDisabled]	1792	1			T1	4		T4	3		T5	4
auto[StInvalid]	326	1			T16	5		T38	4		T52	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	937	1			T5	3		T15	5		T17	4
auto[StInit]	632	1			T1	1		T4	1		T5	1
auto[StCreatorRootKey]	554	1			T1	1		T4	1		T5	1
auto[StOwnerIntKey]	477	1			T1	1		T5	1		T15	1
auto[StOwnerKey]	449	1			T1	1		T4	1		T5	1
auto[StDisabled]	1792	1			T1	4		T4	3		T5	4
auto[StInvalid]	326	1			T16	5		T38	4		T52	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	10
[auto[0] - auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[2] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[2] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[2] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[2] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[4]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset] , auto[StInit]]	[auto[OpAdvance]]	--	--	2
[auto[5]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[5]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[6] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[6] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	3	1			T247	1		T248	1		T249	1
auto[0]	auto[StReset]	auto[OpGenId]	137	1			T129	1		T69	2		T95	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	158	1			T17	1		T64	1		T74	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	253	1			T5	1		T15	2		T38	1
auto[0]	auto[StInit]	auto[OpAdvance]	35	1			T20	1		T40	1		T21	1
auto[0]	auto[StInit]	auto[OpGenId]	109	1			T127	1		T69	1		T250	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	92	1			T10	1		T27	1		T34	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	166	1			T1	1		T4	1		T18	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	24	1			T158	1		T251	1		T252	3
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	52	1			T47	1		T30	1		T69	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	43	1			T19	1		T64	1		T75	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	82	1			T18	1		T64	1		T100	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T78	1		T65	1		T253	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	31	1			T23	1		T254	1		T9	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	34	1			T212	1		T101	1		T255	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	67	1			T127	2		T97	1		T71	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T20	1		T112	1		T256	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	24	1			T257	1		T258	1		T255	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	19	1			T22	1		T155	1		T211	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	51	1			T1	1		T15	1		T130	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	36	1			T74	1		T155	1		T259	1
auto[0]	auto[StDisabled]	auto[OpGenId]	55	1			T74	1		T260	1		T154	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	62	1			T47	1		T64	1		T257	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	146	1			T215	1		T77	1		T166	1
auto[0]	auto[StDisabled]	auto[OpDisable]	20	1			T79	1		T65	1		T261	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	18	1			T38	1		T99	1		T262	1
auto[0]	auto[StInvalid]	auto[OpGenId]	29	1			T38	1		T37	1		T51	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	25	1			T49	2		T148	1		T263	2
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	32	1			T16	1		T52	1		T48	2
auto[1]	auto[StReset]	auto[OpAdvance]	1	1			T264	1		-	-		-	-
auto[1]	auto[StReset]	auto[OpGenId]	13	1			T30	1		T8	1		T265	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	11	1			T51	1		T211	1		T202	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	41	1			T17	2		T129	1		T100	1
auto[1]	auto[StInit]	auto[OpAdvance]	10	1			T84	1		T264	1		T266	3
auto[1]	auto[StInit]	auto[OpGenId]	13	1			T27	1		T28	1		T9	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	5	1			T28	1		T192	1		T225	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	26	1			T215	1		T64	1		T267	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T9	1		T268	1		T269	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T270	1		T53	1		T211	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T4	1		T97	1		T71	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	35	1			T20	1		T34	1		T94	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T271	1		T272	1		T273	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T274	1		T275	1		T204	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T34	1		T155	1		T114	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	28	1			T100	1		T76	1		T94	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T56	1		T204	1		T222	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	13	1			T21	1		T271	1		T276	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T154	1		T221	1		T204	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	35	1			T166	1		T167	1		T34	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	22	1			T101	2		T277	1		T271	1
auto[1]	auto[StDisabled]	auto[OpGenId]	49	1			T17	1		T146	1		T210	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	43	1			T97	1		T87	1		T69	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	151	1			T1	1		T5	1		T22	1
auto[1]	auto[StDisabled]	auto[OpDisable]	9	1			T80	1		T278	1		T279	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	11	1			T52	1		T280	1		T281	1
auto[1]	auto[StInvalid]	auto[OpGenId]	12	1			T282	1		T283	1		T284	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T49	1		T148	1		T285	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T38	1		T99	1		T286	1
auto[2]	auto[StReset]	auto[OpGenId]	27	1			T38	1		T30	1		T211	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	20	1			T66	1		T282	1		T82	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	46	1			T5	1		T209	1		T94	1
auto[2]	auto[StInit]	auto[OpAdvance]	6	1			T287	1		T53	1		T288	1
auto[2]	auto[StInit]	auto[OpGenId]	11	1			T17	1		T95	1		T289	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	6	1			T81	1		T290	1		T291	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	18	1			T165	1		T292	1		T293	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T155	1		T294	1		T295	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	16	1			T22	1		T296	1		T297	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T209	1		T40	1		T287	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	47	1			T15	1		T74	1		T298	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T299	1		T300	1		T244	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T287	1		T278	1		T81	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	19	1			T40	1		T74	2		T77	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	39	1			T18	1		T130	1		T215	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T204	1		T301	1		T302	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	16	1			T212	1		T214	1		T200	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T211	1		T275	1		T221	2
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T303	1		T254	1		T298	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	22	1			T87	1		T257	1		T9	1
auto[2]	auto[StDisabled]	auto[OpGenId]	52	1			T127	1		T69	1		T303	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	61	1			T4	1		T78	2		T93	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	149	1			T1	1		T5	1		T15	2
auto[2]	auto[StDisabled]	auto[OpDisable]	10	1			T304	1		T305	1		T306	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	7	1			T280	1		T307	1		T308	1
auto[2]	auto[StInvalid]	auto[OpGenId]	11	1			T38	1		T48	1		T309	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T37	1		T280	1		T310	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T51	1		T280	1		T310	1
auto[3]	auto[StReset]	auto[OpGenId]	11	1			T146	1		T9	1		T155	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	18	1			T17	1		T79	1		T310	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	40	1			T5	1		T15	2		T38	1
auto[3]	auto[StInit]	auto[OpAdvance]	6	1			T27	1		T155	1		T311	1
auto[3]	auto[StInit]	auto[OpGenId]	3	1			T210	1		T312	1		T313	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	8	1			T129	1		T80	1		T278	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	28	1			T5	1		T15	1		T94	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T314	1		T221	1		T315	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T103	1		T316	1		T317	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T144	1		T66	1		T154	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	40	1			T215	1		T69	1		T267	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T318	1		T319	5		T320	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T147	1		T154	1		T265	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T146	1		T321	1		T276	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	36	1			T1	1		T5	1		T15	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T322	1		T323	1		-	-
auto[3]	auto[StOwnerKey]	auto[OpGenId]	15	1			T4	1		T69	1		T65	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T77	1		T66	1		T324	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	32	1			T5	1		T18	1		T75	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	32	1			T4	1		T260	1		T108	1
auto[3]	auto[StDisabled]	auto[OpGenId]	53	1			T4	1		T129	1		T87	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	59	1			T95	1		T287	1		T9	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	160	1			T127	2		T215	1		T100	2
auto[3]	auto[StDisabled]	auto[OpDisable]	13	1			T69	1		T103	1		T204	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	5	1			T16	1		T37	1		T49	1
auto[3]	auto[StInvalid]	auto[OpGenId]	17	1			T52	1		T51	1		T310	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T16	1		T45	1		T286	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T99	1		T48	1		T325	1
auto[4]	auto[StReset]	auto[OpAdvance]	1	1			T326	1		-	-		-	-
auto[4]	auto[StReset]	auto[OpGenId]	6	1			T257	1		T327	1		T328	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	14	1			T51	1		T65	1		T154	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	18	1			T94	1		T95	1		T267	1
auto[4]	auto[StInit]	auto[OpAdvance]	2	1			T329	1		T330	1		-	-
auto[4]	auto[StInit]	auto[OpGenId]	2	1			T144	1		T204	1		-	-
auto[4]	auto[StInit]	auto[OpGenSwOut]	11	1			T27	1		T146	1		T303	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	12	1			T107	1		T79	1		T331	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T332	1		T231	1		T333	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T213	1		T334	1		T234	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T335	1		T323	1		T239	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T1	1		T107	1		T154	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T336	1		T269	1		T326	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T209	1		T87	1		T210	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	1	1			T65	1		-	-		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T166	1		T337	1		T338	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T339	1		T340	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	6	1			T154	1		T268	1		T159	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T65	1		T341	1		T294	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T72	1		T342	1		T343	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	10	1			T30	1		T251	1		T252	1
auto[4]	auto[StDisabled]	auto[OpGenId]	19	1			T154	1		T344	1		T345	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	16	1			T64	1		T79	1		T65	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	60	1			T15	1		T215	1		T75	1
auto[4]	auto[StDisabled]	auto[OpDisable]	5	1			T346	1		T347	1		T348	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	4	1			T349	1		T350	1		T284	1
auto[4]	auto[StInvalid]	auto[OpGenId]	9	1			T285	1		T325	1		T351	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T16	1		T352	1		T353	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T45	1		T262	1		T354	1
auto[5]	auto[StReset]	auto[OpGenId]	12	1			T79	1		T355	1		T230	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	12	1			T69	1		T356	1		T357	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	16	1			T105	1		T358	1		T331	1
auto[5]	auto[StInit]	auto[OpGenId]	3	1			T359	1		T360	1		T57	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	3	1			T155	1		T309	1		T361	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	7	1			T298	1		T362	1		T363	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T364	1		T291	1		T220	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T357	1		T365	1		T366	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T10	1		T108	1		T265	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	13	1			T367	1		T368	1		T369	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T291	1		T233	1		T220	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T250	1		T158	1		T201	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T204	1		T370	1		T240	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T292	1		T343	1		T367	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T114	1		T295	1		T371	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	3	1			T9	1		T202	1		T372	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T291	1		T195	1		T373	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	24	1			T94	1		T337	1		T374	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	7	1			T30	1		T200	1		T375	1
auto[5]	auto[StDisabled]	auto[OpGenId]	20	1			T21	1		T34	1		T66	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	27	1			T19	1		T93	1		T69	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	76	1			T1	1		T23	1		T130	1
auto[5]	auto[StDisabled]	auto[OpDisable]	11	1			T66	1		T154	1		T376	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	4	1			T263	1		T377	1		T378	1
auto[5]	auto[StInvalid]	auto[OpGenId]	6	1			T99	1		T379	1		T380	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T381	1		T382	1		T383	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T51	1		T325	1		T384	1
auto[6]	auto[StReset]	auto[OpGenId]	9	1			T268	1		T193	1		T385	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	12	1			T71	1		T51	1		T35	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	21	1			T166	1		T94	1		T282	1
auto[6]	auto[StInit]	auto[OpAdvance]	7	1			T74	1		T386	1		T387	3
auto[6]	auto[StInit]	auto[OpGenId]	7	1			T66	1		T296	1		T252	2
auto[6]	auto[StInit]	auto[OpGenSwOut]	4	1			T233	1		T245	1		T220	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	18	1			T166	1		T358	1		T368	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T127	1		T192	1		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T165	1		T79	1		T271	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T85	1		T250	1		T114	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T166	1		T388	1		T389	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T234	1		T390	1		T391	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T29	1		T392	1		T393	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T394	1		T395	1		T396	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T95	1		T155	1		T84	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T79	1		T80	1		T397	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	6	1			T225	1		T193	1		T235	2
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T19	1		T97	1		T78	2
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T78	1		T69	1		T267	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	21	1			T34	1		T311	1		T158	1
auto[6]	auto[StDisabled]	auto[OpGenId]	32	1			T97	1		T21	1		T78	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	36	1			T19	1		T87	1		T78	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	86	1			T5	2		T18	2		T22	1
auto[6]	auto[StDisabled]	auto[OpDisable]	1	1			T347	1		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpAdvance]	9	1			T309	1		T308	1		T398	1
auto[6]	auto[StInvalid]	auto[OpGenId]	12	1			T16	1		T307	1		T399	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T282	1		T400	1		T401	2
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T399	1		T402	1		T403	1
auto[7]	auto[StReset]	auto[OpGenId]	9	1			T11	1		T290	1		T404	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	6	1			T405	1		T277	1		T406	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	22	1			T15	1		T100	1		T166	1
auto[7]	auto[StInit]	auto[OpAdvance]	3	1			T407	1		T219	1		T408	1
auto[7]	auto[StInit]	auto[OpGenId]	1	1			T59	1		-	-		-	-
auto[7]	auto[StInit]	auto[OpGenSwOut]	4	1			T409	1		T59	1		T204	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	6	1			T27	1		T410	1		T411	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T248	1		T407	1		T412	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T81	1		T413	1		T414	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T303	1		T355	1		T278	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T5	1		T130	1		T167	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T415	1		T96	1		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	3	1			T248	1		T240	1		T416	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T28	1		T317	1		T268	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T64	2		T303	1		T342	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T417	1		T418	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	4	1			T419	1		T420	2		T421	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T74	1		T28	1		T155	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T422	1		T423	1		T424	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	8	1			T259	1		T81	1		T89	1
auto[7]	auto[StDisabled]	auto[OpGenId]	31	1			T154	1		T84	1		T211	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	30	1			T97	1		T64	1		T69	2
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	88	1			T1	1		T15	1		T72	1
auto[7]	auto[StDisabled]	auto[OpDisable]	4	1			T129	1		T146	1		T154	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	2	1			T384	1		T425	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	8	1			T52	1		T280	1		T404	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T45	1		T283	1		T351	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T262	1		T309	1		T349	1