Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

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Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1358

1

T1

3

T5

3

T15

3

clear_one[1]

auto[0]

auto[0]

auto[0]

362

1

T1

1

T4

1

T17

2

clear_one[1]

auto[0]

auto[0]

auto[1]

97

1

T22

1

T71

1

T166

1

clear_one[1]

auto[0]

auto[1]

auto[0]

117

1

T5

1

T72

1

T76

1

clear_one[1]

auto[0]

auto[1]

auto[1]

40

1

T17

1

T20

1

T34

3

clear_one[2]

auto[0]

auto[0]

auto[0]

415

1

T4

1

T5

2

T17

1

clear_one[2]

auto[0]

auto[0]

auto[1]

128

1

T15

3

T18

3

T127

1

clear_one[2]

auto[1]

auto[0]

auto[0]

119

1

T1

1

T130

2

T209

1

clear_one[2]

auto[1]

auto[0]

auto[1]

41

1

T23

1

T78

2

T287

1

clear_one[3]

auto[0]

auto[0]

auto[0]

391

1

T5

2

T15

4

T16

2

clear_one[3]

auto[0]

auto[1]

auto[0]

119

1

T4

3

T5

2

T127

1

clear_one[3]

auto[1]

auto[0]

auto[0]

123

1

T1

1

T100

2

T87

1

clear_one[3]

auto[1]

auto[1]

auto[0]

42

1

T127

1

T9

1

T278

3

clear_none

auto[0]

auto[0]

auto[0]

1322

1

T1

1

T4

1

T5

1

clear_none

auto[0]

auto[0]

auto[1]

128

1

T15

1

T18

1

T19

1

clear_none

auto[0]

auto[1]

auto[0]

130

1

T20

1

T215

2

T72

2

clear_none

auto[0]

auto[1]

auto[1]

33

1

T127

1

T74

2

T257

1

clear_none

auto[1]

auto[0]

auto[0]

119

1

T1

1

T130

1

T100

2

clear_none

auto[1]

auto[0]

auto[1]

26

1

T47

1

T426

1

T427

1

clear_none

auto[1]

auto[1]

auto[0]

35

1

T93

2

T101

1

T9

1

clear_none

auto[1]

auto[1]

auto[1]

22

1

T101

2

T417

1

T113

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1286	1			T1	3		T5	3		T15	3
clear_all	auto[1]	72	1			T78	4		T252	4		T112	3
clear_one[1]	auto[0]	586	1			T1	1		T4	1		T5	1
clear_one[1]	auto[1]	30	1			T101	3		T247	3		T428	2
clear_one[2]	auto[0]	658	1			T1	1		T5	2		T15	3
clear_one[2]	auto[1]	45	1			T4	1		T74	2		T78	2
clear_one[3]	auto[0]	626	1			T1	1		T4	3		T5	4
clear_one[3]	auto[1]	49	1			T127	1		T247	1		T429	2
clear_none	auto[0]	1713	1			T1	2		T4	1		T5	1
clear_none	auto[1]	102	1			T127	1		T74	2		T78	1