Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10718

1

T1

2

T2

13

T4

8

auto[Attestation]

7274

1

T1

6

T2

2

T4

15

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2579	1			T2	2		T4	4		T6	2
auto[Aes]	3187	1			T1	8		T2	2		T4	5
auto[Kmac]	3253	1			T2	3		T4	5		T5	13
auto[Otbn]	3321	1			T2	2		T15	22		T6	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7321	1			T1	8		T2	8		T4	8
auto[OpGenId]	5652	1			T2	6		T4	9		T6	6
auto[OpGenSwOut]	5607	1			T2	9		T4	5		T6	5
auto[OpGenHwOut]	6733	1			T1	8		T4	9		T5	13
auto[OpDisable]	144	1			T129	1		T64	1		T144	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10086

1

T1

8

T2

8

T4

16

auto[OpDoneFail]

15371

1

T1

8

T2

15

T4

15

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6280	1			T1	1		T2	8		T4	1
auto[StInit]	3615	1			T1	2		T2	2		T4	2
auto[StCreatorRootKey]	3017	1			T1	2		T2	2		T4	6
auto[StOwnerIntKey]	2604	1			T1	2		T2	2		T4	6
auto[StOwnerKey]	2312	1			T1	2		T2	2		T4	2
auto[StDisabled]	7629	1			T1	7		T2	7		T4	14

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	350	1			T2	1		T6	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	89	1			T2	1		T129	1		T37	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	73	1			T40	1		T144	2		T67	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	66	1			T17	1		T23	1		T64	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	57	1			T154	1		T155	1		T208	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	210	1			T17	1		T23	1		T19	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	333	1			T2	1		T6	2		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	95	1			T127	1		T30	1		T77	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	86	1			T2	1		T4	1		T97	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	61	1			T40	2		T67	1		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	63	1			T22	1		T23	1		T78	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	199	1			T17	1		T64	2		T74	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	386	1			T2	1		T38	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	66	1			T23	1		T129	1		T143	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	77	1			T40	1		T64	1		T10	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	61	1			T23	1		T21	1		T71	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	49	1			T97	1		T98	1		T21	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	206	1			T2	1		T20	1		T64	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	320	1			T2	1		T17	1		T38	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	89	1			T17	1		T64	1		T85	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	76	1			T209	1		T78	1		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	63	1			T17	1		T127	1		T67	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	52	1			T86	1		T95	1		T65	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	241	1			T2	1		T23	1		T19	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	58	1			T67	1		T9	1		T79	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	88	1			T6	1		T23	1		T37	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	72	1			T4	1		T19	2		T209	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	71	1			T98	1		T34	1		T104	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	56	1			T23	1		T19	1		T92	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	192	1			T127	1		T97	1		T74	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	61	1			T79	1		T66	1		T210	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	105	1			T47	1		T61	1		T68	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	91	1			T20	1		T87	1		T71	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	81	1			T4	1		T86	1		T75	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	59	1			T67	1		T101	1		T110	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	197	1			T4	2		T23	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	65	1			T67	1		T9	2		T79	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	96	1			T209	1		T64	1		T10	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	79	1			T20	1		T98	1		T21	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	64	1			T20	1		T40	1		T74	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	65	1			T17	1		T23	1		T64	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	183	1			T2	1		T17	1		T64	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	63	1			T79	2		T155	1		T211	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	101	1			T86	1		T30	1		T27	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	70	1			T6	1		T19	1		T71	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	62	1			T71	1		T77	1		T146	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	38	1			T212	1		T213	1		T211	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	222	1			T17	1		T23	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	259	1			T17	3		T38	4		T52	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	89	1			T60	1		T30	1		T69	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	85	1			T4	1		T74	1		T67	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	60	1			T23	2		T75	2		T69	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	48	1			T64	1		T30	1		T93	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	165	1			T22	1		T23	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	398	1			T6	1		T17	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	122	1			T64	1		T37	1		T100	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	91	1			T20	1		T9	1		T214	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	84	1			T209	1		T100	1		T167	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	79	1			T100	1		T87	1		T167	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	258	1			T1	2		T19	1		T130	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	454	1			T5	5		T6	2		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	99	1			T5	1		T215	1		T75	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	113	1			T5	1		T6	2		T72	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	89	1			T4	1		T127	1		T215	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	88	1			T215	1		T76	1		T94	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	252	1			T5	2		T17	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	475	1			T15	14		T19	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	144	1			T15	1		T17	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	118	1			T15	1		T19	1		T85	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	83	1			T18	1		T127	1		T209	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	79	1			T18	1		T165	1		T69	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	294	1			T15	1		T18	1		T22	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	47	1			T79	1		T66	1		T155	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	100	1			T97	1		T37	1		T10	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	62	1			T64	1		T85	1		T69	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	67	1			T22	1		T19	1		T97	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	46	1			T78	1		T34	1		T9	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	169	1			T4	2		T17	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	49	1			T79	1		T210	1		T155	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	112	1			T1	1		T22	1		T130	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	109	1			T1	1		T4	1		T130	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	108	1			T1	1		T130	1		T64	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	91	1			T1	1		T130	1		T75	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	255	1			T1	2		T22	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	57	1			T9	2		T79	1		T66	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	114	1			T4	1		T85	1		T72	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	109	1			T215	1		T67	1		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	105	1			T4	1		T5	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	81	1			T5	1		T19	1		T30	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	295	1			T4	2		T5	2		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	55	1			T79	1		T66	2		T211	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	107	1			T18	1		T64	1		T30	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	113	1			T18	1		T85	1		T71	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	83	1			T15	1		T47	1		T71	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	87	1			T15	1		T17	1		T165	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	286	1			T15	3		T18	3		T23	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	173	1			T17	1		T23	1		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	672	1			T2	2		T6	1		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	194	1			T2	1		T4	1		T22	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	643	1			T2	1		T6	2		T17	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	177	1			T23	1		T40	1		T97	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	668	1			T2	2		T38	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	179	1			T17	1		T127	1		T209	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	662	1			T2	2		T17	2		T38	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	182	1			T4	1		T23	1		T19	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	355	1			T6	1		T23	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	215	1			T4	1		T20	1		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	379	1			T4	2		T23	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	193	1			T17	1		T23	1		T20	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	359	1			T2	1		T17	1		T209	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	158	1			T6	1		T19	1		T71	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	398	1			T17	1		T23	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	177	1			T4	1		T23	2		T64	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	529	1			T17	3		T22	1		T38	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	247	1			T20	1		T209	1		T100	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	785	1			T1	2		T6	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	272	1			T4	1		T5	1		T6	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	823	1			T5	8		T6	2		T17	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	267	1			T15	1		T18	2		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	926	1			T15	16		T17	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	162	1			T22	1		T97	1		T64	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	329	1			T4	2		T17	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	290	1			T1	3		T4	1		T130	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	434	1			T1	3		T22	2		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	270	1			T4	1		T5	2		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	491	1			T4	3		T5	2		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	267	1			T15	2		T17	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	464	1			T15	3		T18	4		T23	2