Unified Coverage Report :: Group Instance : attest_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31532

1

T1

18

T2

26

T4

35

auto[1]

276

1

T4

2

T74

3

T78

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31541	1			T1	18		T2	26		T4	35
auto[134217728:268435455]	13	1			T101	1		T252	1		T112	2
auto[268435456:402653183]	9	1			T101	1		T247	1		T256	1
auto[402653184:536870911]	7	1			T424	2		T428	1		T319	1
auto[536870912:671088639]	7	1			T247	1		T429	1		T387	1
auto[671088640:805306367]	8	1			T112	1		T247	1		T365	1
auto[805306368:939524095]	6	1			T78	1		T101	1		T249	1
auto[939524096:1073741823]	11	1			T78	1		T112	1		T113	2
auto[1073741824:1207959551]	7	1			T115	2		T429	1		T248	1
auto[1207959552:1342177279]	11	1			T113	1		T429	1		T428	2
auto[1342177280:1476395007]	5	1			T74	1		T248	1		T453	1
auto[1476395008:1610612735]	4	1			T113	1		T424	1		T365	1
auto[1610612736:1744830463]	11	1			T108	1		T112	1		T115	1
auto[1744830464:1879048191]	11	1			T101	1		T112	1		T247	1
auto[1879048192:2013265919]	10	1			T112	1		T113	1		T114	1
auto[2013265920:2147483647]	8	1			T78	1		T252	1		T112	1
auto[2147483648:2281701375]	4	1			T256	1		T387	2		T319	1
auto[2281701376:2415919103]	10	1			T247	1		T420	1		T428	1
auto[2415919104:2550136831]	5	1			T387	1		T266	1		T454	1
auto[2550136832:2684354559]	8	1			T247	1		T424	1		T364	1
auto[2684354560:2818572287]	9	1			T420	1		T429	1		T387	1
auto[2818572288:2952790015]	13	1			T101	1		T247	2		T256	1
auto[2952790016:3087007743]	7	1			T78	1		T112	1		T429	1
auto[3087007744:3221225471]	7	1			T78	1		T252	1		T429	1
auto[3221225472:3355443199]	9	1			T112	1		T247	1		T256	1
auto[3355443200:3489660927]	12	1			T4	1		T112	2		T247	1
auto[3489660928:3623878655]	10	1			T74	1		T420	1		T424	1
auto[3623878656:3758096383]	12	1			T247	3		T256	1		T424	1
auto[3758096384:3892314111]	8	1			T74	1		T101	2		T247	1
auto[3892314112:4026531839]	10	1			T101	2		T112	1		T387	1
auto[4026531840:4160749567]	9	1			T252	1		T113	1		T114	1
auto[4160749568:4294967295]	6	1			T4	1		T428	1		T365	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31532	1			T1	18		T2	26		T4	35
auto[0:134217727]	auto[1]	9	1			T101	1		T115	1		T288	1
auto[134217728:268435455]	auto[1]	13	1			T101	1		T252	1		T112	2
auto[268435456:402653183]	auto[1]	9	1			T101	1		T247	1		T256	1
auto[402653184:536870911]	auto[1]	7	1			T424	2		T428	1		T319	1
auto[536870912:671088639]	auto[1]	7	1			T247	1		T429	1		T387	1
auto[671088640:805306367]	auto[1]	8	1			T112	1		T247	1		T365	1
auto[805306368:939524095]	auto[1]	6	1			T78	1		T101	1		T249	1
auto[939524096:1073741823]	auto[1]	11	1			T78	1		T112	1		T113	2
auto[1073741824:1207959551]	auto[1]	7	1			T115	2		T429	1		T248	1
auto[1207959552:1342177279]	auto[1]	11	1			T113	1		T429	1		T428	2
auto[1342177280:1476395007]	auto[1]	5	1			T74	1		T248	1		T453	1
auto[1476395008:1610612735]	auto[1]	4	1			T113	1		T424	1		T365	1
auto[1610612736:1744830463]	auto[1]	11	1			T108	1		T112	1		T115	1
auto[1744830464:1879048191]	auto[1]	11	1			T101	1		T112	1		T247	1
auto[1879048192:2013265919]	auto[1]	10	1			T112	1		T113	1		T114	1
auto[2013265920:2147483647]	auto[1]	8	1			T78	1		T252	1		T112	1
auto[2147483648:2281701375]	auto[1]	4	1			T256	1		T387	2		T319	1
auto[2281701376:2415919103]	auto[1]	10	1			T247	1		T420	1		T428	1
auto[2415919104:2550136831]	auto[1]	5	1			T387	1		T266	1		T454	1
auto[2550136832:2684354559]	auto[1]	8	1			T247	1		T424	1		T364	1
auto[2684354560:2818572287]	auto[1]	9	1			T420	1		T429	1		T387	1
auto[2818572288:2952790015]	auto[1]	13	1			T101	1		T247	2		T256	1
auto[2952790016:3087007743]	auto[1]	7	1			T78	1		T112	1		T429	1
auto[3087007744:3221225471]	auto[1]	7	1			T78	1		T252	1		T429	1
auto[3221225472:3355443199]	auto[1]	9	1			T112	1		T247	1		T256	1
auto[3355443200:3489660927]	auto[1]	12	1			T4	1		T112	2		T247	1
auto[3489660928:3623878655]	auto[1]	10	1			T74	1		T420	1		T424	1
auto[3623878656:3758096383]	auto[1]	12	1			T247	3		T256	1		T424	1
auto[3758096384:3892314111]	auto[1]	8	1			T74	1		T101	2		T247	1
auto[3892314112:4026531839]	auto[1]	10	1			T101	2		T112	1		T387	1
auto[4026531840:4160749567]	auto[1]	9	1			T252	1		T113	1		T114	1
auto[4160749568:4294967295]	auto[1]	6	1			T4	1		T428	1		T365	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1591

1

T4

2

T16

4

T17

5

auto[1]

1740

1

T4

4

T16

2

T17

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T4	1		T17	1		T23	1
auto[134217728:268435455]	108	1			T99	1		T10	1		T30	1
auto[268435456:402653183]	103	1			T40	2		T87	1		T74	1
auto[402653184:536870911]	97	1			T19	1		T21	2		T69	2
auto[536870912:671088639]	99	1			T4	2		T16	1		T48	1
auto[671088640:805306367]	119	1			T17	1		T99	1		T48	1
auto[805306368:939524095]	106	1			T16	1		T75	1		T78	1
auto[939524096:1073741823]	99	1			T17	1		T38	1		T23	1
auto[1073741824:1207959551]	101	1			T38	1		T20	1		T127	1
auto[1207959552:1342177279]	109	1			T127	1		T30	1		T49	1
auto[1342177280:1476395007]	105	1			T10	1		T78	1		T69	2
auto[1476395008:1610612735]	105	1			T4	1		T17	2		T20	1
auto[1610612736:1744830463]	103	1			T17	1		T127	1		T21	1
auto[1744830464:1879048191]	113	1			T127	1		T87	1		T71	1
auto[1879048192:2013265919]	115	1			T21	1		T75	1		T78	1
auto[2013265920:2147483647]	112	1			T16	1		T127	1		T21	1
auto[2147483648:2281701375]	100	1			T48	1		T257	1		T45	1
auto[2281701376:2415919103]	105	1			T23	1		T37	1		T51	1
auto[2415919104:2550136831]	104	1			T16	1		T19	1		T20	1
auto[2550136832:2684354559]	98	1			T38	3		T129	1		T19	1
auto[2684354560:2818572287]	110	1			T38	1		T209	1		T48	1
auto[2818572288:2952790015]	97	1			T17	1		T23	1		T95	1
auto[2952790016:3087007743]	83	1			T17	2		T52	1		T99	1
auto[3087007744:3221225471]	105	1			T4	1		T38	1		T64	1
auto[3221225472:3355443199]	101	1			T37	1		T30	1		T71	1
auto[3355443200:3489660927]	94	1			T146	1		T45	2		T101	1
auto[3489660928:3623878655]	122	1			T129	1		T64	1		T37	1
auto[3623878656:3758096383]	99	1			T16	1		T64	1		T48	1
auto[3758096384:3892314111]	101	1			T20	1		T30	1		T71	1
auto[3892314112:4026531839]	110	1			T165	1		T67	1		T95	1
auto[4026531840:4160749567]	103	1			T4	1		T16	1		T38	1
auto[4160749568:4294967295]	100	1			T30	1		T75	1		T95	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	52	1			T17	1		T23	1		T99	1
auto[0:134217727]	auto[1]	53	1			T4	1		T69	1		T45	1
auto[134217728:268435455]	auto[0]	49	1			T99	1		T30	1		T7	1
auto[134217728:268435455]	auto[1]	59	1			T10	1		T165	1		T104	1
auto[268435456:402653183]	auto[0]	51	1			T74	1		T314	1		T210	1
auto[268435456:402653183]	auto[1]	52	1			T40	2		T87	1		T95	1
auto[402653184:536870911]	auto[0]	49	1			T21	1		T69	1		T8	1
auto[402653184:536870911]	auto[1]	48	1			T19	1		T21	1		T69	1
auto[536870912:671088639]	auto[0]	45	1			T16	1		T48	1		T74	1
auto[536870912:671088639]	auto[1]	54	1			T4	2		T260	2		T65	2
auto[671088640:805306367]	auto[0]	54	1			T99	1		T48	1		T95	1
auto[671088640:805306367]	auto[1]	65	1			T17	1		T165	1		T212	1
auto[805306368:939524095]	auto[0]	57	1			T78	1		T27	1		T28	1
auto[805306368:939524095]	auto[1]	49	1			T16	1		T75	1		T307	1
auto[939524096:1073741823]	auto[0]	47	1			T17	1		T19	2		T52	1
auto[939524096:1073741823]	auto[1]	52	1			T38	1		T23	1		T87	1
auto[1073741824:1207959551]	auto[0]	44	1			T38	1		T20	1		T127	1
auto[1073741824:1207959551]	auto[1]	57	1			T21	1		T28	1		T314	1
auto[1207959552:1342177279]	auto[0]	49	1			T49	1		T34	1		T95	1
auto[1207959552:1342177279]	auto[1]	60	1			T127	1		T30	1		T34	1
auto[1342177280:1476395007]	auto[0]	57	1			T69	1		T260	1		T101	1
auto[1342177280:1476395007]	auto[1]	48	1			T10	1		T78	1		T69	1
auto[1476395008:1610612735]	auto[0]	45	1			T17	2		T85	1		T146	1
auto[1476395008:1610612735]	auto[1]	60	1			T4	1		T20	1		T48	1
auto[1610612736:1744830463]	auto[0]	36	1			T71	1		T7	1		T286	1
auto[1610612736:1744830463]	auto[1]	67	1			T17	1		T127	1		T21	1
auto[1744830464:1879048191]	auto[0]	57	1			T127	1		T71	1		T303	1
auto[1744830464:1879048191]	auto[1]	56	1			T87	1		T78	1		T144	1
auto[1879048192:2013265919]	auto[0]	52	1			T21	1		T75	1		T27	1
auto[1879048192:2013265919]	auto[1]	63	1			T78	1		T67	1		T69	1
auto[2013265920:2147483647]	auto[0]	50	1			T16	1		T287	1		T152	1
auto[2013265920:2147483647]	auto[1]	62	1			T127	1		T21	1		T74	1
auto[2147483648:2281701375]	auto[0]	48	1			T48	1		T45	1		T152	1
auto[2147483648:2281701375]	auto[1]	52	1			T257	1		T154	1		T108	1
auto[2281701376:2415919103]	auto[0]	49	1			T37	1		T51	1		T210	1
auto[2281701376:2415919103]	auto[1]	56	1			T23	1		T148	1		T9	1
auto[2415919104:2550136831]	auto[0]	42	1			T30	1		T143	1		T287	1
auto[2415919104:2550136831]	auto[1]	62	1			T16	1		T19	1		T20	1
auto[2550136832:2684354559]	auto[0]	53	1			T144	1		T27	1		T51	1
auto[2550136832:2684354559]	auto[1]	45	1			T38	3		T129	1		T19	1
auto[2684354560:2818572287]	auto[0]	58	1			T38	1		T48	1		T74	1
auto[2684354560:2818572287]	auto[1]	52	1			T209	1		T101	1		T65	1
auto[2818572288:2952790015]	auto[0]	47	1			T95	1		T146	1		T104	1
auto[2818572288:2952790015]	auto[1]	50	1			T17	1		T23	1		T147	1
auto[2952790016:3087007743]	auto[0]	49	1			T17	1		T52	1		T99	1
auto[2952790016:3087007743]	auto[1]	34	1			T17	1		T287	1		T147	1
auto[3087007744:3221225471]	auto[0]	55	1			T4	1		T64	1		T71	1
auto[3087007744:3221225471]	auto[1]	50	1			T38	1		T87	1		T69	1
auto[3221225472:3355443199]	auto[0]	47	1			T37	1		T68	1		T51	1
auto[3221225472:3355443199]	auto[1]	54	1			T30	1		T71	1		T34	1
auto[3355443200:3489660927]	auto[0]	46	1			T45	1		T101	1		T9	1
auto[3355443200:3489660927]	auto[1]	48	1			T146	1		T45	1		T9	1
auto[3489660928:3623878655]	auto[0]	53	1			T129	1		T64	1		T37	1
auto[3489660928:3623878655]	auto[1]	69	1			T257	1		T303	2		T148	1
auto[3623878656:3758096383]	auto[0]	44	1			T16	1		T48	1		T7	2
auto[3623878656:3758096383]	auto[1]	55	1			T64	1		T30	1		T287	1
auto[3758096384:3892314111]	auto[0]	43	1			T20	1		T30	1		T71	1
auto[3758096384:3892314111]	auto[1]	58	1			T257	1		T35	1		T250	1
auto[3892314112:4026531839]	auto[0]	55	1			T67	1		T95	1		T45	1
auto[3892314112:4026531839]	auto[1]	55	1			T165	1		T303	1		T65	1
auto[4026531840:4160749567]	auto[0]	54	1			T4	1		T16	1		T52	1
auto[4026531840:4160749567]	auto[1]	49	1			T38	1		T37	1		T287	1
auto[4160749568:4294967295]	auto[0]	54	1			T30	1		T95	1		T257	1
auto[4160749568:4294967295]	auto[1]	46	1			T75	1		T108	1		T259	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1575

1

T4

1

T16

5

T17

4

auto[1]

1755

1

T4

5

T16

1

T17

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	110	1			T127	1		T37	1		T30	1
auto[134217728:268435455]	114	1			T17	1		T38	1		T48	1
auto[268435456:402653183]	114	1			T16	1		T19	1		T87	1
auto[402653184:536870911]	98	1			T17	1		T127	1		T40	1
auto[536870912:671088639]	101	1			T38	1		T10	1		T71	2
auto[671088640:805306367]	108	1			T48	1		T71	2		T69	1
auto[805306368:939524095]	99	1			T23	1		T20	1		T85	1
auto[939524096:1073741823]	89	1			T4	1		T16	1		T69	1
auto[1073741824:1207959551]	85	1			T23	1		T127	1		T64	1
auto[1207959552:1342177279]	110	1			T16	1		T74	1		T69	1
auto[1342177280:1476395007]	106	1			T38	1		T52	1		T144	1
auto[1476395008:1610612735]	102	1			T16	1		T17	1		T21	1
auto[1610612736:1744830463]	110	1			T17	1		T21	1		T48	1
auto[1744830464:1879048191]	113	1			T17	1		T38	2		T7	1
auto[1879048192:2013265919]	106	1			T17	1		T19	1		T99	3
auto[2013265920:2147483647]	106	1			T209	1		T85	1		T48	1
auto[2147483648:2281701375]	116	1			T4	1		T38	1		T19	1
auto[2281701376:2415919103]	121	1			T4	1		T17	1		T40	1
auto[2415919104:2550136831]	84	1			T127	1		T78	1		T7	1
auto[2550136832:2684354559]	100	1			T4	1		T17	1		T129	1
auto[2684354560:2818572287]	105	1			T16	1		T87	1		T49	1
auto[2818572288:2952790015]	88	1			T20	1		T127	1		T303	1
auto[2952790016:3087007743]	110	1			T4	1		T99	2		T27	1
auto[3087007744:3221225471]	104	1			T71	1		T67	1		T95	1
auto[3221225472:3355443199]	111	1			T16	1		T23	1		T19	1
auto[3355443200:3489660927]	103	1			T129	1		T30	1		T49	1
auto[3489660928:3623878655]	109	1			T38	1		T23	1		T64	1
auto[3623878656:3758096383]	100	1			T38	1		T52	1		T87	1
auto[3758096384:3892314111]	103	1			T19	1		T37	1		T85	1
auto[3892314112:4026531839]	109	1			T48	1		T78	1		T34	1
auto[4026531840:4160749567]	89	1			T52	1		T20	1		T99	1
auto[4160749568:4294967295]	107	1			T4	1		T17	1		T20	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	51	1			T37	1		T30	1		T8	1
auto[0:134217727]	auto[1]	59	1			T127	1		T165	1		T212	1
auto[134217728:268435455]	auto[0]	54	1			T48	1		T74	1		T95	1
auto[134217728:268435455]	auto[1]	60	1			T17	1		T38	1		T165	1
auto[268435456:402653183]	auto[0]	63	1			T16	1		T19	1		T27	1
auto[268435456:402653183]	auto[1]	51	1			T87	1		T74	1		T303	1
auto[402653184:536870911]	auto[0]	42	1			T17	1		T127	1		T75	1
auto[402653184:536870911]	auto[1]	56	1			T40	1		T28	1		T101	1
auto[536870912:671088639]	auto[0]	53	1			T38	1		T71	2		T74	1
auto[536870912:671088639]	auto[1]	48	1			T10	1		T303	1		T260	2
auto[671088640:805306367]	auto[0]	44	1			T48	1		T71	1		T69	1
auto[671088640:805306367]	auto[1]	64	1			T71	1		T35	1		T260	1
auto[805306368:939524095]	auto[0]	46	1			T23	1		T85	1		T146	1
auto[805306368:939524095]	auto[1]	53	1			T20	1		T74	1		T165	1
auto[939524096:1073741823]	auto[0]	42	1			T16	1		T69	1		T210	1
auto[939524096:1073741823]	auto[1]	47	1			T4	1		T81	1		T252	1
auto[1073741824:1207959551]	auto[0]	35	1			T127	1		T27	1		T101	1
auto[1073741824:1207959551]	auto[1]	50	1			T23	1		T64	1		T144	1
auto[1207959552:1342177279]	auto[0]	53	1			T74	1		T45	1		T285	1
auto[1207959552:1342177279]	auto[1]	57	1			T16	1		T69	1		T101	1
auto[1342177280:1476395007]	auto[0]	45	1			T52	1		T27	1		T34	1
auto[1342177280:1476395007]	auto[1]	61	1			T38	1		T144	1		T68	1
auto[1476395008:1610612735]	auto[0]	54	1			T16	1		T21	1		T95	1
auto[1476395008:1610612735]	auto[1]	48	1			T17	1		T10	1		T69	1
auto[1610612736:1744830463]	auto[0]	55	1			T17	1		T21	1		T48	1
auto[1610612736:1744830463]	auto[1]	55	1			T287	1		T152	1		T65	1
auto[1744830464:1879048191]	auto[0]	60	1			T38	1		T7	1		T101	1
auto[1744830464:1879048191]	auto[1]	53	1			T17	1		T38	1		T69	1
auto[1879048192:2013265919]	auto[0]	50	1			T17	1		T99	3		T101	1
auto[1879048192:2013265919]	auto[1]	56	1			T19	1		T48	1		T30	1
auto[2013265920:2147483647]	auto[0]	47	1			T209	1		T85	1		T48	1
auto[2013265920:2147483647]	auto[1]	59	1			T165	1		T34	1		T148	1
auto[2147483648:2281701375]	auto[0]	55	1			T30	1		T7	1		T51	1
auto[2147483648:2281701375]	auto[1]	61	1			T4	1		T38	1		T19	1
auto[2281701376:2415919103]	auto[0]	54	1			T4	1		T17	1		T64	1
auto[2281701376:2415919103]	auto[1]	67	1			T40	1		T21	1		T87	1
auto[2415919104:2550136831]	auto[0]	37	1			T78	1		T282	1		T280	2
auto[2415919104:2550136831]	auto[1]	47	1			T127	1		T7	1		T65	1
auto[2550136832:2684354559]	auto[0]	40	1			T129	1		T37	1		T9	2
auto[2550136832:2684354559]	auto[1]	60	1			T4	1		T17	1		T34	1
auto[2684354560:2818572287]	auto[0]	56	1			T16	1		T49	1		T7	1
auto[2684354560:2818572287]	auto[1]	49	1			T87	1		T146	1		T154	1
auto[2818572288:2952790015]	auto[0]	40	1			T20	1		T51	1		T150	1
auto[2818572288:2952790015]	auto[1]	48	1			T127	1		T303	1		T260	1
auto[2952790016:3087007743]	auto[0]	56	1			T99	2		T154	2		T263	1
auto[2952790016:3087007743]	auto[1]	54	1			T4	1		T27	1		T147	1
auto[3087007744:3221225471]	auto[0]	53	1			T71	1		T146	1		T51	1
auto[3087007744:3221225471]	auto[1]	51	1			T67	1		T95	1		T260	1
auto[3221225472:3355443199]	auto[0]	50	1			T16	1		T37	1		T48	1
auto[3221225472:3355443199]	auto[1]	61	1			T23	1		T19	1		T257	1
auto[3355443200:3489660927]	auto[0]	46	1			T30	1		T27	1		T287	1
auto[3355443200:3489660927]	auto[1]	57	1			T129	1		T49	1		T146	1
auto[3489660928:3623878655]	auto[0]	43	1			T38	1		T64	1		T21	1
auto[3489660928:3623878655]	auto[1]	66	1			T23	1		T78	1		T257	1
auto[3623878656:3758096383]	auto[0]	48	1			T52	1		T49	1		T34	1
auto[3623878656:3758096383]	auto[1]	52	1			T38	1		T87	1		T30	1
auto[3758096384:3892314111]	auto[0]	59	1			T37	1		T85	1		T67	1
auto[3758096384:3892314111]	auto[1]	44	1			T19	1		T78	2		T65	1
auto[3892314112:4026531839]	auto[0]	47	1			T48	1		T34	1		T95	1
auto[3892314112:4026531839]	auto[1]	62	1			T78	1		T287	1		T104	1
auto[4026531840:4160749567]	auto[0]	40	1			T52	1		T20	1		T99	1
auto[4026531840:4160749567]	auto[1]	49	1			T21	1		T303	1		T112	2
auto[4160749568:4294967295]	auto[0]	57	1			T95	2		T8	2		T45	2
auto[4160749568:4294967295]	auto[1]	50	1			T4	1		T17	1		T20	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1585

1

T4

2

T16

4

T17

3

auto[1]

1744

1

T4

4

T16

2

T17

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T129	1		T85	1		T87	1
auto[134217728:268435455]	103	1			T37	1		T74	2		T78	1
auto[268435456:402653183]	101	1			T17	1		T20	1		T257	1
auto[402653184:536870911]	128	1			T99	1		T48	1		T71	1
auto[536870912:671088639]	96	1			T127	1		T78	1		T49	1
auto[671088640:805306367]	101	1			T38	2		T7	1		T27	1
auto[805306368:939524095]	103	1			T19	1		T85	1		T10	1
auto[939524096:1073741823]	98	1			T17	1		T19	1		T64	1
auto[1073741824:1207959551]	104	1			T21	1		T75	1		T146	1
auto[1207959552:1342177279]	110	1			T20	1		T49	1		T287	1
auto[1342177280:1476395007]	92	1			T4	1		T16	1		T40	1
auto[1476395008:1610612735]	123	1			T4	1		T16	1		T52	1
auto[1610612736:1744830463]	89	1			T16	1		T99	3		T48	1
auto[1744830464:1879048191]	111	1			T4	1		T17	1		T99	1
auto[1879048192:2013265919]	110	1			T4	1		T17	1		T19	1
auto[2013265920:2147483647]	102	1			T16	1		T38	3		T74	1
auto[2147483648:2281701375]	109	1			T127	1		T74	1		T69	1
auto[2281701376:2415919103]	100	1			T17	1		T64	1		T37	1
auto[2415919104:2550136831]	101	1			T21	1		T303	1		T45	1
auto[2550136832:2684354559]	104	1			T16	1		T19	1		T20	1
auto[2684354560:2818572287]	105	1			T23	1		T48	1		T49	1
auto[2818572288:2952790015]	118	1			T17	1		T23	1		T20	1
auto[2952790016:3087007743]	96	1			T17	1		T30	2		T34	1
auto[3087007744:3221225471]	102	1			T17	1		T38	1		T129	1
auto[3221225472:3355443199]	97	1			T4	1		T52	1		T127	1
auto[3355443200:3489660927]	88	1			T52	1		T48	1		T30	1
auto[3489660928:3623878655]	117	1			T16	1		T38	1		T23	1
auto[3623878656:3758096383]	98	1			T4	1		T38	1		T40	1
auto[3758096384:3892314111]	108	1			T23	1		T37	1		T95	1
auto[3892314112:4026531839]	103	1			T30	1		T7	1		T148	1
auto[4026531840:4160749567]	103	1			T17	1		T209	1		T71	1
auto[4160749568:4294967295]	106	1			T127	1		T64	1		T37	1