Unified Coverage Report :: Group Instance : salt_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2934

1

T4

6

T16

6

T17

9

auto[1]

302

1

T4

2

T127

5

T74

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T34	1		T146	1		T51	2
auto[134217728:268435455]	109	1			T4	1		T129	1		T52	1
auto[268435456:402653183]	111	1			T20	1		T127	1		T27	1
auto[402653184:536870911]	91	1			T23	1		T37	1		T74	1
auto[536870912:671088639]	91	1			T165	1		T35	1		T285	1
auto[671088640:805306367]	95	1			T17	1		T19	1		T48	1
auto[805306368:939524095]	97	1			T127	1		T48	1		T101	1
auto[939524096:1073741823]	121	1			T4	1		T17	1		T38	1
auto[1073741824:1207959551]	89	1			T17	1		T52	1		T99	1
auto[1207959552:1342177279]	110	1			T20	1		T40	1		T21	1
auto[1342177280:1476395007]	89	1			T64	1		T48	1		T10	1
auto[1476395008:1610612735]	103	1			T17	1		T19	1		T52	1
auto[1610612736:1744830463]	118	1			T17	2		T23	1		T20	1
auto[1744830464:1879048191]	101	1			T4	1		T16	1		T38	1
auto[1879048192:2013265919]	120	1			T17	1		T38	1		T37	1
auto[2013265920:2147483647]	117	1			T16	1		T37	1		T48	3
auto[2147483648:2281701375]	98	1			T17	1		T99	2		T85	1
auto[2281701376:2415919103]	90	1			T4	1		T71	1		T49	2
auto[2415919104:2550136831]	100	1			T17	1		T74	3		T257	1
auto[2550136832:2684354559]	94	1			T4	1		T23	1		T99	1
auto[2684354560:2818572287]	104	1			T99	1		T165	1		T7	1
auto[2818572288:2952790015]	101	1			T4	1		T68	1		T28	1
auto[2952790016:3087007743]	105	1			T34	1		T95	1		T147	1
auto[3087007744:3221225471]	87	1			T38	2		T20	1		T127	1
auto[3221225472:3355443199]	102	1			T74	1		T34	1		T69	1
auto[3355443200:3489660927]	105	1			T4	1		T16	1		T19	1
auto[3489660928:3623878655]	90	1			T16	1		T38	1		T48	1
auto[3623878656:3758096383]	94	1			T30	1		T78	2		T287	1
auto[3758096384:3892314111]	106	1			T16	1		T30	1		T74	1
auto[3892314112:4026531839]	105	1			T10	1		T71	1		T74	1
auto[4026531840:4160749567]	91	1			T16	1		T38	1		T23	1
auto[4160749568:4294967295]	94	1			T4	1		T38	1		T19	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	96	1			T34	1		T146	1		T51	2
auto[0:134217727]	auto[1]	12	1			T101	1		T115	1		T429	1
auto[134217728:268435455]	auto[0]	103	1			T4	1		T129	1		T52	1
auto[134217728:268435455]	auto[1]	6	1			T127	1		T113	1		T248	1
auto[268435456:402653183]	auto[0]	99	1			T20	1		T127	1		T27	1
auto[268435456:402653183]	auto[1]	12	1			T101	1		T112	1		T114	1
auto[402653184:536870911]	auto[0]	82	1			T23	1		T37	1		T67	1
auto[402653184:536870911]	auto[1]	9	1			T74	1		T78	1		T247	1
auto[536870912:671088639]	auto[0]	77	1			T165	1		T35	1		T285	1
auto[536870912:671088639]	auto[1]	14	1			T112	1		T247	2		T424	1
auto[671088640:805306367]	auto[0]	87	1			T17	1		T19	1		T48	1
auto[671088640:805306367]	auto[1]	8	1			T101	1		T429	1		T387	1
auto[805306368:939524095]	auto[0]	90	1			T127	1		T48	1		T104	1
auto[805306368:939524095]	auto[1]	7	1			T101	1		T113	2		T247	1
auto[939524096:1073741823]	auto[0]	110	1			T17	1		T38	1		T129	1
auto[939524096:1073741823]	auto[1]	11	1			T4	1		T127	1		T113	1
auto[1073741824:1207959551]	auto[0]	84	1			T17	1		T52	1		T99	1
auto[1073741824:1207959551]	auto[1]	5	1			T115	1		T454	1		T461	1
auto[1207959552:1342177279]	auto[0]	98	1			T20	1		T40	1		T21	1
auto[1207959552:1342177279]	auto[1]	12	1			T78	1		T101	1		T113	1
auto[1342177280:1476395007]	auto[0]	81	1			T64	1		T48	1		T10	1
auto[1342177280:1476395007]	auto[1]	8	1			T74	1		T115	1		T420	1
auto[1476395008:1610612735]	auto[0]	96	1			T17	1		T19	1		T52	1
auto[1476395008:1610612735]	auto[1]	7	1			T247	1		T433	1		T248	1
auto[1610612736:1744830463]	auto[0]	103	1			T17	2		T23	1		T20	1
auto[1610612736:1744830463]	auto[1]	15	1			T101	2		T112	1		T115	1
auto[1744830464:1879048191]	auto[0]	93	1			T4	1		T16	1		T38	1
auto[1744830464:1879048191]	auto[1]	8	1			T252	1		T112	1		T115	1
auto[1879048192:2013265919]	auto[0]	109	1			T17	1		T38	1		T37	1
auto[1879048192:2013265919]	auto[1]	11	1			T74	1		T112	1		T114	1
auto[2013265920:2147483647]	auto[0]	108	1			T16	1		T37	1		T48	3
auto[2013265920:2147483647]	auto[1]	9	1			T101	1		T108	1		T112	1
auto[2147483648:2281701375]	auto[0]	88	1			T17	1		T99	2		T85	1
auto[2147483648:2281701375]	auto[1]	10	1			T424	2		T321	1		T319	1
auto[2281701376:2415919103]	auto[0]	75	1			T71	1		T49	2		T257	1
auto[2281701376:2415919103]	auto[1]	15	1			T4	1		T114	1		T247	2
auto[2415919104:2550136831]	auto[0]	92	1			T17	1		T74	2		T257	1
auto[2415919104:2550136831]	auto[1]	8	1			T74	1		T113	1		T424	1
auto[2550136832:2684354559]	auto[0]	83	1			T4	1		T23	1		T99	1
auto[2550136832:2684354559]	auto[1]	11	1			T78	1		T112	1		T115	2
auto[2684354560:2818572287]	auto[0]	96	1			T99	1		T165	1		T7	1
auto[2684354560:2818572287]	auto[1]	8	1			T101	1		T252	1		T247	1
auto[2818572288:2952790015]	auto[0]	89	1			T4	1		T68	1		T28	1
auto[2818572288:2952790015]	auto[1]	12	1			T101	1		T113	2		T114	1
auto[2952790016:3087007743]	auto[0]	94	1			T34	1		T95	1		T147	1
auto[2952790016:3087007743]	auto[1]	11	1			T101	1		T256	1		T424	3
auto[3087007744:3221225471]	auto[0]	80	1			T38	2		T20	1		T64	1
auto[3087007744:3221225471]	auto[1]	7	1			T127	1		T112	1		T387	2
auto[3221225472:3355443199]	auto[0]	92	1			T74	1		T34	1		T69	1
auto[3221225472:3355443199]	auto[1]	10	1			T101	1		T113	1		T428	1
auto[3355443200:3489660927]	auto[0]	94	1			T4	1		T16	1		T19	1
auto[3355443200:3489660927]	auto[1]	11	1			T127	1		T115	1		T420	1
auto[3489660928:3623878655]	auto[0]	84	1			T16	1		T38	1		T48	1
auto[3489660928:3623878655]	auto[1]	6	1			T113	1		T248	1		T266	1
auto[3623878656:3758096383]	auto[0]	84	1			T30	1		T78	2		T287	1
auto[3623878656:3758096383]	auto[1]	10	1			T101	1		T321	1		T319	1
auto[3758096384:3892314111]	auto[0]	98	1			T16	1		T30	1		T74	1
auto[3758096384:3892314111]	auto[1]	8	1			T101	1		T112	1		T113	1
auto[3892314112:4026531839]	auto[0]	94	1			T10	1		T71	1		T144	1
auto[3892314112:4026531839]	auto[1]	11	1			T74	1		T364	2		T434	1
auto[4026531840:4160749567]	auto[0]	87	1			T16	1		T38	1		T23	1
auto[4026531840:4160749567]	auto[1]	4	1			T78	1		T365	1		T460	1
auto[4160749568:4294967295]	auto[0]	88	1			T4	1		T38	1		T19	1
auto[4160749568:4294967295]	auto[1]	6	1			T127	1		T424	1		T266	3