Unified Coverage Report :: Group Instance : sealing_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1599

1

T4

2

T16

5

T17

4

auto[1]

1730

1

T4

4

T16

1

T17

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	94	1			T52	1		T99	1		T21	1
auto[134217728:268435455]	114	1			T4	1		T17	1		T19	2
auto[268435456:402653183]	106	1			T19	1		T20	1		T40	1
auto[402653184:536870911]	102	1			T23	1		T209	1		T10	1
auto[536870912:671088639]	82	1			T38	2		T20	1		T99	1
auto[671088640:805306367]	101	1			T20	1		T99	1		T165	1
auto[805306368:939524095]	104	1			T19	1		T87	1		T78	1
auto[939524096:1073741823]	104	1			T4	2		T16	2		T17	1
auto[1073741824:1207959551]	98	1			T17	1		T87	1		T257	1
auto[1207959552:1342177279]	116	1			T17	1		T85	1		T71	1
auto[1342177280:1476395007]	122	1			T16	1		T17	1		T30	1
auto[1476395008:1610612735]	111	1			T16	1		T85	1		T165	1
auto[1610612736:1744830463]	120	1			T21	1		T48	1		T71	1
auto[1744830464:1879048191]	94	1			T38	1		T21	1		T30	1
auto[1879048192:2013265919]	98	1			T64	1		T37	1		T10	1
auto[2013265920:2147483647]	103	1			T4	1		T17	1		T48	2
auto[2147483648:2281701375]	109	1			T127	1		T78	1		T69	1
auto[2281701376:2415919103]	108	1			T38	1		T52	1		T78	1
auto[2415919104:2550136831]	100	1			T21	1		T30	1		T74	1
auto[2550136832:2684354559]	104	1			T52	1		T30	1		T7	1
auto[2684354560:2818572287]	115	1			T38	1		T87	1		T30	1
auto[2818572288:2952790015]	92	1			T38	1		T127	1		T64	1
auto[2952790016:3087007743]	103	1			T4	1		T23	1		T99	1
auto[3087007744:3221225471]	109	1			T20	1		T37	1		T48	1
auto[3221225472:3355443199]	93	1			T21	1		T74	1		T49	1
auto[3355443200:3489660927]	100	1			T7	1		T257	1		T51	1
auto[3489660928:3623878655]	102	1			T17	1		T129	2		T30	1
auto[3623878656:3758096383]	123	1			T4	1		T40	1		T48	1
auto[3758096384:3892314111]	99	1			T16	2		T37	1		T48	1
auto[3892314112:4026531839]	92	1			T38	1		T23	1		T19	1
auto[4026531840:4160749567]	113	1			T17	1		T38	1		T64	1
auto[4160749568:4294967295]	98	1			T17	1		T127	2		T144	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T52	1		T99	1		T21	1
auto[0:134217727]	auto[1]	46	1			T87	1		T303	1		T210	1
auto[134217728:268435455]	auto[0]	60	1			T37	1		T99	1		T49	1
auto[134217728:268435455]	auto[1]	54	1			T4	1		T17	1		T19	2
auto[268435456:402653183]	auto[0]	57	1			T19	1		T71	1		T66	1
auto[268435456:402653183]	auto[1]	49	1			T20	1		T40	1		T75	1
auto[402653184:536870911]	auto[0]	50	1			T7	1		T303	1		T101	1
auto[402653184:536870911]	auto[1]	52	1			T23	1		T209	1		T10	1
auto[536870912:671088639]	auto[0]	38	1			T38	1		T20	1		T99	1
auto[536870912:671088639]	auto[1]	44	1			T38	1		T21	1		T67	1
auto[671088640:805306367]	auto[0]	45	1			T99	1		T69	1		T95	1
auto[671088640:805306367]	auto[1]	56	1			T20	1		T165	1		T303	2
auto[805306368:939524095]	auto[0]	46	1			T49	1		T27	1		T287	1
auto[805306368:939524095]	auto[1]	58	1			T19	1		T87	1		T78	1
auto[939524096:1073741823]	auto[0]	52	1			T4	1		T16	2		T99	1
auto[939524096:1073741823]	auto[1]	52	1			T4	1		T17	1		T23	1
auto[1073741824:1207959551]	auto[0]	41	1			T17	1		T9	2		T66	1
auto[1073741824:1207959551]	auto[1]	57	1			T87	1		T257	1		T400	1
auto[1207959552:1342177279]	auto[0]	47	1			T17	1		T85	1		T71	1
auto[1207959552:1342177279]	auto[1]	69	1			T69	1		T66	1		T154	1
auto[1342177280:1476395007]	auto[0]	64	1			T16	1		T17	1		T9	1
auto[1342177280:1476395007]	auto[1]	58	1			T30	1		T78	1		T257	1
auto[1476395008:1610612735]	auto[0]	54	1			T16	1		T85	1		T51	1
auto[1476395008:1610612735]	auto[1]	57	1			T165	1		T104	1		T66	1
auto[1610612736:1744830463]	auto[0]	62	1			T71	1		T143	1		T27	1
auto[1610612736:1744830463]	auto[1]	58	1			T21	1		T48	1		T7	1
auto[1744830464:1879048191]	auto[0]	42	1			T38	1		T30	1		T95	1
auto[1744830464:1879048191]	auto[1]	52	1			T21	1		T144	1		T303	1
auto[1879048192:2013265919]	auto[0]	44	1			T37	1		T51	1		T314	1
auto[1879048192:2013265919]	auto[1]	54	1			T64	1		T10	1		T165	1
auto[2013265920:2147483647]	auto[0]	45	1			T48	2		T7	1		T34	1
auto[2013265920:2147483647]	auto[1]	58	1			T4	1		T17	1		T303	1
auto[2147483648:2281701375]	auto[0]	55	1			T69	1		T8	1		T45	3
auto[2147483648:2281701375]	auto[1]	54	1			T127	1		T78	1		T65	1
auto[2281701376:2415919103]	auto[0]	59	1			T38	1		T69	1		T147	1
auto[2281701376:2415919103]	auto[1]	49	1			T52	1		T78	1		T148	1
auto[2415919104:2550136831]	auto[0]	40	1			T30	1		T74	1		T101	2
auto[2415919104:2550136831]	auto[1]	60	1			T21	1		T27	1		T146	1
auto[2550136832:2684354559]	auto[0]	45	1			T52	1		T7	1		T309	1
auto[2550136832:2684354559]	auto[1]	59	1			T30	1		T212	1		T147	1
auto[2684354560:2818572287]	auto[0]	53	1			T87	1		T71	1		T75	1
auto[2684354560:2818572287]	auto[1]	62	1			T38	1		T30	1		T28	1
auto[2818572288:2952790015]	auto[0]	48	1			T127	1		T64	1		T48	1
auto[2818572288:2952790015]	auto[1]	44	1			T38	1		T69	1		T9	1
auto[2952790016:3087007743]	auto[0]	45	1			T23	1		T99	1		T71	1
auto[2952790016:3087007743]	auto[1]	58	1			T4	1		T34	1		T45	1
auto[3087007744:3221225471]	auto[0]	55	1			T20	1		T37	1		T75	1
auto[3087007744:3221225471]	auto[1]	54	1			T48	1		T71	1		T287	1
auto[3221225472:3355443199]	auto[0]	46	1			T21	1		T49	1		T34	1
auto[3221225472:3355443199]	auto[1]	47	1			T74	1		T212	1		T66	1
auto[3355443200:3489660927]	auto[0]	39	1			T7	1		T51	1		T101	1
auto[3355443200:3489660927]	auto[1]	61	1			T257	1		T210	2		T435	1
auto[3489660928:3623878655]	auto[0]	55	1			T17	1		T129	2		T74	1
auto[3489660928:3623878655]	auto[1]	47	1			T30	1		T95	1		T28	1
auto[3623878656:3758096383]	auto[0]	63	1			T4	1		T48	1		T69	1
auto[3623878656:3758096383]	auto[1]	60	1			T40	1		T95	1		T65	1
auto[3758096384:3892314111]	auto[0]	57	1			T16	1		T37	1		T48	1
auto[3758096384:3892314111]	auto[1]	42	1			T16	1		T68	1		T148	1
auto[3892314112:4026531839]	auto[0]	42	1			T19	1		T127	1		T85	1
auto[3892314112:4026531839]	auto[1]	50	1			T38	1		T23	1		T165	1
auto[4026531840:4160749567]	auto[0]	47	1			T64	1		T95	1		T441	1
auto[4026531840:4160749567]	auto[1]	66	1			T17	1		T38	1		T287	1
auto[4160749568:4294967295]	auto[0]	55	1			T144	1		T95	1		T152	1
auto[4160749568:4294967295]	auto[1]	43	1			T17	1		T127	2		T111	1