Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6831

1

T4

11

T16

14

T17

16

auto[1]

296

1

T4

4

T127

6

T74

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2872	1			T4	5		T16	6		T17	6
auto[134217728:268435455]	153	1			T38	1		T87	2		T49	1
auto[268435456:402653183]	147	1			T38	1		T52	1		T74	1
auto[402653184:536870911]	136	1			T16	1		T19	2		T99	1
auto[536870912:671088639]	171	1			T17	2		T129	1		T20	1
auto[671088640:805306367]	147	1			T17	1		T23	2		T129	1
auto[805306368:939524095]	144	1			T16	1		T19	2		T40	1
auto[939524096:1073741823]	133	1			T38	1		T127	1		T21	1
auto[1073741824:1207959551]	139	1			T4	1		T16	1		T30	1
auto[1207959552:1342177279]	125	1			T16	1		T127	2		T85	1
auto[1342177280:1476395007]	119	1			T19	2		T52	2		T127	1
auto[1476395008:1610612735]	137	1			T19	1		T10	1		T74	1
auto[1610612736:1744830463]	144	1			T85	1		T87	1		T165	1
auto[1744830464:1879048191]	141	1			T16	1		T23	1		T19	2
auto[1879048192:2013265919]	125	1			T38	1		T37	1		T85	1
auto[2013265920:2147483647]	130	1			T23	1		T19	1		T21	1
auto[2147483648:2281701375]	142	1			T38	1		T30	1		T257	1
auto[2281701376:2415919103]	141	1			T4	1		T52	1		T127	1
auto[2415919104:2550136831]	134	1			T4	1		T52	1		T209	1
auto[2550136832:2684354559]	130	1			T4	1		T38	1		T20	1
auto[2684354560:2818572287]	145	1			T4	3		T38	1		T48	1
auto[2818572288:2952790015]	118	1			T17	1		T23	1		T37	1
auto[2952790016:3087007743]	140	1			T99	1		T21	1		T48	1
auto[3087007744:3221225471]	124	1			T4	1		T16	1		T17	1
auto[3221225472:3355443199]	144	1			T17	1		T52	1		T127	1
auto[3355443200:3489660927]	131	1			T19	1		T20	2		T99	1
auto[3489660928:3623878655]	130	1			T37	1		T99	1		T48	1
auto[3623878656:3758096383]	131	1			T38	1		T19	3		T30	2
auto[3758096384:3892314111]	124	1			T16	1		T17	2		T20	1
auto[3892314112:4026531839]	126	1			T4	1		T17	1		T21	1
auto[4026531840:4160749567]	168	1			T4	1		T17	1		T23	1
auto[4160749568:4294967295]	136	1			T16	1		T64	1		T68	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2864	1			T4	5		T16	6		T17	6
auto[0:134217727]	auto[1]	8	1			T113	1		T247	1		T371	1
auto[134217728:268435455]	auto[0]	149	1			T38	1		T87	2		T49	1
auto[134217728:268435455]	auto[1]	4	1			T101	1		T247	1		T407	1
auto[268435456:402653183]	auto[0]	135	1			T38	1		T52	1		T78	1
auto[268435456:402653183]	auto[1]	12	1			T74	1		T101	1		T112	2
auto[402653184:536870911]	auto[0]	127	1			T16	1		T19	2		T99	1
auto[402653184:536870911]	auto[1]	9	1			T101	1		T113	1		T247	1
auto[536870912:671088639]	auto[0]	163	1			T17	2		T129	1		T20	1
auto[536870912:671088639]	auto[1]	8	1			T74	1		T112	1		T247	1
auto[671088640:805306367]	auto[0]	137	1			T17	1		T23	2		T129	1
auto[671088640:805306367]	auto[1]	10	1			T127	1		T74	1		T78	2
auto[805306368:939524095]	auto[0]	136	1			T16	1		T19	2		T40	1
auto[805306368:939524095]	auto[1]	8	1			T113	1		T247	1		T428	1
auto[939524096:1073741823]	auto[0]	123	1			T38	1		T21	1		T30	1
auto[939524096:1073741823]	auto[1]	10	1			T127	1		T78	1		T112	2
auto[1073741824:1207959551]	auto[0]	126	1			T16	1		T30	1		T144	1
auto[1073741824:1207959551]	auto[1]	13	1			T4	1		T256	1		T424	1
auto[1207959552:1342177279]	auto[0]	117	1			T16	1		T127	2		T85	1
auto[1207959552:1342177279]	auto[1]	8	1			T74	2		T247	1		T429	1
auto[1342177280:1476395007]	auto[0]	111	1			T19	2		T52	2		T64	1
auto[1342177280:1476395007]	auto[1]	8	1			T127	1		T247	1		T115	1
auto[1476395008:1610612735]	auto[0]	127	1			T19	1		T10	1		T287	1
auto[1476395008:1610612735]	auto[1]	10	1			T74	1		T101	1		T115	1
auto[1610612736:1744830463]	auto[0]	139	1			T85	1		T87	1		T165	1
auto[1610612736:1744830463]	auto[1]	5	1			T256	2		T248	1		T326	1
auto[1744830464:1879048191]	auto[0]	133	1			T16	1		T23	1		T19	2
auto[1744830464:1879048191]	auto[1]	8	1			T78	1		T252	1		T112	1
auto[1879048192:2013265919]	auto[0]	116	1			T38	1		T37	1		T85	1
auto[1879048192:2013265919]	auto[1]	9	1			T113	1		T424	2		T319	1
auto[2013265920:2147483647]	auto[0]	123	1			T23	1		T19	1		T21	1
auto[2013265920:2147483647]	auto[1]	7	1			T113	1		T247	1		T424	1
auto[2147483648:2281701375]	auto[0]	134	1			T38	1		T30	1		T257	1
auto[2147483648:2281701375]	auto[1]	8	1			T113	1		T429	1		T424	1
auto[2281701376:2415919103]	auto[0]	131	1			T4	1		T52	1		T99	1
auto[2281701376:2415919103]	auto[1]	10	1			T127	1		T78	1		T113	1
auto[2415919104:2550136831]	auto[0]	124	1			T52	1		T209	1		T74	1
auto[2415919104:2550136831]	auto[1]	10	1			T4	1		T78	1		T101	1
auto[2550136832:2684354559]	auto[0]	119	1			T38	1		T20	1		T99	1
auto[2550136832:2684354559]	auto[1]	11	1			T4	1		T74	1		T247	1
auto[2684354560:2818572287]	auto[0]	139	1			T4	3		T38	1		T48	1
auto[2684354560:2818572287]	auto[1]	6	1			T78	1		T247	1		T115	1
auto[2818572288:2952790015]	auto[0]	107	1			T17	1		T23	1		T37	1
auto[2818572288:2952790015]	auto[1]	11	1			T247	1		T429	1		T424	2
auto[2952790016:3087007743]	auto[0]	128	1			T99	1		T21	1		T48	1
auto[2952790016:3087007743]	auto[1]	12	1			T247	1		T420	1		T429	1
auto[3087007744:3221225471]	auto[0]	111	1			T4	1		T16	1		T17	1
auto[3087007744:3221225471]	auto[1]	13	1			T127	1		T74	1		T112	1
auto[3221225472:3355443199]	auto[0]	131	1			T17	1		T52	1		T127	1
auto[3221225472:3355443199]	auto[1]	13	1			T78	1		T115	1		T420	1
auto[3355443200:3489660927]	auto[0]	121	1			T19	1		T20	2		T99	1
auto[3355443200:3489660927]	auto[1]	10	1			T112	1		T113	1		T247	1
auto[3489660928:3623878655]	auto[0]	119	1			T37	1		T99	1		T48	1
auto[3489660928:3623878655]	auto[1]	11	1			T252	1		T115	1		T256	1
auto[3623878656:3758096383]	auto[0]	122	1			T38	1		T19	3		T30	2
auto[3623878656:3758096383]	auto[1]	9	1			T78	1		T429	2		T371	1
auto[3758096384:3892314111]	auto[0]	116	1			T16	1		T17	2		T20	1
auto[3758096384:3892314111]	auto[1]	8	1			T78	2		T108	1		T424	1
auto[3892314112:4026531839]	auto[0]	118	1			T17	1		T21	1		T30	1
auto[3892314112:4026531839]	auto[1]	8	1			T4	1		T78	1		T247	1
auto[4026531840:4160749567]	auto[0]	160	1			T4	1		T17	1		T23	1
auto[4026531840:4160749567]	auto[1]	8	1			T127	1		T112	2		T115	1
auto[4160749568:4294967295]	auto[0]	125	1			T16	1		T64	1		T68	1
auto[4160749568:4294967295]	auto[1]	11	1			T252	1		T247	1		T115	1