Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
74.60	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

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Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	15	34	69.39

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	14	21	60.00	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	59	1			T15	1		T26	1		T57	1
auto[OpGenId]	11	1			T42	1		T237	1		T238	1
auto[OpGenSwOut]	23	1			T27	1		T70	1		T114	1
auto[OpGenHwOut]	14	1			T6	1		T7	1		T8	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1640	1			T11	180		T26	2		T12	90
auto[StInit]	97	1			T31	1		T49	1		T28	1
auto[StCreatorRootKey]	50	1			T19	1		T26	1		T27	1
auto[StOwnerIntKey]	51	1			T15	1		T37	1		T26	1
auto[StOwnerKey]	32	1			T26	1		T39	1		T40	1
auto[StDisabled]	481	1			T26	5		T27	2		T70	2
auto[StInvalid]	49	1			T38	1		T48	1		T107	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3375

1

T1

1

T2

1

T3

1

auto[1]

107

1

T15

1

T26

1

T27

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1632	1			T11	180		T26	2		T12	90
auto[StReset]	auto[1]	8	1			T43	1		T61	1		T33	1
auto[StInit]	auto[0]	51	1			T31	1		T49	1		T28	1
auto[StInit]	auto[1]	46	1			T29	1		T10	1		T237	1
auto[StCreatorRootKey]	auto[0]	31	1			T19	1		T53	1		T114	1
auto[StCreatorRootKey]	auto[1]	19	1			T26	1		T27	1		T9	1
auto[StOwnerIntKey]	auto[0]	37	1			T37	1		T26	1		T233	1
auto[StOwnerIntKey]	auto[1]	14	1			T15	1		T57	1		T70	1
auto[StOwnerKey]	auto[0]	24	1			T26	1		T39	1		T40	1
auto[StOwnerKey]	auto[1]	8	1			T239	1		T240	1		T241	1
auto[StDisabled]	auto[0]	469	1			T26	5		T27	2		T70	2
auto[StDisabled]	auto[1]	12	1			T59	1		T60	1		T54	1
auto[StInvalid]	auto[0]	49	1			T38	1		T48	1		T107	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	14	21	60.00	14

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey] , auto[StDisabled]]	[auto[OpDisable]]	--	--	5

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	8	1			T43	1		T61	1		T33	1
auto[StInit]	auto[OpAdvance]	22	1			T29	1		T10	1		T242	1
auto[StInit]	auto[OpGenId]	6	1			T237	1		T243	1		T244	1
auto[StInit]	auto[OpGenSwOut]	11	1			T245	1		T127	1		T246	1
auto[StInit]	auto[OpGenHwOut]	7	1			T8	1		T247	1		T248	1
auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T26	1		T9	1		T59	2
auto[StCreatorRootKey]	auto[OpGenId]	2	1			T42	1		T249	1		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T27	1		T250	1		T81	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	2	1			T7	1		T251	1		-	-
auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T15	1		T57	1		T146	1
auto[StOwnerIntKey]	auto[OpGenId]	1	1			T238	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	2	1			T70	1		T252	1		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	2	1			T6	1		T253	1		-	-
auto[StOwnerKey]	auto[OpAdvance]	5	1			T240	1		T241	1		T205	1
auto[StOwnerKey]	auto[OpGenId]	1	1			T239	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T254	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T252	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	6	1			T59	1		T60	1		T54	1
auto[StDisabled]	auto[OpGenId]	1	1			T189	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	3	1			T114	1		T178	1		T255	1
auto[StDisabled]	auto[OpGenHwOut]	2	1			T256	1		T257	1		-	-