Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4473

1

T1

4

T3

8

T4

4

auto[1]

551

1

T18

1

T19

1

T112

6

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4473

1

T1

4

T3

8

T4

4

auto[1]

551

1

T18

1

T19

1

T112

6

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4510

1

T1

1

T3

5

T4

3

auto[1]

514

1

T1

3

T3

3

T4

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4510

1

T1

1

T3

5

T4

3

auto[1]

514

1

T1

3

T3

3

T4

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	403	1			T14	1		T74	1		T19	2
auto[OpGenId]	1037	1			T1	2		T4	1		T14	1
auto[OpGenSwOut]	1042	1			T1	1		T4	2		T14	1
auto[OpGenHwOut]	2472	1			T1	1		T3	8		T15	1
auto[OpDisable]	70	1			T4	1		T129	1		T116	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	403	1			T14	1		T74	1		T19	2
auto[OpGenId]	1037	1			T1	2		T4	1		T14	1
auto[OpGenSwOut]	1042	1			T1	1		T4	2		T14	1
auto[OpGenHwOut]	2472	1			T1	1		T3	8		T15	1
auto[OpDisable]	70	1			T4	1		T129	1		T116	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4491

1

T1

4

T3

8

T4

4

auto[1]

533

1

T18

2

T36

2

T129

2

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4491

1

T1

4

T3

8

T4

4

auto[1]

533

1

T18

2

T36

2

T129

2

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4782

1

T1

4

T3

8

T4

4

auto[1]

242

1

T91

7

T73

2

T64

2

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1744	1			T1	2		T3	2		T4	2
auto[1]	602	1			T1	1		T3	1		T14	1
auto[2]	703	1			T3	2		T18	1		T35	1
auto[3]	644	1			T3	1		T15	1		T17	1
auto[4]	357	1			T3	1		T4	1		T14	1
auto[5]	350	1			T4	1		T36	1		T218	1
auto[6]	327	1			T1	1		T3	1		T75	2
auto[7]	297	1			T35	2		T112	1		T218	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1331	1			T1	1		T3	2		T4	2
clear_one[1]	602	1			T1	1		T3	1		T14	1
clear_one[2]	703	1			T3	2		T18	1		T35	1
clear_one[3]	644	1			T3	1		T15	1		T17	1
clear_none	1744	1			T1	2		T3	2		T4	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	924	1			T4	2		T15	3		T35	2
auto[StInit]	627	1			T3	1		T15	1		T17	1
auto[StCreatorRootKey]	549	1			T1	1		T3	1		T17	1
auto[StOwnerIntKey]	495	1			T3	1		T18	1		T36	1
auto[StOwnerKey]	441	1			T1	1		T3	1		T18	1
auto[StDisabled]	1713	1			T1	2		T3	4		T4	2
auto[StInvalid]	275	1			T14	3		T38	5		T39	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	924	1			T4	2		T15	3		T35	2
auto[StInit]	627	1			T3	1		T15	1		T17	1
auto[StCreatorRootKey]	549	1			T1	1		T3	1		T17	1
auto[StOwnerIntKey]	495	1			T3	1		T18	1		T36	1
auto[StOwnerKey]	441	1			T1	1		T3	1		T18	1
auto[StDisabled]	1713	1			T1	2		T3	4		T4	2
auto[StInvalid]	275	1			T14	3		T38	5		T39	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	57	223	79.64	57

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	4
[auto[1] - auto[4]]	[auto[StReset]]	[auto[OpDisable]]	--	--	4
[auto[1] - auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	16
[auto[1] - auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	4
[auto[5] - auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[5] - auto[6]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[5] - auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[5] - auto[6]]	[auto[StInvalid]]	[auto[OpAdvance]]	--	--	2
[auto[5] - auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	4	1			T91	1		T249	1		T250	1
auto[0]	auto[StReset]	auto[OpGenId]	148	1			T39	1		T205	1		T211	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	135	1			T4	1		T15	1		T35	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	252	1			T15	1		T75	3		T218	1
auto[0]	auto[StInit]	auto[OpAdvance]	45	1			T74	1		T24	1		T50	1
auto[0]	auto[StInit]	auto[OpGenId]	92	1			T19	1		T116	1		T26	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	86	1			T207	1		T126	1		T60	2
auto[0]	auto[StInit]	auto[OpGenHwOut]	180	1			T3	1		T17	1		T36	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	25	1			T91	1		T251	1		T134	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	49	1			T60	1		T252	1		T94	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	55	1			T18	1		T60	1		T94	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	64	1			T1	1		T3	1		T112	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	13	1			T156	1		T253	1		T79	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	32	1			T69	1		T209	1		T93	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	25	1			T208	1		T30	1		T94	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	43	1			T216	1		T221	1		T254	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T19	1		T76	1		T196	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	24	1			T1	1		T254	1		T255	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	18	1			T94	1		T256	1		T249	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	45	1			T129	1		T113	1		T91	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	35	1			T73	1		T48	1		T60	1
auto[0]	auto[StDisabled]	auto[OpGenId]	57	1			T4	1		T26	1		T210	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	59	1			T26	1		T70	1		T48	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	138	1			T112	1		T113	2		T216	2
auto[0]	auto[StDisabled]	auto[OpDisable]	23	1			T126	1		T60	1		T213	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	10	1			T66	1		T257	1		T258	1
auto[0]	auto[StInvalid]	auto[OpGenId]	26	1			T14	1		T38	1		T114	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	23	1			T39	1		T101	2		T259	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	27	1			T114	1		T101	1		T102	1
auto[1]	auto[StReset]	auto[OpGenId]	13	1			T260	2		T261	1		T110	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	11	1			T222	1		T262	1		T263	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	33	1			T219	3		T264	1		T265	1
auto[1]	auto[StInit]	auto[OpAdvance]	7	1			T78	3		T130	1		T266	1
auto[1]	auto[StInit]	auto[OpGenId]	5	1			T222	1		T267	1		T268	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	10	1			T15	1		T53	1		T228	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	23	1			T216	1		T138	1		T269	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T156	2		T226	1		T270	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T60	1		T271	1		T188	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T21	1		T271	1		T220	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	32	1			T216	1		T61	1		T272	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T196	1		T273	1		T274	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T275	1		T276	1		T274	3
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T156	1		T277	1		T278	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	46	1			T113	1		T61	1		T272	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T222	1		T279	1		T188	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	14	1			T276	1		T280	1		T281	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T18	1		T73	1		T93	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	28	1			T264	1		T30	1		T94	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	20	1			T19	1		T60	1		T253	1
auto[1]	auto[StDisabled]	auto[OpGenId]	45	1			T254	1		T94	1		T282	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	45	1			T1	1		T126	1		T95	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	142	1			T3	1		T36	1		T75	1
auto[1]	auto[StDisabled]	auto[OpDisable]	6	1			T60	1		T262	1		T141	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	2	1			T101	1		T283	1		-	-
auto[1]	auto[StInvalid]	auto[OpGenId]	10	1			T38	1		T259	1		T284	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	17	1			T14	1		T39	2		T285	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T66	1		T286	1		T287	1
auto[2]	auto[StReset]	auto[OpGenId]	24	1			T35	1		T5	2		T114	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	12	1			T60	1		T53	2		T288	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	48	1			T75	1		T113	2		T60	1
auto[2]	auto[StInit]	auto[OpAdvance]	4	1			T289	1		T290	1		T291	1
auto[2]	auto[StInit]	auto[OpGenId]	13	1			T292	1		T44	1		T52	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	8	1			T277	1		T196	1		T243	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	21	1			T218	1		T219	1		T60	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T196	1		T280	1		T8	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T116	1		T206	1		T293	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	17	1			T152	1		T277	1		T294	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	45	1			T75	1		T264	1		T295	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T296	1		T297	1		T240	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T252	1		T196	1		T130	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T298	1		T290	2		T299	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	46	1			T18	1		T112	1		T218	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T209	1		T252	1		T196	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	8	1			T196	1		T300	1		T197	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T49	1		T278	1		T301	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	38	1			T3	1		T216	1		T207	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	33	1			T51	1		T196	1		T302	4
auto[2]	auto[StDisabled]	auto[OpGenId]	45	1			T94	1		T222	1		T196	2
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	56	1			T207	1		T60	1		T94	3
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	168	1			T3	1		T36	1		T19	1
auto[2]	auto[StDisabled]	auto[OpDisable]	10	1			T129	1		T303	1		T55	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	6	1			T39	1		T259	1		T285	1
auto[2]	auto[StInvalid]	auto[OpGenId]	11	1			T38	1		T66	1		T101	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T304	1		T258	1		T285	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T102	1		T305	1		T306	1
auto[3]	auto[StReset]	auto[OpGenId]	18	1			T23	1		T269	1		T27	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	25	1			T15	1		T138	1		T277	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	34	1			T75	1		T113	1		T217	1
auto[3]	auto[StInit]	auto[OpAdvance]	8	1			T24	1		T53	1		T143	1
auto[3]	auto[StInit]	auto[OpGenId]	10	1			T60	1		T307	1		T303	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	12	1			T23	1		T156	2		T308	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	23	1			T75	1		T113	1		T217	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T91	2		T307	1		T156	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T17	1		T95	1		T21	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T53	1		T309	1		T310	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	34	1			T36	1		T219	1		T60	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T60	1		T222	1		T311	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T91	2		T312	1		T55	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T313	1		T314	1		T315	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	32	1			T205	1		T217	1		T264	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T263	1		T270	1		T316	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	8	1			T196	1		T181	1		T228	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T152	1		T317	1		T318	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	43	1			T36	1		T295	1		T319	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	25	1			T60	1		T94	1		T256	1
auto[3]	auto[StDisabled]	auto[OpGenId]	40	1			T18	1		T60	1		T307	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	49	1			T91	1		T60	1		T95	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	149	1			T3	1		T36	2		T75	1
auto[3]	auto[StDisabled]	auto[OpDisable]	15	1			T48	1		T50	1		T128	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	6	1			T269	1		T306	1		T320	1
auto[3]	auto[StInvalid]	auto[OpGenId]	9	1			T286	1		T321	1		T322	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T102	1		T305	1		T323	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	15	1			T114	1		T71	1		T66	1
auto[4]	auto[StReset]	auto[OpGenId]	12	1			T60	1		T21	1		T136	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	13	1			T94	1		T220	1		T267	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	25	1			T324	1		T259	1		T325	1
auto[4]	auto[StInit]	auto[OpAdvance]	1	1			T326	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenId]	2	1			T96	1		T224	1		-	-
auto[4]	auto[StInit]	auto[OpGenSwOut]	7	1			T211	1		T222	1		T144	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	8	1			T265	1		T94	1		T319	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T275	1		T182	1		T108	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T94	1		T327	1		T328	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T49	1		T94	1		T329	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T113	1		T221	1		T330	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T136	1		T331	1		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T19	1		T51	1		T271	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T332	1		T329	1		T333	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T3	1		T75	1		T60	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T297	1		-	-		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	6	1			T260	1		T136	1		T334	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T60	1		T55	1		T143	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	29	1			T218	1		T335	1		T336	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	4	1			T156	1		T279	1		T337	1
auto[4]	auto[StDisabled]	auto[OpGenId]	27	1			T211	1		T58	1		T338	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	35	1			T98	2		T312	1		T339	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	67	1			T217	2		T272	1		T265	1
auto[4]	auto[StDisabled]	auto[OpDisable]	5	1			T4	1		T157	1		T128	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	7	1			T14	1		T259	1		T340	1
auto[4]	auto[StInvalid]	auto[OpGenId]	5	1			T305	1		T323	1		T341	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T66	1		T304	1		T261	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T259	1		T133	1		T287	1
auto[5]	auto[StReset]	auto[OpGenId]	12	1			T259	1		T253	1		T220	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	9	1			T4	1		T94	1		T186	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	21	1			T113	1		T342	1		T343	1
auto[5]	auto[StInit]	auto[OpAdvance]	4	1			T24	1		T136	1		T344	1
auto[5]	auto[StInit]	auto[OpGenId]	3	1			T334	1		T345	1		T346	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	4	1			T23	1		T148	1		T297	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	9	1			T63	1		T246	1		T347	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T196	1		T348	1		T349	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T350	1		T334	1		T351	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T93	1		T94	1		T50	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	24	1			T265	1		T342	1		T336	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T243	1		T352	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T344	1		T231	1		T147	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T206	1		T262	1		T196	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	17	1			T36	1		T26	1		T265	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T353	2		-	-		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	10	1			T94	1		T78	1		T222	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T354	1		T334	1		T355	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T61	1		T63	1		T272	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	9	1			T222	1		T356	1		T357	1
auto[5]	auto[StDisabled]	auto[OpGenId]	29	1			T94	1		T317	1		T196	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	21	1			T252	1		T215	1		T222	2
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	88	1			T218	1		T113	1		T217	1
auto[5]	auto[StDisabled]	auto[OpDisable]	2	1			T358	1		T240	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	5	1			T321	1		T341	1		T359	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T38	1		T71	1		T360	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T114	1		T361	1		T306	1
auto[6]	auto[StReset]	auto[OpGenId]	9	1			T304	1		T362	1		T334	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	9	1			T256	1		T363	1		T364	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	23	1			T216	1		T217	1		T219	1
auto[6]	auto[StInit]	auto[OpAdvance]	5	1			T302	2		T244	2		T365	1
auto[6]	auto[StInit]	auto[OpGenId]	3	1			T302	1		T366	1		T367	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	1	1			T260	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenHwOut]	8	1			T339	1		T342	1		T368	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T24	1		T359	1		T369	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T140	1		T222	1		T370	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T136	1		T371	1		T144	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T372	1		T325	1		T373	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T23	1		T374	1		T375	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T94	1		T302	1		T53	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T60	1		T95	1		T279	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T138	1		T342	1		T336	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T236	1		T376	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	9	1			T277	1		T302	1		T266	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T377	1		-	-		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T75	1		T219	1		T378	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	8	1			T91	1		T311	1		T302	1
auto[6]	auto[StDisabled]	auto[OpGenId]	21	1			T1	1		T91	2		T60	2
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T26	1		T207	1		T379	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	83	1			T3	1		T75	1		T91	1
auto[6]	auto[StDisabled]	auto[OpDisable]	7	1			T94	2		T380	1		T143	1
auto[6]	auto[StInvalid]	auto[OpGenId]	7	1			T284	1		T361	1		T97	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T38	1		T286	1		T381	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T66	1		T102	1		T322	1
auto[7]	auto[StReset]	auto[OpGenId]	8	1			T382	1		T306	1		T383	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	7	1			T215	1		T311	1		T301	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	19	1			T60	2		T215	1		T222	1
auto[7]	auto[StInit]	auto[OpAdvance]	2	1			T311	1		T164	1		-	-
auto[7]	auto[StInit]	auto[OpGenId]	5	1			T95	1		T275	1		T222	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	6	1			T355	1		T384	1		T385	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	12	1			T253	1		T386	1		T387	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T64	1		T385	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T58	1		T388	1		T389	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T164	1		T231	1		T352	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T218	1		T378	1		T319	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T307	1		T384	1		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T211	1		T73	1		T390	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T288	1		T266	2		T357	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T335	1		T201	1		T391	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T392	1		T351	1		T393	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	4	1			T394	1		T395	1		T396	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T55	1		T397	1		T316	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T112	1		T94	2		T343	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	2	1			T351	1		T398	1		-	-
auto[7]	auto[StDisabled]	auto[OpGenId]	22	1			T35	1		T64	1		T94	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	27	1			T116	1		T94	1		T128	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	69	1			T35	1		T219	1		T221	1
auto[7]	auto[StDisabled]	auto[OpDisable]	2	1			T116	1		T48	1		-	-
auto[7]	auto[StInvalid]	auto[OpAdvance]	2	1			T381	1		T399	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	3	1			T284	1		T400	1		T401	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T305	1		T320	1		T402	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T304	1		T284	1		T99	1