Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1362	1			T2	2		T3	3		T4	5
clear_all	auto[1]	85	1			T46	2		T138	2		T297	9
clear_one[1]	auto[0]	699	1			T4	1		T14	3		T16	1
clear_one[1]	auto[1]	34	1			T137	2		T138	1		T279	1
clear_one[2]	auto[0]	684	1			T3	2		T5	1		T14	2
clear_one[2]	auto[1]	17	1			T279	1		T284	1		T419	1
clear_one[3]	auto[0]	635	1			T4	3		T5	1		T14	2
clear_one[3]	auto[1]	44	1			T46	2		T135	12		T420	1
clear_none	auto[0]	1786	1			T2	1		T3	3		T4	2
clear_none	auto[1]	119	1			T46	4		T119	2		T135	1