Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

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Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1331

1

T1

1

T3

2

T4

2

clear_one[1]

auto[0]

auto[0]

auto[0]

354

1

T14

1

T15

1

T19

1

clear_one[1]

auto[0]

auto[0]

auto[1]

95

1

T18

1

T36

1

T113

1

clear_one[1]

auto[0]

auto[1]

auto[0]

111

1

T1

1

T3

1

T75

1

clear_one[1]

auto[0]

auto[1]

auto[1]

42

1

T256

1

T50

1

T150

1

clear_one[2]

auto[0]

auto[0]

auto[0]

385

1

T3

2

T35

1

T75

3

clear_one[2]

auto[0]

auto[0]

auto[1]

119

1

T18

1

T36

1

T26

1

clear_one[2]

auto[1]

auto[0]

auto[0]

135

1

T19

1

T112

2

T216

2

clear_one[2]

auto[1]

auto[0]

auto[1]

64

1

T129

1

T207

2

T379

1

clear_one[3]

auto[0]

auto[0]

auto[0]

386

1

T15

1

T36

4

T75

2

clear_one[3]

auto[0]

auto[1]

auto[0]

108

1

T3

1

T17

1

T75

1

clear_one[3]

auto[1]

auto[0]

auto[0]

105

1

T18

1

T112

2

T216

1

clear_one[3]

auto[1]

auto[1]

auto[0]

45

1

T94

1

T275

1

T249

1

clear_none

auto[0]

auto[0]

auto[0]

1269

1

T3

1

T4

1

T14

1

clear_none

auto[0]

auto[0]

auto[1]

125

1

T113

3

T91

1

T272

1

clear_none

auto[0]

auto[1]

auto[0]

120

1

T1

2

T3

1

T4

1

clear_none

auto[0]

auto[1]

auto[1]

28

1

T48

1

T210

1

T128

1

clear_none

auto[1]

auto[0]

auto[0]

108

1

T112

2

T216

3

T217

2

clear_none

auto[1]

auto[0]

auto[1]

34

1

T129

1

T73

1

T94

1

clear_none

auto[1]

auto[1]

auto[0]

34

1

T208

1

T128

3

T222

1

clear_none

auto[1]

auto[1]

auto[1]

26

1

T70

1

T379

1

T93

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1266	1			T1	1		T3	2		T4	2
clear_all	auto[1]	65	1			T91	3		T64	2		T76	1
clear_one[1]	auto[0]	565	1			T1	1		T3	1		T14	1
clear_one[1]	auto[1]	37	1			T76	1		T156	2		T78	4
clear_one[2]	auto[0]	662	1			T3	2		T18	1		T35	1
clear_one[2]	auto[1]	41	1			T302	3		T394	4		T344	1
clear_one[3]	auto[0]	604	1			T3	1		T15	1		T17	1
clear_one[3]	auto[1]	40	1			T91	3		T156	2		T78	4
clear_none	auto[0]	1685	1			T1	2		T3	2		T4	2
clear_none	auto[1]	59	1			T91	1		T73	2		T249	1