Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10549

1

T1

6

T2

5

T3

5

auto[Attestation]

7319

1

T1

2

T2

3

T3

3

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2538	1			T4	4		T15	1		T16	3
auto[Aes]	3301	1			T2	2		T15	3		T16	2
auto[Kmac]	3237	1			T1	4		T2	2		T3	8
auto[Otbn]	3228	1			T1	2		T4	2		T15	4

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7131	1			T1	8		T2	8		T3	8
auto[OpGenId]	5564	1			T1	2		T2	4		T4	6
auto[OpGenSwOut]	5576	1			T1	5		T2	4		T4	4
auto[OpGenHwOut]	6728	1			T1	1		T3	8		T4	5
auto[OpDisable]	132	1			T4	1		T129	1		T116	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10181

1

T1

8

T2

8

T3

8

auto[OpDoneFail]

14950

1

T1

8

T2

8

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6073	1			T1	1		T2	1		T3	1
auto[StInit]	3599	1			T1	2		T2	2		T3	2
auto[StCreatorRootKey]	3098	1			T1	2		T2	2		T3	2
auto[StOwnerIntKey]	2648	1			T1	2		T2	2		T3	2
auto[StOwnerKey]	2330	1			T1	2		T2	2		T3	2
auto[StDisabled]	7383	1			T1	7		T2	7		T3	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	316	1			T4	2		T16	2		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	81	1			T15	1		T91	1		T60	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	94	1			T129	1		T60	1		T64	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	75	1			T205	1		T60	1		T49	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	56	1			T18	1		T129	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	189	1			T16	1		T18	1		T116	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	324	1			T15	3		T17	1		T35	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	116	1			T37	1		T39	1		T126	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	77	1			T16	1		T17	1		T129	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	76	1			T48	1		T60	1		T94	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	56	1			T206	1		T94	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	168	1			T2	1		T26	1		T207	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	319	1			T4	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	104	1			T1	1		T40	1		T68	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	83	1			T15	1		T129	1		T60	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	75	1			T1	1		T26	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	55	1			T73	2		T60	1		T138	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	215	1			T1	1		T2	1		T116	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	314	1			T15	3		T16	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	100	1			T19	1		T5	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	79	1			T129	1		T5	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	61	1			T37	1		T207	1		T205	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	59	1			T60	1		T208	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	210	1			T1	1		T16	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	75	1			T60	2		T50	6		T128	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	100	1			T41	1		T205	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	82	1			T48	1		T209	1		T210	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	65	1			T18	1		T60	2		T62	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	59	1			T35	1		T60	1		T206	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	173	1			T19	1		T207	1		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	72	1			T60	4		T50	4		T128	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	92	1			T16	1		T207	2		T211	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	81	1			T212	1		T60	1		T213	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	78	1			T2	1		T70	1		T208	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	56	1			T60	2		T210	1		T94	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	231	1			T91	1		T26	2		T207	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	67	1			T60	3		T94	1		T50	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	84	1			T18	1		T126	1		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	66	1			T18	2		T64	1		T208	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	68	1			T69	1		T73	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	56	1			T2	1		T48	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	215	1			T16	1		T19	1		T212	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	52	1			T60	1		T50	1		T128	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	95	1			T19	1		T48	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	76	1			T37	1		T207	1		T214	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	71	1			T16	1		T73	1		T60	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	54	1			T91	1		T26	1		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	206	1			T1	1		T4	1		T91	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	254	1			T35	2		T5	1		T211	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	106	1			T5	3		T205	1		T68	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	70	1			T37	1		T39	1		T207	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	50	1			T94	1		T134	1		T215	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	47	1			T207	1		T60	1		T30	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	155	1			T4	1		T91	1		T126	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	477	1			T17	1		T216	2		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	109	1			T217	1		T48	1		T63	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	109	1			T17	1		T19	1		T217	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	93	1			T35	1		T37	1		T205	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	82	1			T211	1		T60	1		T209	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	272	1			T19	1		T112	2		T129	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	421	1			T4	1		T35	1		T75	12
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	104	1			T3	1		T40	1		T205	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	126	1			T17	1		T214	2		T69	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	95	1			T3	1		T18	1		T218	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	82	1			T3	1		T26	1		T60	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	273	1			T3	2		T4	1		T75	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	417	1			T15	1		T17	2		T113	14
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	115	1			T17	1		T37	1		T113	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	94	1			T113	1		T219	1		T64	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	93	1			T113	1		T205	1		T68	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	92	1			T113	1		T207	1		T219	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	275	1			T36	1		T113	2		T91	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	42	1			T60	2		T50	4		T128	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	95	1			T4	1		T18	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	81	1			T35	1		T19	1		T207	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	56	1			T19	1		T207	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	53	1			T129	1		T91	1		T60	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	164	1			T18	3		T19	1		T91	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	57	1			T60	2		T128	2		T220	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	106	1			T112	1		T216	1		T73	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	113	1			T17	1		T112	1		T216	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	96	1			T112	1		T129	1		T216	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	90	1			T112	1		T216	1		T207	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	270	1			T18	1		T35	2		T112	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	51	1			T60	2		T128	1		T220	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	109	1			T17	1		T75	1		T218	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	115	1			T1	1		T3	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	87	1			T75	1		T205	1		T221	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	101	1			T75	1		T218	1		T221	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	266	1			T3	2		T19	1		T75	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	54	1			T60	2		T50	2		T222	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	111	1			T4	1		T36	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	125	1			T17	1		T36	1		T68	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	96	1			T18	1		T36	1		T205	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	104	1			T36	1		T129	1		T91	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	275	1			T35	1		T36	3		T113	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	209	1			T18	1		T129	2		T205	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	602	1			T4	2		T15	1		T16	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	197	1			T16	1		T17	1		T129	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	620	1			T2	1		T15	3		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	200	1			T1	1		T15	1		T129	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	651	1			T1	2		T2	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	191	1			T37	1		T129	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	632	1			T1	1		T15	3		T16	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	196	1			T18	1		T35	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	358	1			T19	1		T41	1		T207	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	194	1			T2	1		T212	1		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	416	1			T16	1		T91	1		T26	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	179	1			T2	1		T18	2		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	377	1			T16	1		T18	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	188	1			T16	1		T37	1		T91	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	366	1			T1	1		T4	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	151	1			T37	1		T207	2		T206	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	531	1			T4	1		T35	2		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	273	1			T17	1		T35	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	869	1			T17	1		T19	1		T112	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	285	1			T3	2		T17	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	816	1			T3	3		T4	2		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	269	1			T113	3		T207	1		T205	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	817	1			T15	1		T17	3		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	173	1			T35	1		T19	1		T129	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	318	1			T4	1		T18	4		T19	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	282	1			T17	1		T112	3		T129	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	450	1			T18	1		T35	2		T112	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	287	1			T1	1		T3	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	442	1			T3	2		T17	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	314	1			T17	1		T18	1		T36	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	451	1			T4	1		T35	1		T36	4