Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11212

1

T1

19

T2

5

T3

4

auto[Attestation]

7850

1

T1

3

T2

3

T3

4

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2783	1			T1	3		T2	1		T5	4
auto[Aes]	3396	1			T1	2		T2	1		T3	8
auto[Kmac]	3391	1			T1	1		T2	1		T5	4
auto[Otbn]	3500	1			T1	3		T2	1		T4	18

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7732	1			T1	8		T2	8		T3	8
auto[OpGenId]	5992	1			T1	13		T2	4		T5	5
auto[OpGenSwOut]	5973	1			T1	9		T2	2		T5	9
auto[OpGenHwOut]	7097	1			T2	2		T3	8		T4	18
auto[OpDisable]	162	1			T18	1		T26	1		T50	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10884

1

T1

8

T2

8

T3

8

auto[OpDoneFail]

16072

1

T1

22

T2

8

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6416	1			T1	15		T2	1		T3	1
auto[StInit]	3828	1			T1	2		T2	2		T3	2
auto[StCreatorRootKey]	3319	1			T1	2		T2	2		T3	2
auto[StOwnerIntKey]	2841	1			T1	2		T2	2		T3	2
auto[StOwnerKey]	2459	1			T1	2		T2	2		T3	2
auto[StDisabled]	8093	1			T1	7		T2	7		T3	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	310	1			T1	2		T36	1		T38	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	106	1			T16	1		T26	2		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	94	1			T16	1		T36	1		T91	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	72	1			T27	1		T222	1		T223	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	60	1			T26	1		T110	1		T224	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	203	1			T5	1		T91	1		T113	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	324	1			T1	1		T18	3		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	98	1			T26	1		T23	2		T225	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	97	1			T36	1		T26	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	61	1			T91	1		T27	3		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	62	1			T5	1		T225	1		T223	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	222	1			T16	3		T46	2		T119	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	337	1			T18	1		T38	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	98	1			T36	1		T226	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	98	1			T15	1		T18	1		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	66	1			T27	1		T70	1		T93	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	68	1			T39	1		T71	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	237	1			T1	1		T26	2		T226	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	342	1			T1	2		T18	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	116	1			T113	1		T119	1		T23	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	78	1			T1	1		T119	1		T227	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	78	1			T2	1		T70	1		T228	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	62	1			T26	1		T113	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	206	1			T16	1		T26	1		T113	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	84	1			T27	3		T53	6		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	90	1			T37	1		T50	1		T23	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	88	1			T15	1		T113	1		T222	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	79	1			T26	1		T113	1		T94	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	58	1			T1	1		T5	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	207	1			T26	1		T27	1		T229	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	70	1			T26	1		T70	1		T53	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	120	1			T1	1		T46	1		T26	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	89	1			T5	1		T18	1		T113	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	88	1			T26	1		T39	1		T92	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	63	1			T5	1		T27	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	201	1			T2	1		T46	1		T91	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	83	1			T70	1		T53	2		T54	5
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	95	1			T110	1		T23	1		T71	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	90	1			T5	1		T36	1		T113	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	69	1			T18	1		T44	1		T228	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	49	1			T225	1		T53	1		T137	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	216	1			T5	1		T46	2		T91	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	63	1			T27	1		T53	2		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	92	1			T27	1		T31	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	118	1			T5	1		T18	1		T37	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	78	1			T26	1		T110	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	56	1			T26	1		T224	1		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	232	1			T5	1		T16	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	260	1			T38	1		T19	3		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	93	1			T94	1		T23	1		T135	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	76	1			T27	1		T113	1		T230	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	64	1			T36	1		T53	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	68	1			T39	1		T230	1		T53	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	195	1			T2	1		T46	1		T26	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	408	1			T18	1		T38	3		T19	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	108	1			T18	1		T46	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	102	1			T3	1		T5	1		T112	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	121	1			T26	1		T112	1		T94	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	96	1			T16	1		T231	1		T232	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	285	1			T3	3		T16	1		T112	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	427	1			T38	3		T37	4		T48	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	123	1			T26	2		T39	1		T23	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	111	1			T5	1		T70	1		T233	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	94	1			T37	1		T26	2		T230	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	86	1			T14	1		T211	1		T223	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	291	1			T14	1		T26	1		T27	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	452	1			T4	10		T38	1		T19	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	128	1			T4	1		T18	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	132	1			T26	1		T111	1		T135	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	113	1			T4	1		T16	1		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	86	1			T46	1		T111	1		T70	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	278	1			T4	2		T26	2		T27	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	66	1			T26	1		T53	5		T59	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	108	1			T5	1		T19	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	75	1			T27	1		T226	1		T135	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	46	1			T26	1		T92	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	45	1			T119	1		T6	1		T8	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	236	1			T5	1		T27	1		T119	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	73	1			T26	1		T27	1		T53	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	117	1			T3	1		T19	1		T27	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	127	1			T26	1		T119	1		T94	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	90	1			T3	1		T26	2		T226	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	101	1			T3	1		T5	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	273	1			T3	1		T16	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	61	1			T26	1		T27	2		T70	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	122	1			T5	1		T14	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	121	1			T2	1		T14	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	85	1			T14	1		T94	1		T234	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	83	1			T235	1		T234	1		T53	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	281	1			T14	3		T46	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	81	1			T70	1		T53	2		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	127	1			T5	1		T36	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	117	1			T4	1		T26	1		T110	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	103	1			T36	3		T222	1		T227	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	78	1			T4	1		T236	1		T70	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	284	1			T4	2		T26	1		T110	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	196	1			T36	1		T91	1		T26	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	649	1			T1	2		T5	1		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	204	1			T5	1		T36	1		T91	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	660	1			T1	1		T16	3		T18	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	220	1			T15	1		T18	1		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	684	1			T1	1		T18	1		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	208	1			T1	1		T2	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	674	1			T1	2		T16	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	206	1			T1	1		T5	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	400	1			T37	1		T26	1		T27	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	231	1			T5	2		T18	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	400	1			T1	1		T2	1		T46	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	193	1			T5	1		T18	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	409	1			T5	1		T46	2		T91	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	233	1			T5	1		T18	1		T37	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	406	1			T5	1		T16	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	189	1			T36	1		T27	1		T113	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	567	1			T2	1		T38	1		T19	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	305	1			T3	1		T5	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	815	1			T3	3		T16	2		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	281	1			T5	1		T14	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	851	1			T14	1		T38	3		T37	4
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	319	1			T4	1		T16	1		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	870	1			T4	13		T18	1		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	155	1			T26	1		T27	1		T119	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	421	1			T5	2		T19	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	305	1			T3	2		T5	1		T26	4
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	476	1			T3	2		T16	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	276	1			T2	1		T14	2		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	477	1			T5	1		T14	4		T46	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	281	1			T4	2		T36	3		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	509	1			T4	2		T5	1		T36	1